1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * AMD SEV header common between the guest and the hypervisor. 4 * 5 * Author: Brijesh Singh <brijesh.singh@amd.com> 6 */ 7 8 #ifndef __ASM_X86_SEV_COMMON_H 9 #define __ASM_X86_SEV_COMMON_H 10 11 #define GHCB_MSR_INFO_POS 0 12 #define GHCB_DATA_LOW 12 13 #define GHCB_MSR_INFO_MASK (BIT_ULL(GHCB_DATA_LOW) - 1) 14 15 #define GHCB_DATA(v) \ 16 (((unsigned long)(v) & ~GHCB_MSR_INFO_MASK) >> GHCB_DATA_LOW) 17 18 /* SEV Information Request/Response */ 19 #define GHCB_MSR_SEV_INFO_RESP 0x001 20 #define GHCB_MSR_SEV_INFO_REQ 0x002 21 #define GHCB_MSR_VER_MAX_POS 48 22 #define GHCB_MSR_VER_MAX_MASK 0xffff 23 #define GHCB_MSR_VER_MIN_POS 32 24 #define GHCB_MSR_VER_MIN_MASK 0xffff 25 #define GHCB_MSR_CBIT_POS 24 26 #define GHCB_MSR_CBIT_MASK 0xff 27 #define GHCB_MSR_SEV_INFO(_max, _min, _cbit) \ 28 ((((_max) & GHCB_MSR_VER_MAX_MASK) << GHCB_MSR_VER_MAX_POS) | \ 29 (((_min) & GHCB_MSR_VER_MIN_MASK) << GHCB_MSR_VER_MIN_POS) | \ 30 (((_cbit) & GHCB_MSR_CBIT_MASK) << GHCB_MSR_CBIT_POS) | \ 31 GHCB_MSR_SEV_INFO_RESP) 32 #define GHCB_MSR_INFO(v) ((v) & 0xfffUL) 33 #define GHCB_MSR_PROTO_MAX(v) (((v) >> GHCB_MSR_VER_MAX_POS) & GHCB_MSR_VER_MAX_MASK) 34 #define GHCB_MSR_PROTO_MIN(v) (((v) >> GHCB_MSR_VER_MIN_POS) & GHCB_MSR_VER_MIN_MASK) 35 36 /* CPUID Request/Response */ 37 #define GHCB_MSR_CPUID_REQ 0x004 38 #define GHCB_MSR_CPUID_RESP 0x005 39 #define GHCB_MSR_CPUID_FUNC_POS 32 40 #define GHCB_MSR_CPUID_FUNC_MASK 0xffffffff 41 #define GHCB_MSR_CPUID_VALUE_POS 32 42 #define GHCB_MSR_CPUID_VALUE_MASK 0xffffffff 43 #define GHCB_MSR_CPUID_REG_POS 30 44 #define GHCB_MSR_CPUID_REG_MASK 0x3 45 #define GHCB_CPUID_REQ_EAX 0 46 #define GHCB_CPUID_REQ_EBX 1 47 #define GHCB_CPUID_REQ_ECX 2 48 #define GHCB_CPUID_REQ_EDX 3 49 #define GHCB_CPUID_REQ(fn, reg) \ 50 (GHCB_MSR_CPUID_REQ | \ 51 (((unsigned long)reg & GHCB_MSR_CPUID_REG_MASK) << GHCB_MSR_CPUID_REG_POS) | \ 52 (((unsigned long)fn) << GHCB_MSR_CPUID_FUNC_POS)) 53 54 /* AP Reset Hold */ 55 #define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 56 #define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 57 58 /* GHCB Hypervisor Feature Request/Response */ 59 #define GHCB_MSR_HV_FT_REQ 0x080 60 #define GHCB_MSR_HV_FT_RESP 0x081 61 62 #define GHCB_MSR_TERM_REQ 0x100 63 #define GHCB_MSR_TERM_REASON_SET_POS 12 64 #define GHCB_MSR_TERM_REASON_SET_MASK 0xf 65 #define GHCB_MSR_TERM_REASON_POS 16 66 #define GHCB_MSR_TERM_REASON_MASK 0xff 67 #define GHCB_SEV_TERM_REASON(reason_set, reason_val) \ 68 (((((u64)reason_set) & GHCB_MSR_TERM_REASON_SET_MASK) << GHCB_MSR_TERM_REASON_SET_POS) | \ 69 ((((u64)reason_val) & GHCB_MSR_TERM_REASON_MASK) << GHCB_MSR_TERM_REASON_POS)) 70 71 #define GHCB_SEV_ES_REASON_GENERAL_REQUEST 0 72 #define GHCB_SEV_ES_REASON_PROTOCOL_UNSUPPORTED 1 73 74 #define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK) 75 76 #endif 77