1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_PROCESSOR_H 3 #define _ASM_X86_PROCESSOR_H 4 5 #include <asm/processor-flags.h> 6 7 /* Forward declaration, a strange C thing */ 8 struct task_struct; 9 struct mm_struct; 10 struct io_bitmap; 11 struct vm86; 12 13 #include <asm/math_emu.h> 14 #include <asm/segment.h> 15 #include <asm/types.h> 16 #include <uapi/asm/sigcontext.h> 17 #include <asm/current.h> 18 #include <asm/cpufeatures.h> 19 #include <asm/page.h> 20 #include <asm/pgtable_types.h> 21 #include <asm/percpu.h> 22 #include <asm/msr.h> 23 #include <asm/desc_defs.h> 24 #include <asm/nops.h> 25 #include <asm/special_insns.h> 26 #include <asm/fpu/types.h> 27 #include <asm/unwind_hints.h> 28 #include <asm/vmxfeatures.h> 29 #include <asm/vdso/processor.h> 30 31 #include <linux/personality.h> 32 #include <linux/cache.h> 33 #include <linux/threads.h> 34 #include <linux/math64.h> 35 #include <linux/err.h> 36 #include <linux/irqflags.h> 37 #include <linux/mem_encrypt.h> 38 39 /* 40 * We handle most unaligned accesses in hardware. On the other hand 41 * unaligned DMA can be quite expensive on some Nehalem processors. 42 * 43 * Based on this we disable the IP header alignment in network drivers. 44 */ 45 #define NET_IP_ALIGN 0 46 47 #define HBP_NUM 4 48 49 /* 50 * These alignment constraints are for performance in the vSMP case, 51 * but in the task_struct case we must also meet hardware imposed 52 * alignment requirements of the FPU state: 53 */ 54 #ifdef CONFIG_X86_VSMP 55 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 56 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 57 #else 58 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state) 59 # define ARCH_MIN_MMSTRUCT_ALIGN 0 60 #endif 61 62 enum tlb_infos { 63 ENTRIES, 64 NR_INFO 65 }; 66 67 extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 68 extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 69 extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 70 extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 71 extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 72 extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 73 extern u16 __read_mostly tlb_lld_1g[NR_INFO]; 74 75 /* 76 * CPU type and hardware bug flags. Kept separately for each CPU. 77 * Members of this structure are referenced in head_32.S, so think twice 78 * before touching them. [mj] 79 */ 80 81 struct cpuinfo_x86 { 82 __u8 x86; /* CPU family */ 83 __u8 x86_vendor; /* CPU vendor */ 84 __u8 x86_model; 85 __u8 x86_stepping; 86 #ifdef CONFIG_X86_64 87 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 88 int x86_tlbsize; 89 #endif 90 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 91 __u32 vmx_capability[NVMXINTS]; 92 #endif 93 __u8 x86_virt_bits; 94 __u8 x86_phys_bits; 95 /* CPUID returned core id bits: */ 96 __u8 x86_coreid_bits; 97 __u8 cu_id; 98 /* Max extended CPUID function supported: */ 99 __u32 extended_cpuid_level; 100 /* Maximum supported CPUID level, -1=no CPUID: */ 101 int cpuid_level; 102 /* 103 * Align to size of unsigned long because the x86_capability array 104 * is passed to bitops which require the alignment. Use unnamed 105 * union to enforce the array is aligned to size of unsigned long. 106 */ 107 union { 108 __u32 x86_capability[NCAPINTS + NBUGINTS]; 109 unsigned long x86_capability_alignment; 110 }; 111 char x86_vendor_id[16]; 112 char x86_model_id[64]; 113 /* in KB - valid for CPUS which support this call: */ 114 unsigned int x86_cache_size; 115 int x86_cache_alignment; /* In bytes */ 116 /* Cache QoS architectural values, valid only on the BSP: */ 117 int x86_cache_max_rmid; /* max index */ 118 int x86_cache_occ_scale; /* scale to bytes */ 119 int x86_cache_mbm_width_offset; 120 int x86_power; 121 unsigned long loops_per_jiffy; 122 /* cpuid returned max cores value: */ 123 u16 x86_max_cores; 124 u16 apicid; 125 u16 initial_apicid; 126 u16 x86_clflush_size; 127 /* number of cores as seen by the OS: */ 128 u16 booted_cores; 129 /* Physical processor id: */ 130 u16 phys_proc_id; 131 /* Logical processor id: */ 132 u16 logical_proc_id; 133 /* Core id: */ 134 u16 cpu_core_id; 135 u16 cpu_die_id; 136 u16 logical_die_id; 137 /* Index into per_cpu list: */ 138 u16 cpu_index; 139 /* Is SMT active on this core? */ 140 bool smt_active; 141 u32 microcode; 142 /* Address space bits used by the cache internally */ 143 u8 x86_cache_bits; 144 unsigned initialized : 1; 145 } __randomize_layout; 146 147 struct cpuid_regs { 148 u32 eax, ebx, ecx, edx; 149 }; 150 151 enum cpuid_regs_idx { 152 CPUID_EAX = 0, 153 CPUID_EBX, 154 CPUID_ECX, 155 CPUID_EDX, 156 }; 157 158 #define X86_VENDOR_INTEL 0 159 #define X86_VENDOR_CYRIX 1 160 #define X86_VENDOR_AMD 2 161 #define X86_VENDOR_UMC 3 162 #define X86_VENDOR_CENTAUR 5 163 #define X86_VENDOR_TRANSMETA 7 164 #define X86_VENDOR_NSC 8 165 #define X86_VENDOR_HYGON 9 166 #define X86_VENDOR_ZHAOXIN 10 167 #define X86_VENDOR_NUM 11 168 169 #define X86_VENDOR_UNKNOWN 0xff 170 171 /* 172 * capabilities of CPUs 173 */ 174 extern struct cpuinfo_x86 boot_cpu_data; 175 extern struct cpuinfo_x86 new_cpu_data; 176 177 extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; 178 extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; 179 180 #ifdef CONFIG_SMP 181 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 182 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 183 #else 184 #define cpu_info boot_cpu_data 185 #define cpu_data(cpu) boot_cpu_data 186 #endif 187 188 extern const struct seq_operations cpuinfo_op; 189 190 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 191 192 extern void cpu_detect(struct cpuinfo_x86 *c); 193 194 static inline unsigned long long l1tf_pfn_limit(void) 195 { 196 return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT); 197 } 198 199 extern void early_cpu_init(void); 200 extern void identify_boot_cpu(void); 201 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 202 extern void print_cpu_info(struct cpuinfo_x86 *); 203 void print_cpu_msr(struct cpuinfo_x86 *); 204 205 #ifdef CONFIG_X86_32 206 extern int have_cpuid_p(void); 207 #else 208 static inline int have_cpuid_p(void) 209 { 210 return 1; 211 } 212 #endif 213 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 214 unsigned int *ecx, unsigned int *edx) 215 { 216 /* ecx is often an input as well as an output. */ 217 asm volatile("cpuid" 218 : "=a" (*eax), 219 "=b" (*ebx), 220 "=c" (*ecx), 221 "=d" (*edx) 222 : "0" (*eax), "2" (*ecx) 223 : "memory"); 224 } 225 226 #define native_cpuid_reg(reg) \ 227 static inline unsigned int native_cpuid_##reg(unsigned int op) \ 228 { \ 229 unsigned int eax = op, ebx, ecx = 0, edx; \ 230 \ 231 native_cpuid(&eax, &ebx, &ecx, &edx); \ 232 \ 233 return reg; \ 234 } 235 236 /* 237 * Native CPUID functions returning a single datum. 238 */ 239 native_cpuid_reg(eax) 240 native_cpuid_reg(ebx) 241 native_cpuid_reg(ecx) 242 native_cpuid_reg(edx) 243 244 /* 245 * Friendlier CR3 helpers. 246 */ 247 static inline unsigned long read_cr3_pa(void) 248 { 249 return __read_cr3() & CR3_ADDR_MASK; 250 } 251 252 static inline unsigned long native_read_cr3_pa(void) 253 { 254 return __native_read_cr3() & CR3_ADDR_MASK; 255 } 256 257 static inline void load_cr3(pgd_t *pgdir) 258 { 259 write_cr3(__sme_pa(pgdir)); 260 } 261 262 /* 263 * Note that while the legacy 'TSS' name comes from 'Task State Segment', 264 * on modern x86 CPUs the TSS also holds information important to 64-bit mode, 265 * unrelated to the task-switch mechanism: 266 */ 267 #ifdef CONFIG_X86_32 268 /* This is the TSS defined by the hardware. */ 269 struct x86_hw_tss { 270 unsigned short back_link, __blh; 271 unsigned long sp0; 272 unsigned short ss0, __ss0h; 273 unsigned long sp1; 274 275 /* 276 * We don't use ring 1, so ss1 is a convenient scratch space in 277 * the same cacheline as sp0. We use ss1 to cache the value in 278 * MSR_IA32_SYSENTER_CS. When we context switch 279 * MSR_IA32_SYSENTER_CS, we first check if the new value being 280 * written matches ss1, and, if it's not, then we wrmsr the new 281 * value and update ss1. 282 * 283 * The only reason we context switch MSR_IA32_SYSENTER_CS is 284 * that we set it to zero in vm86 tasks to avoid corrupting the 285 * stack if we were to go through the sysenter path from vm86 286 * mode. 287 */ 288 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ 289 290 unsigned short __ss1h; 291 unsigned long sp2; 292 unsigned short ss2, __ss2h; 293 unsigned long __cr3; 294 unsigned long ip; 295 unsigned long flags; 296 unsigned long ax; 297 unsigned long cx; 298 unsigned long dx; 299 unsigned long bx; 300 unsigned long sp; 301 unsigned long bp; 302 unsigned long si; 303 unsigned long di; 304 unsigned short es, __esh; 305 unsigned short cs, __csh; 306 unsigned short ss, __ssh; 307 unsigned short ds, __dsh; 308 unsigned short fs, __fsh; 309 unsigned short gs, __gsh; 310 unsigned short ldt, __ldth; 311 unsigned short trace; 312 unsigned short io_bitmap_base; 313 314 } __attribute__((packed)); 315 #else 316 struct x86_hw_tss { 317 u32 reserved1; 318 u64 sp0; 319 u64 sp1; 320 321 /* 322 * Since Linux does not use ring 2, the 'sp2' slot is unused by 323 * hardware. entry_SYSCALL_64 uses it as scratch space to stash 324 * the user RSP value. 325 */ 326 u64 sp2; 327 328 u64 reserved2; 329 u64 ist[7]; 330 u32 reserved3; 331 u32 reserved4; 332 u16 reserved5; 333 u16 io_bitmap_base; 334 335 } __attribute__((packed)); 336 #endif 337 338 /* 339 * IO-bitmap sizes: 340 */ 341 #define IO_BITMAP_BITS 65536 342 #define IO_BITMAP_BYTES (IO_BITMAP_BITS / BITS_PER_BYTE) 343 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES / sizeof(long)) 344 345 #define IO_BITMAP_OFFSET_VALID_MAP \ 346 (offsetof(struct tss_struct, io_bitmap.bitmap) - \ 347 offsetof(struct tss_struct, x86_tss)) 348 349 #define IO_BITMAP_OFFSET_VALID_ALL \ 350 (offsetof(struct tss_struct, io_bitmap.mapall) - \ 351 offsetof(struct tss_struct, x86_tss)) 352 353 #ifdef CONFIG_X86_IOPL_IOPERM 354 /* 355 * sizeof(unsigned long) coming from an extra "long" at the end of the 356 * iobitmap. The limit is inclusive, i.e. the last valid byte. 357 */ 358 # define __KERNEL_TSS_LIMIT \ 359 (IO_BITMAP_OFFSET_VALID_ALL + IO_BITMAP_BYTES + \ 360 sizeof(unsigned long) - 1) 361 #else 362 # define __KERNEL_TSS_LIMIT \ 363 (offsetof(struct tss_struct, x86_tss) + sizeof(struct x86_hw_tss) - 1) 364 #endif 365 366 /* Base offset outside of TSS_LIMIT so unpriviledged IO causes #GP */ 367 #define IO_BITMAP_OFFSET_INVALID (__KERNEL_TSS_LIMIT + 1) 368 369 struct entry_stack { 370 char stack[PAGE_SIZE]; 371 }; 372 373 struct entry_stack_page { 374 struct entry_stack stack; 375 } __aligned(PAGE_SIZE); 376 377 /* 378 * All IO bitmap related data stored in the TSS: 379 */ 380 struct x86_io_bitmap { 381 /* The sequence number of the last active bitmap. */ 382 u64 prev_sequence; 383 384 /* 385 * Store the dirty size of the last io bitmap offender. The next 386 * one will have to do the cleanup as the switch out to a non io 387 * bitmap user will just set x86_tss.io_bitmap_base to a value 388 * outside of the TSS limit. So for sane tasks there is no need to 389 * actually touch the io_bitmap at all. 390 */ 391 unsigned int prev_max; 392 393 /* 394 * The extra 1 is there because the CPU will access an 395 * additional byte beyond the end of the IO permission 396 * bitmap. The extra byte must be all 1 bits, and must 397 * be within the limit. 398 */ 399 unsigned long bitmap[IO_BITMAP_LONGS + 1]; 400 401 /* 402 * Special I/O bitmap to emulate IOPL(3). All bytes zero, 403 * except the additional byte at the end. 404 */ 405 unsigned long mapall[IO_BITMAP_LONGS + 1]; 406 }; 407 408 struct tss_struct { 409 /* 410 * The fixed hardware portion. This must not cross a page boundary 411 * at risk of violating the SDM's advice and potentially triggering 412 * errata. 413 */ 414 struct x86_hw_tss x86_tss; 415 416 struct x86_io_bitmap io_bitmap; 417 } __aligned(PAGE_SIZE); 418 419 DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw); 420 421 /* Per CPU interrupt stacks */ 422 struct irq_stack { 423 char stack[IRQ_STACK_SIZE]; 424 } __aligned(IRQ_STACK_SIZE); 425 426 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack); 427 428 #ifdef CONFIG_X86_64 429 struct fixed_percpu_data { 430 /* 431 * GCC hardcodes the stack canary as %gs:40. Since the 432 * irq_stack is the object at %gs:0, we reserve the bottom 433 * 48 bytes of the irq stack for the canary. 434 * 435 * Once we are willing to require -mstack-protector-guard-symbol= 436 * support for x86_64 stackprotector, we can get rid of this. 437 */ 438 char gs_base[40]; 439 unsigned long stack_canary; 440 }; 441 442 DECLARE_PER_CPU_FIRST(struct fixed_percpu_data, fixed_percpu_data) __visible; 443 DECLARE_INIT_PER_CPU(fixed_percpu_data); 444 445 static inline unsigned long cpu_kernelmode_gs_base(int cpu) 446 { 447 return (unsigned long)per_cpu(fixed_percpu_data.gs_base, cpu); 448 } 449 450 DECLARE_PER_CPU(void *, hardirq_stack_ptr); 451 DECLARE_PER_CPU(bool, hardirq_stack_inuse); 452 extern asmlinkage void ignore_sysret(void); 453 454 /* Save actual FS/GS selectors and bases to current->thread */ 455 void current_save_fsgs(void); 456 #else /* X86_64 */ 457 #ifdef CONFIG_STACKPROTECTOR 458 DECLARE_PER_CPU(unsigned long, __stack_chk_guard); 459 #endif 460 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack_ptr); 461 DECLARE_PER_CPU(struct irq_stack *, softirq_stack_ptr); 462 #endif /* !X86_64 */ 463 464 extern unsigned int fpu_kernel_xstate_size; 465 extern unsigned int fpu_user_xstate_size; 466 467 struct perf_event; 468 469 struct thread_struct { 470 /* Cached TLS descriptors: */ 471 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 472 #ifdef CONFIG_X86_32 473 unsigned long sp0; 474 #endif 475 unsigned long sp; 476 #ifdef CONFIG_X86_32 477 unsigned long sysenter_cs; 478 #else 479 unsigned short es; 480 unsigned short ds; 481 unsigned short fsindex; 482 unsigned short gsindex; 483 #endif 484 485 #ifdef CONFIG_X86_64 486 unsigned long fsbase; 487 unsigned long gsbase; 488 #else 489 /* 490 * XXX: this could presumably be unsigned short. Alternatively, 491 * 32-bit kernels could be taught to use fsindex instead. 492 */ 493 unsigned long fs; 494 unsigned long gs; 495 #endif 496 497 /* Save middle states of ptrace breakpoints */ 498 struct perf_event *ptrace_bps[HBP_NUM]; 499 /* Debug status used for traps, single steps, etc... */ 500 unsigned long virtual_dr6; 501 /* Keep track of the exact dr7 value set by the user */ 502 unsigned long ptrace_dr7; 503 /* Fault info: */ 504 unsigned long cr2; 505 unsigned long trap_nr; 506 unsigned long error_code; 507 #ifdef CONFIG_VM86 508 /* Virtual 86 mode info */ 509 struct vm86 *vm86; 510 #endif 511 /* IO permissions: */ 512 struct io_bitmap *io_bitmap; 513 514 /* 515 * IOPL. Privilege level dependent I/O permission which is 516 * emulated via the I/O bitmap to prevent user space from disabling 517 * interrupts. 518 */ 519 unsigned long iopl_emul; 520 521 unsigned int sig_on_uaccess_err:1; 522 523 /* 524 * Protection Keys Register for Userspace. Loaded immediately on 525 * context switch. Store it in thread_struct to avoid a lookup in 526 * the tasks's FPU xstate buffer. This value is only valid when a 527 * task is scheduled out. For 'current' the authoritative source of 528 * PKRU is the hardware itself. 529 */ 530 u32 pkru; 531 532 /* Floating point and extended processor state */ 533 struct fpu fpu; 534 /* 535 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at 536 * the end. 537 */ 538 }; 539 540 /* Whitelist the FPU state from the task_struct for hardened usercopy. */ 541 static inline void arch_thread_struct_whitelist(unsigned long *offset, 542 unsigned long *size) 543 { 544 *offset = offsetof(struct thread_struct, fpu.state); 545 *size = fpu_kernel_xstate_size; 546 } 547 548 static inline void 549 native_load_sp0(unsigned long sp0) 550 { 551 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0); 552 } 553 554 static __always_inline void native_swapgs(void) 555 { 556 #ifdef CONFIG_X86_64 557 asm volatile("swapgs" ::: "memory"); 558 #endif 559 } 560 561 static inline unsigned long current_top_of_stack(void) 562 { 563 /* 564 * We can't read directly from tss.sp0: sp0 on x86_32 is special in 565 * and around vm86 mode and sp0 on x86_64 is special because of the 566 * entry trampoline. 567 */ 568 return this_cpu_read_stable(cpu_current_top_of_stack); 569 } 570 571 static inline bool on_thread_stack(void) 572 { 573 return (unsigned long)(current_top_of_stack() - 574 current_stack_pointer) < THREAD_SIZE; 575 } 576 577 #ifdef CONFIG_PARAVIRT_XXL 578 #include <asm/paravirt.h> 579 #else 580 #define __cpuid native_cpuid 581 582 static inline void load_sp0(unsigned long sp0) 583 { 584 native_load_sp0(sp0); 585 } 586 587 #endif /* CONFIG_PARAVIRT_XXL */ 588 589 /* Free all resources held by a thread. */ 590 extern void release_thread(struct task_struct *); 591 592 unsigned long get_wchan(struct task_struct *p); 593 594 /* 595 * Generic CPUID function 596 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 597 * resulting in stale register contents being returned. 598 */ 599 static inline void cpuid(unsigned int op, 600 unsigned int *eax, unsigned int *ebx, 601 unsigned int *ecx, unsigned int *edx) 602 { 603 *eax = op; 604 *ecx = 0; 605 __cpuid(eax, ebx, ecx, edx); 606 } 607 608 /* Some CPUID calls want 'count' to be placed in ecx */ 609 static inline void cpuid_count(unsigned int op, int count, 610 unsigned int *eax, unsigned int *ebx, 611 unsigned int *ecx, unsigned int *edx) 612 { 613 *eax = op; 614 *ecx = count; 615 __cpuid(eax, ebx, ecx, edx); 616 } 617 618 /* 619 * CPUID functions returning a single datum 620 */ 621 static inline unsigned int cpuid_eax(unsigned int op) 622 { 623 unsigned int eax, ebx, ecx, edx; 624 625 cpuid(op, &eax, &ebx, &ecx, &edx); 626 627 return eax; 628 } 629 630 static inline unsigned int cpuid_ebx(unsigned int op) 631 { 632 unsigned int eax, ebx, ecx, edx; 633 634 cpuid(op, &eax, &ebx, &ecx, &edx); 635 636 return ebx; 637 } 638 639 static inline unsigned int cpuid_ecx(unsigned int op) 640 { 641 unsigned int eax, ebx, ecx, edx; 642 643 cpuid(op, &eax, &ebx, &ecx, &edx); 644 645 return ecx; 646 } 647 648 static inline unsigned int cpuid_edx(unsigned int op) 649 { 650 unsigned int eax, ebx, ecx, edx; 651 652 cpuid(op, &eax, &ebx, &ecx, &edx); 653 654 return edx; 655 } 656 657 extern void select_idle_routine(const struct cpuinfo_x86 *c); 658 extern void amd_e400_c1e_apic_setup(void); 659 660 extern unsigned long boot_option_idle_override; 661 662 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 663 IDLE_POLL}; 664 665 extern void enable_sep_cpu(void); 666 extern int sysenter_setup(void); 667 668 669 /* Defined in head.S */ 670 extern struct desc_ptr early_gdt_descr; 671 672 extern void switch_to_new_gdt(int); 673 extern void load_direct_gdt(int); 674 extern void load_fixmap_gdt(int); 675 extern void load_percpu_segment(int); 676 extern void cpu_init(void); 677 extern void cpu_init_secondary(void); 678 extern void cpu_init_exception_handling(void); 679 extern void cr4_init(void); 680 681 static inline unsigned long get_debugctlmsr(void) 682 { 683 unsigned long debugctlmsr = 0; 684 685 #ifndef CONFIG_X86_DEBUGCTLMSR 686 if (boot_cpu_data.x86 < 6) 687 return 0; 688 #endif 689 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 690 691 return debugctlmsr; 692 } 693 694 static inline void update_debugctlmsr(unsigned long debugctlmsr) 695 { 696 #ifndef CONFIG_X86_DEBUGCTLMSR 697 if (boot_cpu_data.x86 < 6) 698 return; 699 #endif 700 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 701 } 702 703 extern void set_task_blockstep(struct task_struct *task, bool on); 704 705 /* Boot loader type from the setup header: */ 706 extern int bootloader_type; 707 extern int bootloader_version; 708 709 extern char ignore_fpu_irq; 710 711 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 712 #define ARCH_HAS_PREFETCHW 713 #define ARCH_HAS_SPINLOCK_PREFETCH 714 715 #ifdef CONFIG_X86_32 716 # define BASE_PREFETCH "" 717 # define ARCH_HAS_PREFETCH 718 #else 719 # define BASE_PREFETCH "prefetcht0 %P1" 720 #endif 721 722 /* 723 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 724 * 725 * It's not worth to care about 3dnow prefetches for the K6 726 * because they are microcoded there and very slow. 727 */ 728 static inline void prefetch(const void *x) 729 { 730 alternative_input(BASE_PREFETCH, "prefetchnta %P1", 731 X86_FEATURE_XMM, 732 "m" (*(const char *)x)); 733 } 734 735 /* 736 * 3dnow prefetch to get an exclusive cache line. 737 * Useful for spinlocks to avoid one state transition in the 738 * cache coherency protocol: 739 */ 740 static __always_inline void prefetchw(const void *x) 741 { 742 alternative_input(BASE_PREFETCH, "prefetchw %P1", 743 X86_FEATURE_3DNOWPREFETCH, 744 "m" (*(const char *)x)); 745 } 746 747 static inline void spin_lock_prefetch(const void *x) 748 { 749 prefetchw(x); 750 } 751 752 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ 753 TOP_OF_KERNEL_STACK_PADDING) 754 755 #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1)) 756 757 #define task_pt_regs(task) \ 758 ({ \ 759 unsigned long __ptr = (unsigned long)task_stack_page(task); \ 760 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ 761 ((struct pt_regs *)__ptr) - 1; \ 762 }) 763 764 #ifdef CONFIG_X86_32 765 #define INIT_THREAD { \ 766 .sp0 = TOP_OF_INIT_STACK, \ 767 .sysenter_cs = __KERNEL_CS, \ 768 } 769 770 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 771 772 #else 773 #define INIT_THREAD { } 774 775 extern unsigned long KSTK_ESP(struct task_struct *task); 776 777 #endif /* CONFIG_X86_64 */ 778 779 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 780 unsigned long new_sp); 781 782 /* 783 * This decides where the kernel will search for a free chunk of vm 784 * space during mmap's. 785 */ 786 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3)) 787 #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW) 788 789 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 790 791 /* Get/set a process' ability to use the timestamp counter instruction */ 792 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 793 #define SET_TSC_CTL(val) set_tsc_mode((val)) 794 795 extern int get_tsc_mode(unsigned long adr); 796 extern int set_tsc_mode(unsigned int val); 797 798 DECLARE_PER_CPU(u64, msr_misc_features_shadow); 799 800 extern u16 get_llc_id(unsigned int cpu); 801 802 #ifdef CONFIG_CPU_SUP_AMD 803 extern u32 amd_get_nodes_per_socket(void); 804 extern u32 amd_get_highest_perf(void); 805 #else 806 static inline u32 amd_get_nodes_per_socket(void) { return 0; } 807 static inline u32 amd_get_highest_perf(void) { return 0; } 808 #endif 809 810 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves) 811 { 812 uint32_t base, eax, signature[3]; 813 814 for (base = 0x40000000; base < 0x40010000; base += 0x100) { 815 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); 816 817 if (!memcmp(sig, signature, 12) && 818 (leaves == 0 || ((eax - base) >= leaves))) 819 return base; 820 } 821 822 return 0; 823 } 824 825 extern unsigned long arch_align_stack(unsigned long sp); 826 void free_init_pages(const char *what, unsigned long begin, unsigned long end); 827 extern void free_kernel_image_pages(const char *what, void *begin, void *end); 828 829 void default_idle(void); 830 #ifdef CONFIG_XEN 831 bool xen_set_default_idle(void); 832 #else 833 #define xen_set_default_idle 0 834 #endif 835 836 void stop_this_cpu(void *dummy); 837 void microcode_check(void); 838 839 enum l1tf_mitigations { 840 L1TF_MITIGATION_OFF, 841 L1TF_MITIGATION_FLUSH_NOWARN, 842 L1TF_MITIGATION_FLUSH, 843 L1TF_MITIGATION_FLUSH_NOSMT, 844 L1TF_MITIGATION_FULL, 845 L1TF_MITIGATION_FULL_FORCE 846 }; 847 848 extern enum l1tf_mitigations l1tf_mitigation; 849 850 enum mds_mitigations { 851 MDS_MITIGATION_OFF, 852 MDS_MITIGATION_FULL, 853 MDS_MITIGATION_VMWERV, 854 }; 855 856 #endif /* _ASM_X86_PROCESSOR_H */ 857