1 #ifndef _ASM_X86_PROCESSOR_H 2 #define _ASM_X86_PROCESSOR_H 3 4 #include <asm/processor-flags.h> 5 6 /* Forward declaration, a strange C thing */ 7 struct task_struct; 8 struct mm_struct; 9 struct vm86; 10 11 #include <asm/math_emu.h> 12 #include <asm/segment.h> 13 #include <asm/types.h> 14 #include <uapi/asm/sigcontext.h> 15 #include <asm/current.h> 16 #include <asm/cpufeatures.h> 17 #include <asm/page.h> 18 #include <asm/pgtable_types.h> 19 #include <asm/percpu.h> 20 #include <asm/msr.h> 21 #include <asm/desc_defs.h> 22 #include <asm/nops.h> 23 #include <asm/special_insns.h> 24 #include <asm/fpu/types.h> 25 26 #include <linux/personality.h> 27 #include <linux/cache.h> 28 #include <linux/threads.h> 29 #include <linux/math64.h> 30 #include <linux/err.h> 31 #include <linux/irqflags.h> 32 33 /* 34 * We handle most unaligned accesses in hardware. On the other hand 35 * unaligned DMA can be quite expensive on some Nehalem processors. 36 * 37 * Based on this we disable the IP header alignment in network drivers. 38 */ 39 #define NET_IP_ALIGN 0 40 41 #define HBP_NUM 4 42 /* 43 * Default implementation of macro that returns current 44 * instruction pointer ("program counter"). 45 */ 46 static inline void *current_text_addr(void) 47 { 48 void *pc; 49 50 asm volatile("mov $1f, %0; 1:":"=r" (pc)); 51 52 return pc; 53 } 54 55 /* 56 * These alignment constraints are for performance in the vSMP case, 57 * but in the task_struct case we must also meet hardware imposed 58 * alignment requirements of the FPU state: 59 */ 60 #ifdef CONFIG_X86_VSMP 61 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 62 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 63 #else 64 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state) 65 # define ARCH_MIN_MMSTRUCT_ALIGN 0 66 #endif 67 68 enum tlb_infos { 69 ENTRIES, 70 NR_INFO 71 }; 72 73 extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 74 extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 75 extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 76 extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 77 extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 78 extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 79 extern u16 __read_mostly tlb_lld_1g[NR_INFO]; 80 81 /* 82 * CPU type and hardware bug flags. Kept separately for each CPU. 83 * Members of this structure are referenced in head_32.S, so think twice 84 * before touching them. [mj] 85 */ 86 87 struct cpuinfo_x86 { 88 __u8 x86; /* CPU family */ 89 __u8 x86_vendor; /* CPU vendor */ 90 __u8 x86_model; 91 __u8 x86_mask; 92 #ifdef CONFIG_X86_64 93 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 94 int x86_tlbsize; 95 #endif 96 __u8 x86_virt_bits; 97 __u8 x86_phys_bits; 98 /* CPUID returned core id bits: */ 99 __u8 x86_coreid_bits; 100 __u8 cu_id; 101 /* Max extended CPUID function supported: */ 102 __u32 extended_cpuid_level; 103 /* Maximum supported CPUID level, -1=no CPUID: */ 104 int cpuid_level; 105 __u32 x86_capability[NCAPINTS + NBUGINTS]; 106 char x86_vendor_id[16]; 107 char x86_model_id[64]; 108 /* in KB - valid for CPUS which support this call: */ 109 int x86_cache_size; 110 int x86_cache_alignment; /* In bytes */ 111 /* Cache QoS architectural values: */ 112 int x86_cache_max_rmid; /* max index */ 113 int x86_cache_occ_scale; /* scale to bytes */ 114 int x86_power; 115 unsigned long loops_per_jiffy; 116 /* cpuid returned max cores value: */ 117 u16 x86_max_cores; 118 u16 apicid; 119 u16 initial_apicid; 120 u16 x86_clflush_size; 121 /* number of cores as seen by the OS: */ 122 u16 booted_cores; 123 /* Physical processor id: */ 124 u16 phys_proc_id; 125 /* Logical processor id: */ 126 u16 logical_proc_id; 127 /* Core id: */ 128 u16 cpu_core_id; 129 /* Index into per_cpu list: */ 130 u16 cpu_index; 131 u32 microcode; 132 }; 133 134 struct cpuid_regs { 135 u32 eax, ebx, ecx, edx; 136 }; 137 138 enum cpuid_regs_idx { 139 CPUID_EAX = 0, 140 CPUID_EBX, 141 CPUID_ECX, 142 CPUID_EDX, 143 }; 144 145 #define X86_VENDOR_INTEL 0 146 #define X86_VENDOR_CYRIX 1 147 #define X86_VENDOR_AMD 2 148 #define X86_VENDOR_UMC 3 149 #define X86_VENDOR_CENTAUR 5 150 #define X86_VENDOR_TRANSMETA 7 151 #define X86_VENDOR_NSC 8 152 #define X86_VENDOR_NUM 9 153 154 #define X86_VENDOR_UNKNOWN 0xff 155 156 /* 157 * capabilities of CPUs 158 */ 159 extern struct cpuinfo_x86 boot_cpu_data; 160 extern struct cpuinfo_x86 new_cpu_data; 161 162 extern struct tss_struct doublefault_tss; 163 extern __u32 cpu_caps_cleared[NCAPINTS]; 164 extern __u32 cpu_caps_set[NCAPINTS]; 165 166 #ifdef CONFIG_SMP 167 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 168 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 169 #else 170 #define cpu_info boot_cpu_data 171 #define cpu_data(cpu) boot_cpu_data 172 #endif 173 174 extern const struct seq_operations cpuinfo_op; 175 176 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 177 178 extern void cpu_detect(struct cpuinfo_x86 *c); 179 180 extern void early_cpu_init(void); 181 extern void identify_boot_cpu(void); 182 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 183 extern void print_cpu_info(struct cpuinfo_x86 *); 184 void print_cpu_msr(struct cpuinfo_x86 *); 185 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); 186 extern u32 get_scattered_cpuid_leaf(unsigned int level, 187 unsigned int sub_leaf, 188 enum cpuid_regs_idx reg); 189 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); 190 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); 191 192 extern void detect_extended_topology(struct cpuinfo_x86 *c); 193 extern void detect_ht(struct cpuinfo_x86 *c); 194 195 #ifdef CONFIG_X86_32 196 extern int have_cpuid_p(void); 197 #else 198 static inline int have_cpuid_p(void) 199 { 200 return 1; 201 } 202 #endif 203 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 204 unsigned int *ecx, unsigned int *edx) 205 { 206 /* ecx is often an input as well as an output. */ 207 asm volatile("cpuid" 208 : "=a" (*eax), 209 "=b" (*ebx), 210 "=c" (*ecx), 211 "=d" (*edx) 212 : "0" (*eax), "2" (*ecx) 213 : "memory"); 214 } 215 216 #define native_cpuid_reg(reg) \ 217 static inline unsigned int native_cpuid_##reg(unsigned int op) \ 218 { \ 219 unsigned int eax = op, ebx, ecx = 0, edx; \ 220 \ 221 native_cpuid(&eax, &ebx, &ecx, &edx); \ 222 \ 223 return reg; \ 224 } 225 226 /* 227 * Native CPUID functions returning a single datum. 228 */ 229 native_cpuid_reg(eax) 230 native_cpuid_reg(ebx) 231 native_cpuid_reg(ecx) 232 native_cpuid_reg(edx) 233 234 static inline void load_cr3(pgd_t *pgdir) 235 { 236 write_cr3(__pa(pgdir)); 237 } 238 239 #ifdef CONFIG_X86_32 240 /* This is the TSS defined by the hardware. */ 241 struct x86_hw_tss { 242 unsigned short back_link, __blh; 243 unsigned long sp0; 244 unsigned short ss0, __ss0h; 245 unsigned long sp1; 246 247 /* 248 * We don't use ring 1, so ss1 is a convenient scratch space in 249 * the same cacheline as sp0. We use ss1 to cache the value in 250 * MSR_IA32_SYSENTER_CS. When we context switch 251 * MSR_IA32_SYSENTER_CS, we first check if the new value being 252 * written matches ss1, and, if it's not, then we wrmsr the new 253 * value and update ss1. 254 * 255 * The only reason we context switch MSR_IA32_SYSENTER_CS is 256 * that we set it to zero in vm86 tasks to avoid corrupting the 257 * stack if we were to go through the sysenter path from vm86 258 * mode. 259 */ 260 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ 261 262 unsigned short __ss1h; 263 unsigned long sp2; 264 unsigned short ss2, __ss2h; 265 unsigned long __cr3; 266 unsigned long ip; 267 unsigned long flags; 268 unsigned long ax; 269 unsigned long cx; 270 unsigned long dx; 271 unsigned long bx; 272 unsigned long sp; 273 unsigned long bp; 274 unsigned long si; 275 unsigned long di; 276 unsigned short es, __esh; 277 unsigned short cs, __csh; 278 unsigned short ss, __ssh; 279 unsigned short ds, __dsh; 280 unsigned short fs, __fsh; 281 unsigned short gs, __gsh; 282 unsigned short ldt, __ldth; 283 unsigned short trace; 284 unsigned short io_bitmap_base; 285 286 } __attribute__((packed)); 287 #else 288 struct x86_hw_tss { 289 u32 reserved1; 290 u64 sp0; 291 u64 sp1; 292 u64 sp2; 293 u64 reserved2; 294 u64 ist[7]; 295 u32 reserved3; 296 u32 reserved4; 297 u16 reserved5; 298 u16 io_bitmap_base; 299 300 } __attribute__((packed)); 301 #endif 302 303 /* 304 * IO-bitmap sizes: 305 */ 306 #define IO_BITMAP_BITS 65536 307 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) 308 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) 309 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) 310 #define INVALID_IO_BITMAP_OFFSET 0x8000 311 312 struct tss_struct { 313 /* 314 * The hardware state: 315 */ 316 struct x86_hw_tss x86_tss; 317 318 /* 319 * The extra 1 is there because the CPU will access an 320 * additional byte beyond the end of the IO permission 321 * bitmap. The extra byte must be all 1 bits, and must 322 * be within the limit. 323 */ 324 unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; 325 326 #ifdef CONFIG_X86_32 327 /* 328 * Space for the temporary SYSENTER stack. 329 */ 330 unsigned long SYSENTER_stack_canary; 331 unsigned long SYSENTER_stack[64]; 332 #endif 333 334 } ____cacheline_aligned; 335 336 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss); 337 338 /* 339 * sizeof(unsigned long) coming from an extra "long" at the end 340 * of the iobitmap. 341 * 342 * -1? seg base+limit should be pointing to the address of the 343 * last valid byte 344 */ 345 #define __KERNEL_TSS_LIMIT \ 346 (IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1) 347 348 #ifdef CONFIG_X86_32 349 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack); 350 #endif 351 352 /* 353 * Save the original ist values for checking stack pointers during debugging 354 */ 355 struct orig_ist { 356 unsigned long ist[7]; 357 }; 358 359 #ifdef CONFIG_X86_64 360 DECLARE_PER_CPU(struct orig_ist, orig_ist); 361 362 union irq_stack_union { 363 char irq_stack[IRQ_STACK_SIZE]; 364 /* 365 * GCC hardcodes the stack canary as %gs:40. Since the 366 * irq_stack is the object at %gs:0, we reserve the bottom 367 * 48 bytes of the irq stack for the canary. 368 */ 369 struct { 370 char gs_base[40]; 371 unsigned long stack_canary; 372 }; 373 }; 374 375 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible; 376 DECLARE_INIT_PER_CPU(irq_stack_union); 377 378 DECLARE_PER_CPU(char *, irq_stack_ptr); 379 DECLARE_PER_CPU(unsigned int, irq_count); 380 extern asmlinkage void ignore_sysret(void); 381 #else /* X86_64 */ 382 #ifdef CONFIG_CC_STACKPROTECTOR 383 /* 384 * Make sure stack canary segment base is cached-aligned: 385 * "For Intel Atom processors, avoid non zero segment base address 386 * that is not aligned to cache line boundary at all cost." 387 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) 388 */ 389 struct stack_canary { 390 char __pad[20]; /* canary at %gs:20 */ 391 unsigned long canary; 392 }; 393 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 394 #endif 395 /* 396 * per-CPU IRQ handling stacks 397 */ 398 struct irq_stack { 399 u32 stack[THREAD_SIZE/sizeof(u32)]; 400 } __aligned(THREAD_SIZE); 401 402 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack); 403 DECLARE_PER_CPU(struct irq_stack *, softirq_stack); 404 #endif /* X86_64 */ 405 406 extern unsigned int fpu_kernel_xstate_size; 407 extern unsigned int fpu_user_xstate_size; 408 409 struct perf_event; 410 411 typedef struct { 412 unsigned long seg; 413 } mm_segment_t; 414 415 struct thread_struct { 416 /* Cached TLS descriptors: */ 417 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 418 unsigned long sp0; 419 unsigned long sp; 420 #ifdef CONFIG_X86_32 421 unsigned long sysenter_cs; 422 #else 423 unsigned short es; 424 unsigned short ds; 425 unsigned short fsindex; 426 unsigned short gsindex; 427 #endif 428 429 u32 status; /* thread synchronous flags */ 430 431 #ifdef CONFIG_X86_64 432 unsigned long fsbase; 433 unsigned long gsbase; 434 #else 435 /* 436 * XXX: this could presumably be unsigned short. Alternatively, 437 * 32-bit kernels could be taught to use fsindex instead. 438 */ 439 unsigned long fs; 440 unsigned long gs; 441 #endif 442 443 /* Save middle states of ptrace breakpoints */ 444 struct perf_event *ptrace_bps[HBP_NUM]; 445 /* Debug status used for traps, single steps, etc... */ 446 unsigned long debugreg6; 447 /* Keep track of the exact dr7 value set by the user */ 448 unsigned long ptrace_dr7; 449 /* Fault info: */ 450 unsigned long cr2; 451 unsigned long trap_nr; 452 unsigned long error_code; 453 #ifdef CONFIG_VM86 454 /* Virtual 86 mode info */ 455 struct vm86 *vm86; 456 #endif 457 /* IO permissions: */ 458 unsigned long *io_bitmap_ptr; 459 unsigned long iopl; 460 /* Max allowed port in the bitmap, in bytes: */ 461 unsigned io_bitmap_max; 462 463 mm_segment_t addr_limit; 464 465 unsigned int sig_on_uaccess_err:1; 466 unsigned int uaccess_err:1; /* uaccess failed */ 467 468 /* Floating point and extended processor state */ 469 struct fpu fpu; 470 /* 471 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at 472 * the end. 473 */ 474 }; 475 476 /* 477 * Thread-synchronous status. 478 * 479 * This is different from the flags in that nobody else 480 * ever touches our thread-synchronous status, so we don't 481 * have to worry about atomic accesses. 482 */ 483 #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/ 484 485 /* 486 * Set IOPL bits in EFLAGS from given mask 487 */ 488 static inline void native_set_iopl_mask(unsigned mask) 489 { 490 #ifdef CONFIG_X86_32 491 unsigned int reg; 492 493 asm volatile ("pushfl;" 494 "popl %0;" 495 "andl %1, %0;" 496 "orl %2, %0;" 497 "pushl %0;" 498 "popfl" 499 : "=&r" (reg) 500 : "i" (~X86_EFLAGS_IOPL), "r" (mask)); 501 #endif 502 } 503 504 static inline void 505 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread) 506 { 507 tss->x86_tss.sp0 = thread->sp0; 508 #ifdef CONFIG_X86_32 509 /* Only happens when SEP is enabled, no need to test "SEP"arately: */ 510 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { 511 tss->x86_tss.ss1 = thread->sysenter_cs; 512 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); 513 } 514 #endif 515 } 516 517 static inline void native_swapgs(void) 518 { 519 #ifdef CONFIG_X86_64 520 asm volatile("swapgs" ::: "memory"); 521 #endif 522 } 523 524 static inline unsigned long current_top_of_stack(void) 525 { 526 #ifdef CONFIG_X86_64 527 return this_cpu_read_stable(cpu_tss.x86_tss.sp0); 528 #else 529 /* sp0 on x86_32 is special in and around vm86 mode. */ 530 return this_cpu_read_stable(cpu_current_top_of_stack); 531 #endif 532 } 533 534 #ifdef CONFIG_PARAVIRT 535 #include <asm/paravirt.h> 536 #else 537 #define __cpuid native_cpuid 538 539 static inline void load_sp0(struct tss_struct *tss, 540 struct thread_struct *thread) 541 { 542 native_load_sp0(tss, thread); 543 } 544 545 #define set_iopl_mask native_set_iopl_mask 546 #endif /* CONFIG_PARAVIRT */ 547 548 /* Free all resources held by a thread. */ 549 extern void release_thread(struct task_struct *); 550 551 unsigned long get_wchan(struct task_struct *p); 552 553 /* 554 * Generic CPUID function 555 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 556 * resulting in stale register contents being returned. 557 */ 558 static inline void cpuid(unsigned int op, 559 unsigned int *eax, unsigned int *ebx, 560 unsigned int *ecx, unsigned int *edx) 561 { 562 *eax = op; 563 *ecx = 0; 564 __cpuid(eax, ebx, ecx, edx); 565 } 566 567 /* Some CPUID calls want 'count' to be placed in ecx */ 568 static inline void cpuid_count(unsigned int op, int count, 569 unsigned int *eax, unsigned int *ebx, 570 unsigned int *ecx, unsigned int *edx) 571 { 572 *eax = op; 573 *ecx = count; 574 __cpuid(eax, ebx, ecx, edx); 575 } 576 577 /* 578 * CPUID functions returning a single datum 579 */ 580 static inline unsigned int cpuid_eax(unsigned int op) 581 { 582 unsigned int eax, ebx, ecx, edx; 583 584 cpuid(op, &eax, &ebx, &ecx, &edx); 585 586 return eax; 587 } 588 589 static inline unsigned int cpuid_ebx(unsigned int op) 590 { 591 unsigned int eax, ebx, ecx, edx; 592 593 cpuid(op, &eax, &ebx, &ecx, &edx); 594 595 return ebx; 596 } 597 598 static inline unsigned int cpuid_ecx(unsigned int op) 599 { 600 unsigned int eax, ebx, ecx, edx; 601 602 cpuid(op, &eax, &ebx, &ecx, &edx); 603 604 return ecx; 605 } 606 607 static inline unsigned int cpuid_edx(unsigned int op) 608 { 609 unsigned int eax, ebx, ecx, edx; 610 611 cpuid(op, &eax, &ebx, &ecx, &edx); 612 613 return edx; 614 } 615 616 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 617 static __always_inline void rep_nop(void) 618 { 619 asm volatile("rep; nop" ::: "memory"); 620 } 621 622 static __always_inline void cpu_relax(void) 623 { 624 rep_nop(); 625 } 626 627 /* 628 * This function forces the icache and prefetched instruction stream to 629 * catch up with reality in two very specific cases: 630 * 631 * a) Text was modified using one virtual address and is about to be executed 632 * from the same physical page at a different virtual address. 633 * 634 * b) Text was modified on a different CPU, may subsequently be 635 * executed on this CPU, and you want to make sure the new version 636 * gets executed. This generally means you're calling this in a IPI. 637 * 638 * If you're calling this for a different reason, you're probably doing 639 * it wrong. 640 */ 641 static inline void sync_core(void) 642 { 643 /* 644 * There are quite a few ways to do this. IRET-to-self is nice 645 * because it works on every CPU, at any CPL (so it's compatible 646 * with paravirtualization), and it never exits to a hypervisor. 647 * The only down sides are that it's a bit slow (it seems to be 648 * a bit more than 2x slower than the fastest options) and that 649 * it unmasks NMIs. The "push %cs" is needed because, in 650 * paravirtual environments, __KERNEL_CS may not be a valid CS 651 * value when we do IRET directly. 652 * 653 * In case NMI unmasking or performance ever becomes a problem, 654 * the next best option appears to be MOV-to-CR2 and an 655 * unconditional jump. That sequence also works on all CPUs, 656 * but it will fault at CPL3 (i.e. Xen PV and lguest). 657 * 658 * CPUID is the conventional way, but it's nasty: it doesn't 659 * exist on some 486-like CPUs, and it usually exits to a 660 * hypervisor. 661 * 662 * Like all of Linux's memory ordering operations, this is a 663 * compiler barrier as well. 664 */ 665 register void *__sp asm(_ASM_SP); 666 667 #ifdef CONFIG_X86_32 668 asm volatile ( 669 "pushfl\n\t" 670 "pushl %%cs\n\t" 671 "pushl $1f\n\t" 672 "iret\n\t" 673 "1:" 674 : "+r" (__sp) : : "memory"); 675 #else 676 unsigned int tmp; 677 678 asm volatile ( 679 "mov %%ss, %0\n\t" 680 "pushq %q0\n\t" 681 "pushq %%rsp\n\t" 682 "addq $8, (%%rsp)\n\t" 683 "pushfq\n\t" 684 "mov %%cs, %0\n\t" 685 "pushq %q0\n\t" 686 "pushq $1f\n\t" 687 "iretq\n\t" 688 "1:" 689 : "=&r" (tmp), "+r" (__sp) : : "cc", "memory"); 690 #endif 691 } 692 693 extern void select_idle_routine(const struct cpuinfo_x86 *c); 694 extern void amd_e400_c1e_apic_setup(void); 695 696 extern unsigned long boot_option_idle_override; 697 698 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 699 IDLE_POLL}; 700 701 extern void enable_sep_cpu(void); 702 extern int sysenter_setup(void); 703 704 extern void early_trap_init(void); 705 void early_trap_pf_init(void); 706 707 /* Defined in head.S */ 708 extern struct desc_ptr early_gdt_descr; 709 710 extern void cpu_set_gdt(int); 711 extern void switch_to_new_gdt(int); 712 extern void load_direct_gdt(int); 713 extern void load_fixmap_gdt(int); 714 extern void load_percpu_segment(int); 715 extern void cpu_init(void); 716 717 static inline unsigned long get_debugctlmsr(void) 718 { 719 unsigned long debugctlmsr = 0; 720 721 #ifndef CONFIG_X86_DEBUGCTLMSR 722 if (boot_cpu_data.x86 < 6) 723 return 0; 724 #endif 725 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 726 727 return debugctlmsr; 728 } 729 730 static inline void update_debugctlmsr(unsigned long debugctlmsr) 731 { 732 #ifndef CONFIG_X86_DEBUGCTLMSR 733 if (boot_cpu_data.x86 < 6) 734 return; 735 #endif 736 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 737 } 738 739 extern void set_task_blockstep(struct task_struct *task, bool on); 740 741 /* Boot loader type from the setup header: */ 742 extern int bootloader_type; 743 extern int bootloader_version; 744 745 extern char ignore_fpu_irq; 746 747 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 748 #define ARCH_HAS_PREFETCHW 749 #define ARCH_HAS_SPINLOCK_PREFETCH 750 751 #ifdef CONFIG_X86_32 752 # define BASE_PREFETCH "" 753 # define ARCH_HAS_PREFETCH 754 #else 755 # define BASE_PREFETCH "prefetcht0 %P1" 756 #endif 757 758 /* 759 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 760 * 761 * It's not worth to care about 3dnow prefetches for the K6 762 * because they are microcoded there and very slow. 763 */ 764 static inline void prefetch(const void *x) 765 { 766 alternative_input(BASE_PREFETCH, "prefetchnta %P1", 767 X86_FEATURE_XMM, 768 "m" (*(const char *)x)); 769 } 770 771 /* 772 * 3dnow prefetch to get an exclusive cache line. 773 * Useful for spinlocks to avoid one state transition in the 774 * cache coherency protocol: 775 */ 776 static inline void prefetchw(const void *x) 777 { 778 alternative_input(BASE_PREFETCH, "prefetchw %P1", 779 X86_FEATURE_3DNOWPREFETCH, 780 "m" (*(const char *)x)); 781 } 782 783 static inline void spin_lock_prefetch(const void *x) 784 { 785 prefetchw(x); 786 } 787 788 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ 789 TOP_OF_KERNEL_STACK_PADDING) 790 791 #ifdef CONFIG_X86_32 792 /* 793 * User space process size: 3GB (default). 794 */ 795 #define IA32_PAGE_OFFSET PAGE_OFFSET 796 #define TASK_SIZE PAGE_OFFSET 797 #define TASK_SIZE_MAX TASK_SIZE 798 #define STACK_TOP TASK_SIZE 799 #define STACK_TOP_MAX STACK_TOP 800 801 #define INIT_THREAD { \ 802 .sp0 = TOP_OF_INIT_STACK, \ 803 .sysenter_cs = __KERNEL_CS, \ 804 .io_bitmap_ptr = NULL, \ 805 .addr_limit = KERNEL_DS, \ 806 } 807 808 /* 809 * TOP_OF_KERNEL_STACK_PADDING reserves 8 bytes on top of the ring0 stack. 810 * This is necessary to guarantee that the entire "struct pt_regs" 811 * is accessible even if the CPU haven't stored the SS/ESP registers 812 * on the stack (interrupt gate does not save these registers 813 * when switching to the same priv ring). 814 * Therefore beware: accessing the ss/esp fields of the 815 * "struct pt_regs" is possible, but they may contain the 816 * completely wrong values. 817 */ 818 #define task_pt_regs(task) \ 819 ({ \ 820 unsigned long __ptr = (unsigned long)task_stack_page(task); \ 821 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ 822 ((struct pt_regs *)__ptr) - 1; \ 823 }) 824 825 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 826 827 #else 828 /* 829 * User space process size. 47bits minus one guard page. The guard 830 * page is necessary on Intel CPUs: if a SYSCALL instruction is at 831 * the highest possible canonical userspace address, then that 832 * syscall will enter the kernel with a non-canonical return 833 * address, and SYSRET will explode dangerously. We avoid this 834 * particular problem by preventing anything from being mapped 835 * at the maximum canonical address. 836 */ 837 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE) 838 839 /* This decides where the kernel will search for a free chunk of vm 840 * space during mmap's. 841 */ 842 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ 843 0xc0000000 : 0xFFFFe000) 844 845 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ 846 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 847 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ 848 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 849 850 #define STACK_TOP TASK_SIZE 851 #define STACK_TOP_MAX TASK_SIZE_MAX 852 853 #define INIT_THREAD { \ 854 .sp0 = TOP_OF_INIT_STACK, \ 855 .addr_limit = KERNEL_DS, \ 856 } 857 858 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) 859 extern unsigned long KSTK_ESP(struct task_struct *task); 860 861 #endif /* CONFIG_X86_64 */ 862 863 extern unsigned long thread_saved_pc(struct task_struct *tsk); 864 865 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 866 unsigned long new_sp); 867 868 /* 869 * This decides where the kernel will search for a free chunk of vm 870 * space during mmap's. 871 */ 872 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3)) 873 #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE) 874 875 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 876 877 /* Get/set a process' ability to use the timestamp counter instruction */ 878 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 879 #define SET_TSC_CTL(val) set_tsc_mode((val)) 880 881 extern int get_tsc_mode(unsigned long adr); 882 extern int set_tsc_mode(unsigned int val); 883 884 DECLARE_PER_CPU(u64, msr_misc_features_shadow); 885 886 /* Register/unregister a process' MPX related resource */ 887 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management() 888 #define MPX_DISABLE_MANAGEMENT() mpx_disable_management() 889 890 #ifdef CONFIG_X86_INTEL_MPX 891 extern int mpx_enable_management(void); 892 extern int mpx_disable_management(void); 893 #else 894 static inline int mpx_enable_management(void) 895 { 896 return -EINVAL; 897 } 898 static inline int mpx_disable_management(void) 899 { 900 return -EINVAL; 901 } 902 #endif /* CONFIG_X86_INTEL_MPX */ 903 904 extern u16 amd_get_nb_id(int cpu); 905 extern u32 amd_get_nodes_per_socket(void); 906 907 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves) 908 { 909 uint32_t base, eax, signature[3]; 910 911 for (base = 0x40000000; base < 0x40010000; base += 0x100) { 912 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); 913 914 if (!memcmp(sig, signature, 12) && 915 (leaves == 0 || ((eax - base) >= leaves))) 916 return base; 917 } 918 919 return 0; 920 } 921 922 extern unsigned long arch_align_stack(unsigned long sp); 923 extern void free_init_pages(char *what, unsigned long begin, unsigned long end); 924 925 void default_idle(void); 926 #ifdef CONFIG_XEN 927 bool xen_set_default_idle(void); 928 #else 929 #define xen_set_default_idle 0 930 #endif 931 932 void stop_this_cpu(void *dummy); 933 void df_debug(struct pt_regs *regs, long error_code); 934 #endif /* _ASM_X86_PROCESSOR_H */ 935