1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_PROCESSOR_H 3 #define _ASM_X86_PROCESSOR_H 4 5 #include <asm/processor-flags.h> 6 7 /* Forward declaration, a strange C thing */ 8 struct task_struct; 9 struct mm_struct; 10 struct io_bitmap; 11 struct vm86; 12 13 #include <asm/math_emu.h> 14 #include <asm/segment.h> 15 #include <asm/types.h> 16 #include <uapi/asm/sigcontext.h> 17 #include <asm/current.h> 18 #include <asm/cpufeatures.h> 19 #include <asm/cpuid.h> 20 #include <asm/page.h> 21 #include <asm/pgtable_types.h> 22 #include <asm/percpu.h> 23 #include <asm/msr.h> 24 #include <asm/desc_defs.h> 25 #include <asm/nops.h> 26 #include <asm/special_insns.h> 27 #include <asm/fpu/types.h> 28 #include <asm/unwind_hints.h> 29 #include <asm/vmxfeatures.h> 30 #include <asm/vdso/processor.h> 31 #include <asm/shstk.h> 32 33 #include <linux/personality.h> 34 #include <linux/cache.h> 35 #include <linux/threads.h> 36 #include <linux/math64.h> 37 #include <linux/err.h> 38 #include <linux/irqflags.h> 39 #include <linux/mem_encrypt.h> 40 41 /* 42 * We handle most unaligned accesses in hardware. On the other hand 43 * unaligned DMA can be quite expensive on some Nehalem processors. 44 * 45 * Based on this we disable the IP header alignment in network drivers. 46 */ 47 #define NET_IP_ALIGN 0 48 49 #define HBP_NUM 4 50 51 /* 52 * These alignment constraints are for performance in the vSMP case, 53 * but in the task_struct case we must also meet hardware imposed 54 * alignment requirements of the FPU state: 55 */ 56 #ifdef CONFIG_X86_VSMP 57 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 58 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 59 #else 60 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state) 61 # define ARCH_MIN_MMSTRUCT_ALIGN 0 62 #endif 63 64 enum tlb_infos { 65 ENTRIES, 66 NR_INFO 67 }; 68 69 extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 70 extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 71 extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 72 extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 73 extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 74 extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 75 extern u16 __read_mostly tlb_lld_1g[NR_INFO]; 76 77 /* 78 * CPU type and hardware bug flags. Kept separately for each CPU. 79 * Members of this structure are referenced in head_32.S, so think twice 80 * before touching them. [mj] 81 */ 82 83 struct cpuinfo_x86 { 84 __u8 x86; /* CPU family */ 85 __u8 x86_vendor; /* CPU vendor */ 86 __u8 x86_model; 87 __u8 x86_stepping; 88 #ifdef CONFIG_X86_64 89 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 90 int x86_tlbsize; 91 #endif 92 #ifdef CONFIG_X86_VMX_FEATURE_NAMES 93 __u32 vmx_capability[NVMXINTS]; 94 #endif 95 __u8 x86_virt_bits; 96 __u8 x86_phys_bits; 97 /* CPUID returned core id bits: */ 98 __u8 x86_coreid_bits; 99 __u8 cu_id; 100 /* Max extended CPUID function supported: */ 101 __u32 extended_cpuid_level; 102 /* Maximum supported CPUID level, -1=no CPUID: */ 103 int cpuid_level; 104 /* 105 * Align to size of unsigned long because the x86_capability array 106 * is passed to bitops which require the alignment. Use unnamed 107 * union to enforce the array is aligned to size of unsigned long. 108 */ 109 union { 110 __u32 x86_capability[NCAPINTS + NBUGINTS]; 111 unsigned long x86_capability_alignment; 112 }; 113 char x86_vendor_id[16]; 114 char x86_model_id[64]; 115 /* in KB - valid for CPUS which support this call: */ 116 unsigned int x86_cache_size; 117 int x86_cache_alignment; /* In bytes */ 118 /* Cache QoS architectural values, valid only on the BSP: */ 119 int x86_cache_max_rmid; /* max index */ 120 int x86_cache_occ_scale; /* scale to bytes */ 121 int x86_cache_mbm_width_offset; 122 int x86_power; 123 unsigned long loops_per_jiffy; 124 /* protected processor identification number */ 125 u64 ppin; 126 /* cpuid returned max cores value: */ 127 u16 x86_max_cores; 128 u16 apicid; 129 u16 initial_apicid; 130 u16 x86_clflush_size; 131 /* number of cores as seen by the OS: */ 132 u16 booted_cores; 133 /* Physical processor id: */ 134 u16 phys_proc_id; 135 /* Logical processor id: */ 136 u16 logical_proc_id; 137 /* Core id: */ 138 u16 cpu_core_id; 139 u16 cpu_die_id; 140 u16 logical_die_id; 141 /* Index into per_cpu list: */ 142 u16 cpu_index; 143 /* Is SMT active on this core? */ 144 bool smt_active; 145 u32 microcode; 146 /* Address space bits used by the cache internally */ 147 u8 x86_cache_bits; 148 unsigned initialized : 1; 149 } __randomize_layout; 150 151 #define X86_VENDOR_INTEL 0 152 #define X86_VENDOR_CYRIX 1 153 #define X86_VENDOR_AMD 2 154 #define X86_VENDOR_UMC 3 155 #define X86_VENDOR_CENTAUR 5 156 #define X86_VENDOR_TRANSMETA 7 157 #define X86_VENDOR_NSC 8 158 #define X86_VENDOR_HYGON 9 159 #define X86_VENDOR_ZHAOXIN 10 160 #define X86_VENDOR_VORTEX 11 161 #define X86_VENDOR_NUM 12 162 163 #define X86_VENDOR_UNKNOWN 0xff 164 165 /* 166 * capabilities of CPUs 167 */ 168 extern struct cpuinfo_x86 boot_cpu_data; 169 extern struct cpuinfo_x86 new_cpu_data; 170 171 extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; 172 extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; 173 174 #ifdef CONFIG_SMP 175 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 176 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 177 #else 178 #define cpu_info boot_cpu_data 179 #define cpu_data(cpu) boot_cpu_data 180 #endif 181 182 extern const struct seq_operations cpuinfo_op; 183 184 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 185 186 extern void cpu_detect(struct cpuinfo_x86 *c); 187 188 static inline unsigned long long l1tf_pfn_limit(void) 189 { 190 return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT); 191 } 192 193 void init_cpu_devs(void); 194 void get_cpu_vendor(struct cpuinfo_x86 *c); 195 extern void early_cpu_init(void); 196 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 197 extern void print_cpu_info(struct cpuinfo_x86 *); 198 void print_cpu_msr(struct cpuinfo_x86 *); 199 200 /* 201 * Friendlier CR3 helpers. 202 */ 203 static inline unsigned long read_cr3_pa(void) 204 { 205 return __read_cr3() & CR3_ADDR_MASK; 206 } 207 208 static inline unsigned long native_read_cr3_pa(void) 209 { 210 return __native_read_cr3() & CR3_ADDR_MASK; 211 } 212 213 static inline void load_cr3(pgd_t *pgdir) 214 { 215 write_cr3(__sme_pa(pgdir)); 216 } 217 218 /* 219 * Note that while the legacy 'TSS' name comes from 'Task State Segment', 220 * on modern x86 CPUs the TSS also holds information important to 64-bit mode, 221 * unrelated to the task-switch mechanism: 222 */ 223 #ifdef CONFIG_X86_32 224 /* This is the TSS defined by the hardware. */ 225 struct x86_hw_tss { 226 unsigned short back_link, __blh; 227 unsigned long sp0; 228 unsigned short ss0, __ss0h; 229 unsigned long sp1; 230 231 /* 232 * We don't use ring 1, so ss1 is a convenient scratch space in 233 * the same cacheline as sp0. We use ss1 to cache the value in 234 * MSR_IA32_SYSENTER_CS. When we context switch 235 * MSR_IA32_SYSENTER_CS, we first check if the new value being 236 * written matches ss1, and, if it's not, then we wrmsr the new 237 * value and update ss1. 238 * 239 * The only reason we context switch MSR_IA32_SYSENTER_CS is 240 * that we set it to zero in vm86 tasks to avoid corrupting the 241 * stack if we were to go through the sysenter path from vm86 242 * mode. 243 */ 244 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ 245 246 unsigned short __ss1h; 247 unsigned long sp2; 248 unsigned short ss2, __ss2h; 249 unsigned long __cr3; 250 unsigned long ip; 251 unsigned long flags; 252 unsigned long ax; 253 unsigned long cx; 254 unsigned long dx; 255 unsigned long bx; 256 unsigned long sp; 257 unsigned long bp; 258 unsigned long si; 259 unsigned long di; 260 unsigned short es, __esh; 261 unsigned short cs, __csh; 262 unsigned short ss, __ssh; 263 unsigned short ds, __dsh; 264 unsigned short fs, __fsh; 265 unsigned short gs, __gsh; 266 unsigned short ldt, __ldth; 267 unsigned short trace; 268 unsigned short io_bitmap_base; 269 270 } __attribute__((packed)); 271 #else 272 struct x86_hw_tss { 273 u32 reserved1; 274 u64 sp0; 275 u64 sp1; 276 277 /* 278 * Since Linux does not use ring 2, the 'sp2' slot is unused by 279 * hardware. entry_SYSCALL_64 uses it as scratch space to stash 280 * the user RSP value. 281 */ 282 u64 sp2; 283 284 u64 reserved2; 285 u64 ist[7]; 286 u32 reserved3; 287 u32 reserved4; 288 u16 reserved5; 289 u16 io_bitmap_base; 290 291 } __attribute__((packed)); 292 #endif 293 294 /* 295 * IO-bitmap sizes: 296 */ 297 #define IO_BITMAP_BITS 65536 298 #define IO_BITMAP_BYTES (IO_BITMAP_BITS / BITS_PER_BYTE) 299 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES / sizeof(long)) 300 301 #define IO_BITMAP_OFFSET_VALID_MAP \ 302 (offsetof(struct tss_struct, io_bitmap.bitmap) - \ 303 offsetof(struct tss_struct, x86_tss)) 304 305 #define IO_BITMAP_OFFSET_VALID_ALL \ 306 (offsetof(struct tss_struct, io_bitmap.mapall) - \ 307 offsetof(struct tss_struct, x86_tss)) 308 309 #ifdef CONFIG_X86_IOPL_IOPERM 310 /* 311 * sizeof(unsigned long) coming from an extra "long" at the end of the 312 * iobitmap. The limit is inclusive, i.e. the last valid byte. 313 */ 314 # define __KERNEL_TSS_LIMIT \ 315 (IO_BITMAP_OFFSET_VALID_ALL + IO_BITMAP_BYTES + \ 316 sizeof(unsigned long) - 1) 317 #else 318 # define __KERNEL_TSS_LIMIT \ 319 (offsetof(struct tss_struct, x86_tss) + sizeof(struct x86_hw_tss) - 1) 320 #endif 321 322 /* Base offset outside of TSS_LIMIT so unpriviledged IO causes #GP */ 323 #define IO_BITMAP_OFFSET_INVALID (__KERNEL_TSS_LIMIT + 1) 324 325 struct entry_stack { 326 char stack[PAGE_SIZE]; 327 }; 328 329 struct entry_stack_page { 330 struct entry_stack stack; 331 } __aligned(PAGE_SIZE); 332 333 /* 334 * All IO bitmap related data stored in the TSS: 335 */ 336 struct x86_io_bitmap { 337 /* The sequence number of the last active bitmap. */ 338 u64 prev_sequence; 339 340 /* 341 * Store the dirty size of the last io bitmap offender. The next 342 * one will have to do the cleanup as the switch out to a non io 343 * bitmap user will just set x86_tss.io_bitmap_base to a value 344 * outside of the TSS limit. So for sane tasks there is no need to 345 * actually touch the io_bitmap at all. 346 */ 347 unsigned int prev_max; 348 349 /* 350 * The extra 1 is there because the CPU will access an 351 * additional byte beyond the end of the IO permission 352 * bitmap. The extra byte must be all 1 bits, and must 353 * be within the limit. 354 */ 355 unsigned long bitmap[IO_BITMAP_LONGS + 1]; 356 357 /* 358 * Special I/O bitmap to emulate IOPL(3). All bytes zero, 359 * except the additional byte at the end. 360 */ 361 unsigned long mapall[IO_BITMAP_LONGS + 1]; 362 }; 363 364 struct tss_struct { 365 /* 366 * The fixed hardware portion. This must not cross a page boundary 367 * at risk of violating the SDM's advice and potentially triggering 368 * errata. 369 */ 370 struct x86_hw_tss x86_tss; 371 372 struct x86_io_bitmap io_bitmap; 373 } __aligned(PAGE_SIZE); 374 375 DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw); 376 377 /* Per CPU interrupt stacks */ 378 struct irq_stack { 379 char stack[IRQ_STACK_SIZE]; 380 } __aligned(IRQ_STACK_SIZE); 381 382 #ifdef CONFIG_X86_64 383 struct fixed_percpu_data { 384 /* 385 * GCC hardcodes the stack canary as %gs:40. Since the 386 * irq_stack is the object at %gs:0, we reserve the bottom 387 * 48 bytes of the irq stack for the canary. 388 * 389 * Once we are willing to require -mstack-protector-guard-symbol= 390 * support for x86_64 stackprotector, we can get rid of this. 391 */ 392 char gs_base[40]; 393 unsigned long stack_canary; 394 }; 395 396 DECLARE_PER_CPU_FIRST(struct fixed_percpu_data, fixed_percpu_data) __visible; 397 DECLARE_INIT_PER_CPU(fixed_percpu_data); 398 399 static inline unsigned long cpu_kernelmode_gs_base(int cpu) 400 { 401 return (unsigned long)per_cpu(fixed_percpu_data.gs_base, cpu); 402 } 403 404 extern asmlinkage void entry_SYSCALL32_ignore(void); 405 406 /* Save actual FS/GS selectors and bases to current->thread */ 407 void current_save_fsgs(void); 408 #else /* X86_64 */ 409 #ifdef CONFIG_STACKPROTECTOR 410 DECLARE_PER_CPU(unsigned long, __stack_chk_guard); 411 #endif 412 #endif /* !X86_64 */ 413 414 struct perf_event; 415 416 struct thread_struct { 417 /* Cached TLS descriptors: */ 418 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 419 #ifdef CONFIG_X86_32 420 unsigned long sp0; 421 #endif 422 unsigned long sp; 423 #ifdef CONFIG_X86_32 424 unsigned long sysenter_cs; 425 #else 426 unsigned short es; 427 unsigned short ds; 428 unsigned short fsindex; 429 unsigned short gsindex; 430 #endif 431 432 #ifdef CONFIG_X86_64 433 unsigned long fsbase; 434 unsigned long gsbase; 435 #else 436 /* 437 * XXX: this could presumably be unsigned short. Alternatively, 438 * 32-bit kernels could be taught to use fsindex instead. 439 */ 440 unsigned long fs; 441 unsigned long gs; 442 #endif 443 444 /* Save middle states of ptrace breakpoints */ 445 struct perf_event *ptrace_bps[HBP_NUM]; 446 /* Debug status used for traps, single steps, etc... */ 447 unsigned long virtual_dr6; 448 /* Keep track of the exact dr7 value set by the user */ 449 unsigned long ptrace_dr7; 450 /* Fault info: */ 451 unsigned long cr2; 452 unsigned long trap_nr; 453 unsigned long error_code; 454 #ifdef CONFIG_VM86 455 /* Virtual 86 mode info */ 456 struct vm86 *vm86; 457 #endif 458 /* IO permissions: */ 459 struct io_bitmap *io_bitmap; 460 461 /* 462 * IOPL. Privilege level dependent I/O permission which is 463 * emulated via the I/O bitmap to prevent user space from disabling 464 * interrupts. 465 */ 466 unsigned long iopl_emul; 467 468 unsigned int iopl_warn:1; 469 470 /* 471 * Protection Keys Register for Userspace. Loaded immediately on 472 * context switch. Store it in thread_struct to avoid a lookup in 473 * the tasks's FPU xstate buffer. This value is only valid when a 474 * task is scheduled out. For 'current' the authoritative source of 475 * PKRU is the hardware itself. 476 */ 477 u32 pkru; 478 479 #ifdef CONFIG_X86_USER_SHADOW_STACK 480 unsigned long features; 481 unsigned long features_locked; 482 483 struct thread_shstk shstk; 484 #endif 485 486 /* Floating point and extended processor state */ 487 struct fpu fpu; 488 /* 489 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at 490 * the end. 491 */ 492 }; 493 494 extern void fpu_thread_struct_whitelist(unsigned long *offset, unsigned long *size); 495 496 static inline void arch_thread_struct_whitelist(unsigned long *offset, 497 unsigned long *size) 498 { 499 fpu_thread_struct_whitelist(offset, size); 500 } 501 502 static inline void 503 native_load_sp0(unsigned long sp0) 504 { 505 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0); 506 } 507 508 static __always_inline void native_swapgs(void) 509 { 510 #ifdef CONFIG_X86_64 511 asm volatile("swapgs" ::: "memory"); 512 #endif 513 } 514 515 static __always_inline unsigned long current_top_of_stack(void) 516 { 517 /* 518 * We can't read directly from tss.sp0: sp0 on x86_32 is special in 519 * and around vm86 mode and sp0 on x86_64 is special because of the 520 * entry trampoline. 521 */ 522 return this_cpu_read_stable(pcpu_hot.top_of_stack); 523 } 524 525 static __always_inline bool on_thread_stack(void) 526 { 527 return (unsigned long)(current_top_of_stack() - 528 current_stack_pointer) < THREAD_SIZE; 529 } 530 531 #ifdef CONFIG_PARAVIRT_XXL 532 #include <asm/paravirt.h> 533 #else 534 535 static inline void load_sp0(unsigned long sp0) 536 { 537 native_load_sp0(sp0); 538 } 539 540 #endif /* CONFIG_PARAVIRT_XXL */ 541 542 unsigned long __get_wchan(struct task_struct *p); 543 544 extern void select_idle_routine(const struct cpuinfo_x86 *c); 545 extern void amd_e400_c1e_apic_setup(void); 546 547 extern unsigned long boot_option_idle_override; 548 549 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 550 IDLE_POLL}; 551 552 extern void enable_sep_cpu(void); 553 554 555 /* Defined in head.S */ 556 extern struct desc_ptr early_gdt_descr; 557 558 extern void switch_gdt_and_percpu_base(int); 559 extern void load_direct_gdt(int); 560 extern void load_fixmap_gdt(int); 561 extern void cpu_init(void); 562 extern void cpu_init_exception_handling(void); 563 extern void cr4_init(void); 564 565 static inline unsigned long get_debugctlmsr(void) 566 { 567 unsigned long debugctlmsr = 0; 568 569 #ifndef CONFIG_X86_DEBUGCTLMSR 570 if (boot_cpu_data.x86 < 6) 571 return 0; 572 #endif 573 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 574 575 return debugctlmsr; 576 } 577 578 static inline void update_debugctlmsr(unsigned long debugctlmsr) 579 { 580 #ifndef CONFIG_X86_DEBUGCTLMSR 581 if (boot_cpu_data.x86 < 6) 582 return; 583 #endif 584 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 585 } 586 587 extern void set_task_blockstep(struct task_struct *task, bool on); 588 589 /* Boot loader type from the setup header: */ 590 extern int bootloader_type; 591 extern int bootloader_version; 592 593 extern char ignore_fpu_irq; 594 595 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 596 #define ARCH_HAS_PREFETCHW 597 598 #ifdef CONFIG_X86_32 599 # define BASE_PREFETCH "" 600 # define ARCH_HAS_PREFETCH 601 #else 602 # define BASE_PREFETCH "prefetcht0 %P1" 603 #endif 604 605 /* 606 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 607 * 608 * It's not worth to care about 3dnow prefetches for the K6 609 * because they are microcoded there and very slow. 610 */ 611 static inline void prefetch(const void *x) 612 { 613 alternative_input(BASE_PREFETCH, "prefetchnta %P1", 614 X86_FEATURE_XMM, 615 "m" (*(const char *)x)); 616 } 617 618 /* 619 * 3dnow prefetch to get an exclusive cache line. 620 * Useful for spinlocks to avoid one state transition in the 621 * cache coherency protocol: 622 */ 623 static __always_inline void prefetchw(const void *x) 624 { 625 alternative_input(BASE_PREFETCH, "prefetchw %P1", 626 X86_FEATURE_3DNOWPREFETCH, 627 "m" (*(const char *)x)); 628 } 629 630 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ 631 TOP_OF_KERNEL_STACK_PADDING) 632 633 #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1)) 634 635 #define task_pt_regs(task) \ 636 ({ \ 637 unsigned long __ptr = (unsigned long)task_stack_page(task); \ 638 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ 639 ((struct pt_regs *)__ptr) - 1; \ 640 }) 641 642 #ifdef CONFIG_X86_32 643 #define INIT_THREAD { \ 644 .sp0 = TOP_OF_INIT_STACK, \ 645 .sysenter_cs = __KERNEL_CS, \ 646 } 647 648 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 649 650 #else 651 extern unsigned long __end_init_task[]; 652 653 #define INIT_THREAD { \ 654 .sp = (unsigned long)&__end_init_task - sizeof(struct pt_regs), \ 655 } 656 657 extern unsigned long KSTK_ESP(struct task_struct *task); 658 659 #endif /* CONFIG_X86_64 */ 660 661 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 662 unsigned long new_sp); 663 664 /* 665 * This decides where the kernel will search for a free chunk of vm 666 * space during mmap's. 667 */ 668 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3)) 669 #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW) 670 671 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 672 673 /* Get/set a process' ability to use the timestamp counter instruction */ 674 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 675 #define SET_TSC_CTL(val) set_tsc_mode((val)) 676 677 extern int get_tsc_mode(unsigned long adr); 678 extern int set_tsc_mode(unsigned int val); 679 680 DECLARE_PER_CPU(u64, msr_misc_features_shadow); 681 682 extern u16 get_llc_id(unsigned int cpu); 683 684 #ifdef CONFIG_CPU_SUP_AMD 685 extern u32 amd_get_nodes_per_socket(void); 686 extern u32 amd_get_highest_perf(void); 687 extern void amd_clear_divider(void); 688 extern void amd_check_microcode(void); 689 #else 690 static inline u32 amd_get_nodes_per_socket(void) { return 0; } 691 static inline u32 amd_get_highest_perf(void) { return 0; } 692 static inline void amd_clear_divider(void) { } 693 static inline void amd_check_microcode(void) { } 694 #endif 695 696 extern unsigned long arch_align_stack(unsigned long sp); 697 void free_init_pages(const char *what, unsigned long begin, unsigned long end); 698 extern void free_kernel_image_pages(const char *what, void *begin, void *end); 699 700 void default_idle(void); 701 #ifdef CONFIG_XEN 702 bool xen_set_default_idle(void); 703 #else 704 #define xen_set_default_idle 0 705 #endif 706 707 void __noreturn stop_this_cpu(void *dummy); 708 void microcode_check(struct cpuinfo_x86 *prev_info); 709 void store_cpu_caps(struct cpuinfo_x86 *info); 710 711 enum l1tf_mitigations { 712 L1TF_MITIGATION_OFF, 713 L1TF_MITIGATION_FLUSH_NOWARN, 714 L1TF_MITIGATION_FLUSH, 715 L1TF_MITIGATION_FLUSH_NOSMT, 716 L1TF_MITIGATION_FULL, 717 L1TF_MITIGATION_FULL_FORCE 718 }; 719 720 extern enum l1tf_mitigations l1tf_mitigation; 721 722 enum mds_mitigations { 723 MDS_MITIGATION_OFF, 724 MDS_MITIGATION_FULL, 725 MDS_MITIGATION_VMWERV, 726 }; 727 728 #ifdef CONFIG_X86_SGX 729 int arch_memory_failure(unsigned long pfn, int flags); 730 #define arch_memory_failure arch_memory_failure 731 732 bool arch_is_platform_page(u64 paddr); 733 #define arch_is_platform_page arch_is_platform_page 734 #endif 735 736 extern bool gds_ucode_mitigated(void); 737 738 /* 739 * Make previous memory operations globally visible before 740 * a WRMSR. 741 * 742 * MFENCE makes writes visible, but only affects load/store 743 * instructions. WRMSR is unfortunately not a load/store 744 * instruction and is unaffected by MFENCE. The LFENCE ensures 745 * that the WRMSR is not reordered. 746 * 747 * Most WRMSRs are full serializing instructions themselves and 748 * do not require this barrier. This is only required for the 749 * IA32_TSC_DEADLINE and X2APIC MSRs. 750 */ 751 static inline void weak_wrmsr_fence(void) 752 { 753 alternative("mfence; lfence", "", ALT_NOT(X86_FEATURE_APIC_MSRS_FENCE)); 754 } 755 756 #endif /* _ASM_X86_PROCESSOR_H */ 757