1 #ifndef _ASM_X86_PROCESSOR_H 2 #define _ASM_X86_PROCESSOR_H 3 4 #include <asm/processor-flags.h> 5 6 /* Forward declaration, a strange C thing */ 7 struct task_struct; 8 struct mm_struct; 9 struct vm86; 10 11 #include <asm/math_emu.h> 12 #include <asm/segment.h> 13 #include <asm/types.h> 14 #include <uapi/asm/sigcontext.h> 15 #include <asm/current.h> 16 #include <asm/cpufeatures.h> 17 #include <asm/page.h> 18 #include <asm/pgtable_types.h> 19 #include <asm/percpu.h> 20 #include <asm/msr.h> 21 #include <asm/desc_defs.h> 22 #include <asm/nops.h> 23 #include <asm/special_insns.h> 24 #include <asm/fpu/types.h> 25 26 #include <linux/personality.h> 27 #include <linux/cache.h> 28 #include <linux/threads.h> 29 #include <linux/math64.h> 30 #include <linux/err.h> 31 #include <linux/irqflags.h> 32 33 /* 34 * We handle most unaligned accesses in hardware. On the other hand 35 * unaligned DMA can be quite expensive on some Nehalem processors. 36 * 37 * Based on this we disable the IP header alignment in network drivers. 38 */ 39 #define NET_IP_ALIGN 0 40 41 #define HBP_NUM 4 42 /* 43 * Default implementation of macro that returns current 44 * instruction pointer ("program counter"). 45 */ 46 static inline void *current_text_addr(void) 47 { 48 void *pc; 49 50 asm volatile("mov $1f, %0; 1:":"=r" (pc)); 51 52 return pc; 53 } 54 55 /* 56 * These alignment constraints are for performance in the vSMP case, 57 * but in the task_struct case we must also meet hardware imposed 58 * alignment requirements of the FPU state: 59 */ 60 #ifdef CONFIG_X86_VSMP 61 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 62 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 63 #else 64 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state) 65 # define ARCH_MIN_MMSTRUCT_ALIGN 0 66 #endif 67 68 enum tlb_infos { 69 ENTRIES, 70 NR_INFO 71 }; 72 73 extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 74 extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 75 extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 76 extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 77 extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 78 extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 79 extern u16 __read_mostly tlb_lld_1g[NR_INFO]; 80 81 /* 82 * CPU type and hardware bug flags. Kept separately for each CPU. 83 * Members of this structure are referenced in head.S, so think twice 84 * before touching them. [mj] 85 */ 86 87 struct cpuinfo_x86 { 88 __u8 x86; /* CPU family */ 89 __u8 x86_vendor; /* CPU vendor */ 90 __u8 x86_model; 91 __u8 x86_mask; 92 #ifdef CONFIG_X86_32 93 char wp_works_ok; /* It doesn't on 386's */ 94 95 /* Problems on some 486Dx4's and old 386's: */ 96 char rfu; 97 char pad0; 98 char pad1; 99 #else 100 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 101 int x86_tlbsize; 102 #endif 103 __u8 x86_virt_bits; 104 __u8 x86_phys_bits; 105 /* CPUID returned core id bits: */ 106 __u8 x86_coreid_bits; 107 /* Max extended CPUID function supported: */ 108 __u32 extended_cpuid_level; 109 /* Maximum supported CPUID level, -1=no CPUID: */ 110 int cpuid_level; 111 __u32 x86_capability[NCAPINTS + NBUGINTS]; 112 char x86_vendor_id[16]; 113 char x86_model_id[64]; 114 /* in KB - valid for CPUS which support this call: */ 115 int x86_cache_size; 116 int x86_cache_alignment; /* In bytes */ 117 /* Cache QoS architectural values: */ 118 int x86_cache_max_rmid; /* max index */ 119 int x86_cache_occ_scale; /* scale to bytes */ 120 int x86_power; 121 unsigned long loops_per_jiffy; 122 /* cpuid returned max cores value: */ 123 u16 x86_max_cores; 124 u16 apicid; 125 u16 initial_apicid; 126 u16 x86_clflush_size; 127 /* number of cores as seen by the OS: */ 128 u16 booted_cores; 129 /* Physical processor id: */ 130 u16 phys_proc_id; 131 /* Logical processor id: */ 132 u16 logical_proc_id; 133 /* Core id: */ 134 u16 cpu_core_id; 135 /* Index into per_cpu list: */ 136 u16 cpu_index; 137 u32 microcode; 138 }; 139 140 struct cpuid_regs { 141 u32 eax, ebx, ecx, edx; 142 }; 143 144 enum cpuid_regs_idx { 145 CPUID_EAX = 0, 146 CPUID_EBX, 147 CPUID_ECX, 148 CPUID_EDX, 149 }; 150 151 #define X86_VENDOR_INTEL 0 152 #define X86_VENDOR_CYRIX 1 153 #define X86_VENDOR_AMD 2 154 #define X86_VENDOR_UMC 3 155 #define X86_VENDOR_CENTAUR 5 156 #define X86_VENDOR_TRANSMETA 7 157 #define X86_VENDOR_NSC 8 158 #define X86_VENDOR_NUM 9 159 160 #define X86_VENDOR_UNKNOWN 0xff 161 162 /* 163 * capabilities of CPUs 164 */ 165 extern struct cpuinfo_x86 boot_cpu_data; 166 extern struct cpuinfo_x86 new_cpu_data; 167 168 extern struct tss_struct doublefault_tss; 169 extern __u32 cpu_caps_cleared[NCAPINTS]; 170 extern __u32 cpu_caps_set[NCAPINTS]; 171 172 #ifdef CONFIG_SMP 173 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 174 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 175 #else 176 #define cpu_info boot_cpu_data 177 #define cpu_data(cpu) boot_cpu_data 178 #endif 179 180 extern const struct seq_operations cpuinfo_op; 181 182 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 183 184 extern void cpu_detect(struct cpuinfo_x86 *c); 185 186 extern void early_cpu_init(void); 187 extern void identify_boot_cpu(void); 188 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 189 extern void print_cpu_info(struct cpuinfo_x86 *); 190 void print_cpu_msr(struct cpuinfo_x86 *); 191 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); 192 extern u32 get_scattered_cpuid_leaf(unsigned int level, 193 unsigned int sub_leaf, 194 enum cpuid_regs_idx reg); 195 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); 196 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); 197 198 extern void detect_extended_topology(struct cpuinfo_x86 *c); 199 extern void detect_ht(struct cpuinfo_x86 *c); 200 201 #ifdef CONFIG_X86_32 202 extern int have_cpuid_p(void); 203 #else 204 static inline int have_cpuid_p(void) 205 { 206 return 1; 207 } 208 #endif 209 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 210 unsigned int *ecx, unsigned int *edx) 211 { 212 /* ecx is often an input as well as an output. */ 213 asm volatile("cpuid" 214 : "=a" (*eax), 215 "=b" (*ebx), 216 "=c" (*ecx), 217 "=d" (*edx) 218 : "0" (*eax), "2" (*ecx) 219 : "memory"); 220 } 221 222 #define native_cpuid_reg(reg) \ 223 static inline unsigned int native_cpuid_##reg(unsigned int op) \ 224 { \ 225 unsigned int eax = op, ebx, ecx = 0, edx; \ 226 \ 227 native_cpuid(&eax, &ebx, &ecx, &edx); \ 228 \ 229 return reg; \ 230 } 231 232 /* 233 * Native CPUID functions returning a single datum. 234 */ 235 native_cpuid_reg(eax) 236 native_cpuid_reg(ebx) 237 native_cpuid_reg(ecx) 238 native_cpuid_reg(edx) 239 240 static inline void load_cr3(pgd_t *pgdir) 241 { 242 write_cr3(__pa(pgdir)); 243 } 244 245 #ifdef CONFIG_X86_32 246 /* This is the TSS defined by the hardware. */ 247 struct x86_hw_tss { 248 unsigned short back_link, __blh; 249 unsigned long sp0; 250 unsigned short ss0, __ss0h; 251 unsigned long sp1; 252 253 /* 254 * We don't use ring 1, so ss1 is a convenient scratch space in 255 * the same cacheline as sp0. We use ss1 to cache the value in 256 * MSR_IA32_SYSENTER_CS. When we context switch 257 * MSR_IA32_SYSENTER_CS, we first check if the new value being 258 * written matches ss1, and, if it's not, then we wrmsr the new 259 * value and update ss1. 260 * 261 * The only reason we context switch MSR_IA32_SYSENTER_CS is 262 * that we set it to zero in vm86 tasks to avoid corrupting the 263 * stack if we were to go through the sysenter path from vm86 264 * mode. 265 */ 266 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ 267 268 unsigned short __ss1h; 269 unsigned long sp2; 270 unsigned short ss2, __ss2h; 271 unsigned long __cr3; 272 unsigned long ip; 273 unsigned long flags; 274 unsigned long ax; 275 unsigned long cx; 276 unsigned long dx; 277 unsigned long bx; 278 unsigned long sp; 279 unsigned long bp; 280 unsigned long si; 281 unsigned long di; 282 unsigned short es, __esh; 283 unsigned short cs, __csh; 284 unsigned short ss, __ssh; 285 unsigned short ds, __dsh; 286 unsigned short fs, __fsh; 287 unsigned short gs, __gsh; 288 unsigned short ldt, __ldth; 289 unsigned short trace; 290 unsigned short io_bitmap_base; 291 292 } __attribute__((packed)); 293 #else 294 struct x86_hw_tss { 295 u32 reserved1; 296 u64 sp0; 297 u64 sp1; 298 u64 sp2; 299 u64 reserved2; 300 u64 ist[7]; 301 u32 reserved3; 302 u32 reserved4; 303 u16 reserved5; 304 u16 io_bitmap_base; 305 306 } __attribute__((packed)); 307 #endif 308 309 /* 310 * IO-bitmap sizes: 311 */ 312 #define IO_BITMAP_BITS 65536 313 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) 314 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) 315 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) 316 #define INVALID_IO_BITMAP_OFFSET 0x8000 317 318 struct tss_struct { 319 /* 320 * The hardware state: 321 */ 322 struct x86_hw_tss x86_tss; 323 324 /* 325 * The extra 1 is there because the CPU will access an 326 * additional byte beyond the end of the IO permission 327 * bitmap. The extra byte must be all 1 bits, and must 328 * be within the limit. 329 */ 330 unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; 331 332 #ifdef CONFIG_X86_32 333 /* 334 * Space for the temporary SYSENTER stack. 335 */ 336 unsigned long SYSENTER_stack_canary; 337 unsigned long SYSENTER_stack[64]; 338 #endif 339 340 } ____cacheline_aligned; 341 342 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss); 343 344 /* 345 * sizeof(unsigned long) coming from an extra "long" at the end 346 * of the iobitmap. 347 * 348 * -1? seg base+limit should be pointing to the address of the 349 * last valid byte 350 */ 351 #define __KERNEL_TSS_LIMIT \ 352 (IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1) 353 354 #ifdef CONFIG_X86_32 355 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack); 356 #endif 357 358 /* 359 * Save the original ist values for checking stack pointers during debugging 360 */ 361 struct orig_ist { 362 unsigned long ist[7]; 363 }; 364 365 #ifdef CONFIG_X86_64 366 DECLARE_PER_CPU(struct orig_ist, orig_ist); 367 368 union irq_stack_union { 369 char irq_stack[IRQ_STACK_SIZE]; 370 /* 371 * GCC hardcodes the stack canary as %gs:40. Since the 372 * irq_stack is the object at %gs:0, we reserve the bottom 373 * 48 bytes of the irq stack for the canary. 374 */ 375 struct { 376 char gs_base[40]; 377 unsigned long stack_canary; 378 }; 379 }; 380 381 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible; 382 DECLARE_INIT_PER_CPU(irq_stack_union); 383 384 DECLARE_PER_CPU(char *, irq_stack_ptr); 385 DECLARE_PER_CPU(unsigned int, irq_count); 386 extern asmlinkage void ignore_sysret(void); 387 #else /* X86_64 */ 388 #ifdef CONFIG_CC_STACKPROTECTOR 389 /* 390 * Make sure stack canary segment base is cached-aligned: 391 * "For Intel Atom processors, avoid non zero segment base address 392 * that is not aligned to cache line boundary at all cost." 393 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) 394 */ 395 struct stack_canary { 396 char __pad[20]; /* canary at %gs:20 */ 397 unsigned long canary; 398 }; 399 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 400 #endif 401 /* 402 * per-CPU IRQ handling stacks 403 */ 404 struct irq_stack { 405 u32 stack[THREAD_SIZE/sizeof(u32)]; 406 } __aligned(THREAD_SIZE); 407 408 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack); 409 DECLARE_PER_CPU(struct irq_stack *, softirq_stack); 410 #endif /* X86_64 */ 411 412 extern unsigned int fpu_kernel_xstate_size; 413 extern unsigned int fpu_user_xstate_size; 414 415 struct perf_event; 416 417 typedef struct { 418 unsigned long seg; 419 } mm_segment_t; 420 421 struct thread_struct { 422 /* Cached TLS descriptors: */ 423 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 424 unsigned long sp0; 425 unsigned long sp; 426 #ifdef CONFIG_X86_32 427 unsigned long sysenter_cs; 428 #else 429 unsigned short es; 430 unsigned short ds; 431 unsigned short fsindex; 432 unsigned short gsindex; 433 #endif 434 435 u32 status; /* thread synchronous flags */ 436 437 #ifdef CONFIG_X86_64 438 unsigned long fsbase; 439 unsigned long gsbase; 440 #else 441 /* 442 * XXX: this could presumably be unsigned short. Alternatively, 443 * 32-bit kernels could be taught to use fsindex instead. 444 */ 445 unsigned long fs; 446 unsigned long gs; 447 #endif 448 449 /* Save middle states of ptrace breakpoints */ 450 struct perf_event *ptrace_bps[HBP_NUM]; 451 /* Debug status used for traps, single steps, etc... */ 452 unsigned long debugreg6; 453 /* Keep track of the exact dr7 value set by the user */ 454 unsigned long ptrace_dr7; 455 /* Fault info: */ 456 unsigned long cr2; 457 unsigned long trap_nr; 458 unsigned long error_code; 459 #ifdef CONFIG_VM86 460 /* Virtual 86 mode info */ 461 struct vm86 *vm86; 462 #endif 463 /* IO permissions: */ 464 unsigned long *io_bitmap_ptr; 465 unsigned long iopl; 466 /* Max allowed port in the bitmap, in bytes: */ 467 unsigned io_bitmap_max; 468 469 mm_segment_t addr_limit; 470 471 unsigned int sig_on_uaccess_err:1; 472 unsigned int uaccess_err:1; /* uaccess failed */ 473 474 /* Floating point and extended processor state */ 475 struct fpu fpu; 476 /* 477 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at 478 * the end. 479 */ 480 }; 481 482 /* 483 * Thread-synchronous status. 484 * 485 * This is different from the flags in that nobody else 486 * ever touches our thread-synchronous status, so we don't 487 * have to worry about atomic accesses. 488 */ 489 #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/ 490 491 /* 492 * Set IOPL bits in EFLAGS from given mask 493 */ 494 static inline void native_set_iopl_mask(unsigned mask) 495 { 496 #ifdef CONFIG_X86_32 497 unsigned int reg; 498 499 asm volatile ("pushfl;" 500 "popl %0;" 501 "andl %1, %0;" 502 "orl %2, %0;" 503 "pushl %0;" 504 "popfl" 505 : "=&r" (reg) 506 : "i" (~X86_EFLAGS_IOPL), "r" (mask)); 507 #endif 508 } 509 510 static inline void 511 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread) 512 { 513 tss->x86_tss.sp0 = thread->sp0; 514 #ifdef CONFIG_X86_32 515 /* Only happens when SEP is enabled, no need to test "SEP"arately: */ 516 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { 517 tss->x86_tss.ss1 = thread->sysenter_cs; 518 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); 519 } 520 #endif 521 } 522 523 static inline void native_swapgs(void) 524 { 525 #ifdef CONFIG_X86_64 526 asm volatile("swapgs" ::: "memory"); 527 #endif 528 } 529 530 static inline unsigned long current_top_of_stack(void) 531 { 532 #ifdef CONFIG_X86_64 533 return this_cpu_read_stable(cpu_tss.x86_tss.sp0); 534 #else 535 /* sp0 on x86_32 is special in and around vm86 mode. */ 536 return this_cpu_read_stable(cpu_current_top_of_stack); 537 #endif 538 } 539 540 #ifdef CONFIG_PARAVIRT 541 #include <asm/paravirt.h> 542 #else 543 #define __cpuid native_cpuid 544 545 static inline void load_sp0(struct tss_struct *tss, 546 struct thread_struct *thread) 547 { 548 native_load_sp0(tss, thread); 549 } 550 551 #define set_iopl_mask native_set_iopl_mask 552 #endif /* CONFIG_PARAVIRT */ 553 554 /* Free all resources held by a thread. */ 555 extern void release_thread(struct task_struct *); 556 557 unsigned long get_wchan(struct task_struct *p); 558 559 /* 560 * Generic CPUID function 561 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 562 * resulting in stale register contents being returned. 563 */ 564 static inline void cpuid(unsigned int op, 565 unsigned int *eax, unsigned int *ebx, 566 unsigned int *ecx, unsigned int *edx) 567 { 568 *eax = op; 569 *ecx = 0; 570 __cpuid(eax, ebx, ecx, edx); 571 } 572 573 /* Some CPUID calls want 'count' to be placed in ecx */ 574 static inline void cpuid_count(unsigned int op, int count, 575 unsigned int *eax, unsigned int *ebx, 576 unsigned int *ecx, unsigned int *edx) 577 { 578 *eax = op; 579 *ecx = count; 580 __cpuid(eax, ebx, ecx, edx); 581 } 582 583 /* 584 * CPUID functions returning a single datum 585 */ 586 static inline unsigned int cpuid_eax(unsigned int op) 587 { 588 unsigned int eax, ebx, ecx, edx; 589 590 cpuid(op, &eax, &ebx, &ecx, &edx); 591 592 return eax; 593 } 594 595 static inline unsigned int cpuid_ebx(unsigned int op) 596 { 597 unsigned int eax, ebx, ecx, edx; 598 599 cpuid(op, &eax, &ebx, &ecx, &edx); 600 601 return ebx; 602 } 603 604 static inline unsigned int cpuid_ecx(unsigned int op) 605 { 606 unsigned int eax, ebx, ecx, edx; 607 608 cpuid(op, &eax, &ebx, &ecx, &edx); 609 610 return ecx; 611 } 612 613 static inline unsigned int cpuid_edx(unsigned int op) 614 { 615 unsigned int eax, ebx, ecx, edx; 616 617 cpuid(op, &eax, &ebx, &ecx, &edx); 618 619 return edx; 620 } 621 622 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 623 static __always_inline void rep_nop(void) 624 { 625 asm volatile("rep; nop" ::: "memory"); 626 } 627 628 static __always_inline void cpu_relax(void) 629 { 630 rep_nop(); 631 } 632 633 /* 634 * This function forces the icache and prefetched instruction stream to 635 * catch up with reality in two very specific cases: 636 * 637 * a) Text was modified using one virtual address and is about to be executed 638 * from the same physical page at a different virtual address. 639 * 640 * b) Text was modified on a different CPU, may subsequently be 641 * executed on this CPU, and you want to make sure the new version 642 * gets executed. This generally means you're calling this in a IPI. 643 * 644 * If you're calling this for a different reason, you're probably doing 645 * it wrong. 646 */ 647 static inline void sync_core(void) 648 { 649 /* 650 * There are quite a few ways to do this. IRET-to-self is nice 651 * because it works on every CPU, at any CPL (so it's compatible 652 * with paravirtualization), and it never exits to a hypervisor. 653 * The only down sides are that it's a bit slow (it seems to be 654 * a bit more than 2x slower than the fastest options) and that 655 * it unmasks NMIs. The "push %cs" is needed because, in 656 * paravirtual environments, __KERNEL_CS may not be a valid CS 657 * value when we do IRET directly. 658 * 659 * In case NMI unmasking or performance ever becomes a problem, 660 * the next best option appears to be MOV-to-CR2 and an 661 * unconditional jump. That sequence also works on all CPUs, 662 * but it will fault at CPL3 (i.e. Xen PV and lguest). 663 * 664 * CPUID is the conventional way, but it's nasty: it doesn't 665 * exist on some 486-like CPUs, and it usually exits to a 666 * hypervisor. 667 * 668 * Like all of Linux's memory ordering operations, this is a 669 * compiler barrier as well. 670 */ 671 register void *__sp asm(_ASM_SP); 672 673 #ifdef CONFIG_X86_32 674 asm volatile ( 675 "pushfl\n\t" 676 "pushl %%cs\n\t" 677 "pushl $1f\n\t" 678 "iret\n\t" 679 "1:" 680 : "+r" (__sp) : : "memory"); 681 #else 682 unsigned int tmp; 683 684 asm volatile ( 685 "mov %%ss, %0\n\t" 686 "pushq %q0\n\t" 687 "pushq %%rsp\n\t" 688 "addq $8, (%%rsp)\n\t" 689 "pushfq\n\t" 690 "mov %%cs, %0\n\t" 691 "pushq %q0\n\t" 692 "pushq $1f\n\t" 693 "iretq\n\t" 694 "1:" 695 : "=&r" (tmp), "+r" (__sp) : : "cc", "memory"); 696 #endif 697 } 698 699 extern void select_idle_routine(const struct cpuinfo_x86 *c); 700 extern void amd_e400_c1e_apic_setup(void); 701 702 extern unsigned long boot_option_idle_override; 703 704 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 705 IDLE_POLL}; 706 707 extern void enable_sep_cpu(void); 708 extern int sysenter_setup(void); 709 710 extern void early_trap_init(void); 711 void early_trap_pf_init(void); 712 713 /* Defined in head.S */ 714 extern struct desc_ptr early_gdt_descr; 715 716 extern void cpu_set_gdt(int); 717 extern void switch_to_new_gdt(int); 718 extern void load_percpu_segment(int); 719 extern void cpu_init(void); 720 721 static inline unsigned long get_debugctlmsr(void) 722 { 723 unsigned long debugctlmsr = 0; 724 725 #ifndef CONFIG_X86_DEBUGCTLMSR 726 if (boot_cpu_data.x86 < 6) 727 return 0; 728 #endif 729 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 730 731 return debugctlmsr; 732 } 733 734 static inline void update_debugctlmsr(unsigned long debugctlmsr) 735 { 736 #ifndef CONFIG_X86_DEBUGCTLMSR 737 if (boot_cpu_data.x86 < 6) 738 return; 739 #endif 740 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 741 } 742 743 extern void set_task_blockstep(struct task_struct *task, bool on); 744 745 /* Boot loader type from the setup header: */ 746 extern int bootloader_type; 747 extern int bootloader_version; 748 749 extern char ignore_fpu_irq; 750 751 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 752 #define ARCH_HAS_PREFETCHW 753 #define ARCH_HAS_SPINLOCK_PREFETCH 754 755 #ifdef CONFIG_X86_32 756 # define BASE_PREFETCH "" 757 # define ARCH_HAS_PREFETCH 758 #else 759 # define BASE_PREFETCH "prefetcht0 %P1" 760 #endif 761 762 /* 763 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 764 * 765 * It's not worth to care about 3dnow prefetches for the K6 766 * because they are microcoded there and very slow. 767 */ 768 static inline void prefetch(const void *x) 769 { 770 alternative_input(BASE_PREFETCH, "prefetchnta %P1", 771 X86_FEATURE_XMM, 772 "m" (*(const char *)x)); 773 } 774 775 /* 776 * 3dnow prefetch to get an exclusive cache line. 777 * Useful for spinlocks to avoid one state transition in the 778 * cache coherency protocol: 779 */ 780 static inline void prefetchw(const void *x) 781 { 782 alternative_input(BASE_PREFETCH, "prefetchw %P1", 783 X86_FEATURE_3DNOWPREFETCH, 784 "m" (*(const char *)x)); 785 } 786 787 static inline void spin_lock_prefetch(const void *x) 788 { 789 prefetchw(x); 790 } 791 792 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ 793 TOP_OF_KERNEL_STACK_PADDING) 794 795 #ifdef CONFIG_X86_32 796 /* 797 * User space process size: 3GB (default). 798 */ 799 #define TASK_SIZE PAGE_OFFSET 800 #define TASK_SIZE_MAX TASK_SIZE 801 #define STACK_TOP TASK_SIZE 802 #define STACK_TOP_MAX STACK_TOP 803 804 #define INIT_THREAD { \ 805 .sp0 = TOP_OF_INIT_STACK, \ 806 .sysenter_cs = __KERNEL_CS, \ 807 .io_bitmap_ptr = NULL, \ 808 .addr_limit = KERNEL_DS, \ 809 } 810 811 /* 812 * TOP_OF_KERNEL_STACK_PADDING reserves 8 bytes on top of the ring0 stack. 813 * This is necessary to guarantee that the entire "struct pt_regs" 814 * is accessible even if the CPU haven't stored the SS/ESP registers 815 * on the stack (interrupt gate does not save these registers 816 * when switching to the same priv ring). 817 * Therefore beware: accessing the ss/esp fields of the 818 * "struct pt_regs" is possible, but they may contain the 819 * completely wrong values. 820 */ 821 #define task_pt_regs(task) \ 822 ({ \ 823 unsigned long __ptr = (unsigned long)task_stack_page(task); \ 824 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ 825 ((struct pt_regs *)__ptr) - 1; \ 826 }) 827 828 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 829 830 #else 831 /* 832 * User space process size. 47bits minus one guard page. The guard 833 * page is necessary on Intel CPUs: if a SYSCALL instruction is at 834 * the highest possible canonical userspace address, then that 835 * syscall will enter the kernel with a non-canonical return 836 * address, and SYSRET will explode dangerously. We avoid this 837 * particular problem by preventing anything from being mapped 838 * at the maximum canonical address. 839 */ 840 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE) 841 842 /* This decides where the kernel will search for a free chunk of vm 843 * space during mmap's. 844 */ 845 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ 846 0xc0000000 : 0xFFFFe000) 847 848 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ 849 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 850 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ 851 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 852 853 #define STACK_TOP TASK_SIZE 854 #define STACK_TOP_MAX TASK_SIZE_MAX 855 856 #define INIT_THREAD { \ 857 .sp0 = TOP_OF_INIT_STACK, \ 858 .addr_limit = KERNEL_DS, \ 859 } 860 861 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) 862 extern unsigned long KSTK_ESP(struct task_struct *task); 863 864 #endif /* CONFIG_X86_64 */ 865 866 extern unsigned long thread_saved_pc(struct task_struct *tsk); 867 868 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 869 unsigned long new_sp); 870 871 /* 872 * This decides where the kernel will search for a free chunk of vm 873 * space during mmap's. 874 */ 875 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) 876 877 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 878 879 /* Get/set a process' ability to use the timestamp counter instruction */ 880 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 881 #define SET_TSC_CTL(val) set_tsc_mode((val)) 882 883 extern int get_tsc_mode(unsigned long adr); 884 extern int set_tsc_mode(unsigned int val); 885 886 /* Register/unregister a process' MPX related resource */ 887 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management() 888 #define MPX_DISABLE_MANAGEMENT() mpx_disable_management() 889 890 #ifdef CONFIG_X86_INTEL_MPX 891 extern int mpx_enable_management(void); 892 extern int mpx_disable_management(void); 893 #else 894 static inline int mpx_enable_management(void) 895 { 896 return -EINVAL; 897 } 898 static inline int mpx_disable_management(void) 899 { 900 return -EINVAL; 901 } 902 #endif /* CONFIG_X86_INTEL_MPX */ 903 904 extern u16 amd_get_nb_id(int cpu); 905 extern u32 amd_get_nodes_per_socket(void); 906 907 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves) 908 { 909 uint32_t base, eax, signature[3]; 910 911 for (base = 0x40000000; base < 0x40010000; base += 0x100) { 912 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); 913 914 if (!memcmp(sig, signature, 12) && 915 (leaves == 0 || ((eax - base) >= leaves))) 916 return base; 917 } 918 919 return 0; 920 } 921 922 extern unsigned long arch_align_stack(unsigned long sp); 923 extern void free_init_pages(char *what, unsigned long begin, unsigned long end); 924 925 void default_idle(void); 926 #ifdef CONFIG_XEN 927 bool xen_set_default_idle(void); 928 #else 929 #define xen_set_default_idle 0 930 #endif 931 932 void stop_this_cpu(void *dummy); 933 void df_debug(struct pt_regs *regs, long error_code); 934 #endif /* _ASM_X86_PROCESSOR_H */ 935