1 #ifndef _ASM_X86_PROCESSOR_H 2 #define _ASM_X86_PROCESSOR_H 3 4 #include <asm/processor-flags.h> 5 6 /* Forward declaration, a strange C thing */ 7 struct task_struct; 8 struct mm_struct; 9 10 #include <asm/vm86.h> 11 #include <asm/math_emu.h> 12 #include <asm/segment.h> 13 #include <asm/types.h> 14 #include <asm/sigcontext.h> 15 #include <asm/current.h> 16 #include <asm/cpufeature.h> 17 #include <asm/system.h> 18 #include <asm/page.h> 19 #include <asm/pgtable_types.h> 20 #include <asm/percpu.h> 21 #include <asm/msr.h> 22 #include <asm/desc_defs.h> 23 #include <asm/nops.h> 24 #include <asm/ds.h> 25 26 #include <linux/personality.h> 27 #include <linux/cpumask.h> 28 #include <linux/cache.h> 29 #include <linux/threads.h> 30 #include <linux/init.h> 31 32 /* 33 * Default implementation of macro that returns current 34 * instruction pointer ("program counter"). 35 */ 36 static inline void *current_text_addr(void) 37 { 38 void *pc; 39 40 asm volatile("mov $1f, %0; 1:":"=r" (pc)); 41 42 return pc; 43 } 44 45 #ifdef CONFIG_X86_VSMP 46 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 47 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 48 #else 49 # define ARCH_MIN_TASKALIGN 16 50 # define ARCH_MIN_MMSTRUCT_ALIGN 0 51 #endif 52 53 /* 54 * CPU type and hardware bug flags. Kept separately for each CPU. 55 * Members of this structure are referenced in head.S, so think twice 56 * before touching them. [mj] 57 */ 58 59 struct cpuinfo_x86 { 60 __u8 x86; /* CPU family */ 61 __u8 x86_vendor; /* CPU vendor */ 62 __u8 x86_model; 63 __u8 x86_mask; 64 #ifdef CONFIG_X86_32 65 char wp_works_ok; /* It doesn't on 386's */ 66 67 /* Problems on some 486Dx4's and old 386's: */ 68 char hlt_works_ok; 69 char hard_math; 70 char rfu; 71 char fdiv_bug; 72 char f00f_bug; 73 char coma_bug; 74 char pad0; 75 #else 76 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 77 int x86_tlbsize; 78 #endif 79 __u8 x86_virt_bits; 80 __u8 x86_phys_bits; 81 /* CPUID returned core id bits: */ 82 __u8 x86_coreid_bits; 83 /* Max extended CPUID function supported: */ 84 __u32 extended_cpuid_level; 85 /* Maximum supported CPUID level, -1=no CPUID: */ 86 int cpuid_level; 87 __u32 x86_capability[NCAPINTS]; 88 char x86_vendor_id[16]; 89 char x86_model_id[64]; 90 /* in KB - valid for CPUS which support this call: */ 91 int x86_cache_size; 92 int x86_cache_alignment; /* In bytes */ 93 int x86_power; 94 unsigned long loops_per_jiffy; 95 #ifdef CONFIG_SMP 96 /* cpus sharing the last level cache: */ 97 cpumask_var_t llc_shared_map; 98 #endif 99 /* cpuid returned max cores value: */ 100 u16 x86_max_cores; 101 u16 apicid; 102 u16 initial_apicid; 103 u16 x86_clflush_size; 104 #ifdef CONFIG_SMP 105 /* number of cores as seen by the OS: */ 106 u16 booted_cores; 107 /* Physical processor id: */ 108 u16 phys_proc_id; 109 /* Core id: */ 110 u16 cpu_core_id; 111 /* Index into per_cpu list: */ 112 u16 cpu_index; 113 #endif 114 unsigned int x86_hyper_vendor; 115 } __attribute__((__aligned__(SMP_CACHE_BYTES))); 116 117 #define X86_VENDOR_INTEL 0 118 #define X86_VENDOR_CYRIX 1 119 #define X86_VENDOR_AMD 2 120 #define X86_VENDOR_UMC 3 121 #define X86_VENDOR_CENTAUR 5 122 #define X86_VENDOR_TRANSMETA 7 123 #define X86_VENDOR_NSC 8 124 #define X86_VENDOR_NUM 9 125 126 #define X86_VENDOR_UNKNOWN 0xff 127 128 #define X86_HYPER_VENDOR_NONE 0 129 #define X86_HYPER_VENDOR_VMWARE 1 130 131 /* 132 * capabilities of CPUs 133 */ 134 extern struct cpuinfo_x86 boot_cpu_data; 135 extern struct cpuinfo_x86 new_cpu_data; 136 137 extern struct tss_struct doublefault_tss; 138 extern __u32 cleared_cpu_caps[NCAPINTS]; 139 140 #ifdef CONFIG_SMP 141 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info); 142 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 143 #define current_cpu_data __get_cpu_var(cpu_info) 144 #else 145 #define cpu_data(cpu) boot_cpu_data 146 #define current_cpu_data boot_cpu_data 147 #endif 148 149 extern const struct seq_operations cpuinfo_op; 150 151 static inline int hlt_works(int cpu) 152 { 153 #ifdef CONFIG_X86_32 154 return cpu_data(cpu).hlt_works_ok; 155 #else 156 return 1; 157 #endif 158 } 159 160 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 161 162 extern void cpu_detect(struct cpuinfo_x86 *c); 163 164 extern struct pt_regs *idle_regs(struct pt_regs *); 165 166 extern void early_cpu_init(void); 167 extern void identify_boot_cpu(void); 168 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 169 extern void print_cpu_info(struct cpuinfo_x86 *); 170 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); 171 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); 172 extern unsigned short num_cache_leaves; 173 174 extern void detect_extended_topology(struct cpuinfo_x86 *c); 175 extern void detect_ht(struct cpuinfo_x86 *c); 176 177 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 178 unsigned int *ecx, unsigned int *edx) 179 { 180 /* ecx is often an input as well as an output. */ 181 asm("cpuid" 182 : "=a" (*eax), 183 "=b" (*ebx), 184 "=c" (*ecx), 185 "=d" (*edx) 186 : "0" (*eax), "2" (*ecx)); 187 } 188 189 static inline void load_cr3(pgd_t *pgdir) 190 { 191 write_cr3(__pa(pgdir)); 192 } 193 194 #ifdef CONFIG_X86_32 195 /* This is the TSS defined by the hardware. */ 196 struct x86_hw_tss { 197 unsigned short back_link, __blh; 198 unsigned long sp0; 199 unsigned short ss0, __ss0h; 200 unsigned long sp1; 201 /* ss1 caches MSR_IA32_SYSENTER_CS: */ 202 unsigned short ss1, __ss1h; 203 unsigned long sp2; 204 unsigned short ss2, __ss2h; 205 unsigned long __cr3; 206 unsigned long ip; 207 unsigned long flags; 208 unsigned long ax; 209 unsigned long cx; 210 unsigned long dx; 211 unsigned long bx; 212 unsigned long sp; 213 unsigned long bp; 214 unsigned long si; 215 unsigned long di; 216 unsigned short es, __esh; 217 unsigned short cs, __csh; 218 unsigned short ss, __ssh; 219 unsigned short ds, __dsh; 220 unsigned short fs, __fsh; 221 unsigned short gs, __gsh; 222 unsigned short ldt, __ldth; 223 unsigned short trace; 224 unsigned short io_bitmap_base; 225 226 } __attribute__((packed)); 227 #else 228 struct x86_hw_tss { 229 u32 reserved1; 230 u64 sp0; 231 u64 sp1; 232 u64 sp2; 233 u64 reserved2; 234 u64 ist[7]; 235 u32 reserved3; 236 u32 reserved4; 237 u16 reserved5; 238 u16 io_bitmap_base; 239 240 } __attribute__((packed)) ____cacheline_aligned; 241 #endif 242 243 /* 244 * IO-bitmap sizes: 245 */ 246 #define IO_BITMAP_BITS 65536 247 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) 248 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) 249 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) 250 #define INVALID_IO_BITMAP_OFFSET 0x8000 251 252 struct tss_struct { 253 /* 254 * The hardware state: 255 */ 256 struct x86_hw_tss x86_tss; 257 258 /* 259 * The extra 1 is there because the CPU will access an 260 * additional byte beyond the end of the IO permission 261 * bitmap. The extra byte must be all 1 bits, and must 262 * be within the limit. 263 */ 264 unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; 265 266 /* 267 * .. and then another 0x100 bytes for the emergency kernel stack: 268 */ 269 unsigned long stack[64]; 270 271 } ____cacheline_aligned; 272 273 DECLARE_PER_CPU(struct tss_struct, init_tss); 274 275 /* 276 * Save the original ist values for checking stack pointers during debugging 277 */ 278 struct orig_ist { 279 unsigned long ist[7]; 280 }; 281 282 #define MXCSR_DEFAULT 0x1f80 283 284 struct i387_fsave_struct { 285 u32 cwd; /* FPU Control Word */ 286 u32 swd; /* FPU Status Word */ 287 u32 twd; /* FPU Tag Word */ 288 u32 fip; /* FPU IP Offset */ 289 u32 fcs; /* FPU IP Selector */ 290 u32 foo; /* FPU Operand Pointer Offset */ 291 u32 fos; /* FPU Operand Pointer Selector */ 292 293 /* 8*10 bytes for each FP-reg = 80 bytes: */ 294 u32 st_space[20]; 295 296 /* Software status information [not touched by FSAVE ]: */ 297 u32 status; 298 }; 299 300 struct i387_fxsave_struct { 301 u16 cwd; /* Control Word */ 302 u16 swd; /* Status Word */ 303 u16 twd; /* Tag Word */ 304 u16 fop; /* Last Instruction Opcode */ 305 union { 306 struct { 307 u64 rip; /* Instruction Pointer */ 308 u64 rdp; /* Data Pointer */ 309 }; 310 struct { 311 u32 fip; /* FPU IP Offset */ 312 u32 fcs; /* FPU IP Selector */ 313 u32 foo; /* FPU Operand Offset */ 314 u32 fos; /* FPU Operand Selector */ 315 }; 316 }; 317 u32 mxcsr; /* MXCSR Register State */ 318 u32 mxcsr_mask; /* MXCSR Mask */ 319 320 /* 8*16 bytes for each FP-reg = 128 bytes: */ 321 u32 st_space[32]; 322 323 /* 16*16 bytes for each XMM-reg = 256 bytes: */ 324 u32 xmm_space[64]; 325 326 u32 padding[12]; 327 328 union { 329 u32 padding1[12]; 330 u32 sw_reserved[12]; 331 }; 332 333 } __attribute__((aligned(16))); 334 335 struct i387_soft_struct { 336 u32 cwd; 337 u32 swd; 338 u32 twd; 339 u32 fip; 340 u32 fcs; 341 u32 foo; 342 u32 fos; 343 /* 8*10 bytes for each FP-reg = 80 bytes: */ 344 u32 st_space[20]; 345 u8 ftop; 346 u8 changed; 347 u8 lookahead; 348 u8 no_update; 349 u8 rm; 350 u8 alimit; 351 struct math_emu_info *info; 352 u32 entry_eip; 353 }; 354 355 struct ymmh_struct { 356 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */ 357 u32 ymmh_space[64]; 358 }; 359 360 struct xsave_hdr_struct { 361 u64 xstate_bv; 362 u64 reserved1[2]; 363 u64 reserved2[5]; 364 } __attribute__((packed)); 365 366 struct xsave_struct { 367 struct i387_fxsave_struct i387; 368 struct xsave_hdr_struct xsave_hdr; 369 struct ymmh_struct ymmh; 370 /* new processor state extensions will go here */ 371 } __attribute__ ((packed, aligned (64))); 372 373 union thread_xstate { 374 struct i387_fsave_struct fsave; 375 struct i387_fxsave_struct fxsave; 376 struct i387_soft_struct soft; 377 struct xsave_struct xsave; 378 }; 379 380 #ifdef CONFIG_X86_64 381 DECLARE_PER_CPU(struct orig_ist, orig_ist); 382 383 union irq_stack_union { 384 char irq_stack[IRQ_STACK_SIZE]; 385 /* 386 * GCC hardcodes the stack canary as %gs:40. Since the 387 * irq_stack is the object at %gs:0, we reserve the bottom 388 * 48 bytes of the irq stack for the canary. 389 */ 390 struct { 391 char gs_base[40]; 392 unsigned long stack_canary; 393 }; 394 }; 395 396 DECLARE_PER_CPU(union irq_stack_union, irq_stack_union); 397 DECLARE_INIT_PER_CPU(irq_stack_union); 398 399 DECLARE_PER_CPU(char *, irq_stack_ptr); 400 DECLARE_PER_CPU(unsigned int, irq_count); 401 extern unsigned long kernel_eflags; 402 extern asmlinkage void ignore_sysret(void); 403 #else /* X86_64 */ 404 #ifdef CONFIG_CC_STACKPROTECTOR 405 DECLARE_PER_CPU(unsigned long, stack_canary); 406 #endif 407 #endif /* X86_64 */ 408 409 extern unsigned int xstate_size; 410 extern void free_thread_xstate(struct task_struct *); 411 extern struct kmem_cache *task_xstate_cachep; 412 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); 413 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); 414 extern unsigned short num_cache_leaves; 415 416 struct thread_struct { 417 /* Cached TLS descriptors: */ 418 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 419 unsigned long sp0; 420 unsigned long sp; 421 #ifdef CONFIG_X86_32 422 unsigned long sysenter_cs; 423 #else 424 unsigned long usersp; /* Copy from PDA */ 425 unsigned short es; 426 unsigned short ds; 427 unsigned short fsindex; 428 unsigned short gsindex; 429 #endif 430 unsigned long ip; 431 unsigned long fs; 432 unsigned long gs; 433 /* Hardware debugging registers: */ 434 unsigned long debugreg0; 435 unsigned long debugreg1; 436 unsigned long debugreg2; 437 unsigned long debugreg3; 438 unsigned long debugreg6; 439 unsigned long debugreg7; 440 /* Fault info: */ 441 unsigned long cr2; 442 unsigned long trap_no; 443 unsigned long error_code; 444 /* floating point and extended processor state */ 445 union thread_xstate *xstate; 446 #ifdef CONFIG_X86_32 447 /* Virtual 86 mode info */ 448 struct vm86_struct __user *vm86_info; 449 unsigned long screen_bitmap; 450 unsigned long v86flags; 451 unsigned long v86mask; 452 unsigned long saved_sp0; 453 unsigned int saved_fs; 454 unsigned int saved_gs; 455 #endif 456 /* IO permissions: */ 457 unsigned long *io_bitmap_ptr; 458 unsigned long iopl; 459 /* Max allowed port in the bitmap, in bytes: */ 460 unsigned io_bitmap_max; 461 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */ 462 unsigned long debugctlmsr; 463 #ifdef CONFIG_X86_DS 464 /* Debug Store context; see include/asm-x86/ds.h; goes into MSR_IA32_DS_AREA */ 465 struct ds_context *ds_ctx; 466 #endif /* CONFIG_X86_DS */ 467 #ifdef CONFIG_X86_PTRACE_BTS 468 /* the signal to send on a bts buffer overflow */ 469 unsigned int bts_ovfl_signal; 470 #endif /* CONFIG_X86_PTRACE_BTS */ 471 }; 472 473 static inline unsigned long native_get_debugreg(int regno) 474 { 475 unsigned long val = 0; /* Damn you, gcc! */ 476 477 switch (regno) { 478 case 0: 479 asm("mov %%db0, %0" :"=r" (val)); 480 break; 481 case 1: 482 asm("mov %%db1, %0" :"=r" (val)); 483 break; 484 case 2: 485 asm("mov %%db2, %0" :"=r" (val)); 486 break; 487 case 3: 488 asm("mov %%db3, %0" :"=r" (val)); 489 break; 490 case 6: 491 asm("mov %%db6, %0" :"=r" (val)); 492 break; 493 case 7: 494 asm("mov %%db7, %0" :"=r" (val)); 495 break; 496 default: 497 BUG(); 498 } 499 return val; 500 } 501 502 static inline void native_set_debugreg(int regno, unsigned long value) 503 { 504 switch (regno) { 505 case 0: 506 asm("mov %0, %%db0" ::"r" (value)); 507 break; 508 case 1: 509 asm("mov %0, %%db1" ::"r" (value)); 510 break; 511 case 2: 512 asm("mov %0, %%db2" ::"r" (value)); 513 break; 514 case 3: 515 asm("mov %0, %%db3" ::"r" (value)); 516 break; 517 case 6: 518 asm("mov %0, %%db6" ::"r" (value)); 519 break; 520 case 7: 521 asm("mov %0, %%db7" ::"r" (value)); 522 break; 523 default: 524 BUG(); 525 } 526 } 527 528 /* 529 * Set IOPL bits in EFLAGS from given mask 530 */ 531 static inline void native_set_iopl_mask(unsigned mask) 532 { 533 #ifdef CONFIG_X86_32 534 unsigned int reg; 535 536 asm volatile ("pushfl;" 537 "popl %0;" 538 "andl %1, %0;" 539 "orl %2, %0;" 540 "pushl %0;" 541 "popfl" 542 : "=&r" (reg) 543 : "i" (~X86_EFLAGS_IOPL), "r" (mask)); 544 #endif 545 } 546 547 static inline void 548 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread) 549 { 550 tss->x86_tss.sp0 = thread->sp0; 551 #ifdef CONFIG_X86_32 552 /* Only happens when SEP is enabled, no need to test "SEP"arately: */ 553 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { 554 tss->x86_tss.ss1 = thread->sysenter_cs; 555 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); 556 } 557 #endif 558 } 559 560 static inline void native_swapgs(void) 561 { 562 #ifdef CONFIG_X86_64 563 asm volatile("swapgs" ::: "memory"); 564 #endif 565 } 566 567 #ifdef CONFIG_PARAVIRT 568 #include <asm/paravirt.h> 569 #else 570 #define __cpuid native_cpuid 571 #define paravirt_enabled() 0 572 573 /* 574 * These special macros can be used to get or set a debugging register 575 */ 576 #define get_debugreg(var, register) \ 577 (var) = native_get_debugreg(register) 578 #define set_debugreg(value, register) \ 579 native_set_debugreg(register, value) 580 581 static inline void load_sp0(struct tss_struct *tss, 582 struct thread_struct *thread) 583 { 584 native_load_sp0(tss, thread); 585 } 586 587 #define set_iopl_mask native_set_iopl_mask 588 #endif /* CONFIG_PARAVIRT */ 589 590 /* 591 * Save the cr4 feature set we're using (ie 592 * Pentium 4MB enable and PPro Global page 593 * enable), so that any CPU's that boot up 594 * after us can get the correct flags. 595 */ 596 extern unsigned long mmu_cr4_features; 597 598 static inline void set_in_cr4(unsigned long mask) 599 { 600 unsigned cr4; 601 602 mmu_cr4_features |= mask; 603 cr4 = read_cr4(); 604 cr4 |= mask; 605 write_cr4(cr4); 606 } 607 608 static inline void clear_in_cr4(unsigned long mask) 609 { 610 unsigned cr4; 611 612 mmu_cr4_features &= ~mask; 613 cr4 = read_cr4(); 614 cr4 &= ~mask; 615 write_cr4(cr4); 616 } 617 618 typedef struct { 619 unsigned long seg; 620 } mm_segment_t; 621 622 623 /* 624 * create a kernel thread without removing it from tasklists 625 */ 626 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); 627 628 /* Free all resources held by a thread. */ 629 extern void release_thread(struct task_struct *); 630 631 /* Prepare to copy thread state - unlazy all lazy state */ 632 extern void prepare_to_copy(struct task_struct *tsk); 633 634 unsigned long get_wchan(struct task_struct *p); 635 636 /* 637 * Generic CPUID function 638 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 639 * resulting in stale register contents being returned. 640 */ 641 static inline void cpuid(unsigned int op, 642 unsigned int *eax, unsigned int *ebx, 643 unsigned int *ecx, unsigned int *edx) 644 { 645 *eax = op; 646 *ecx = 0; 647 __cpuid(eax, ebx, ecx, edx); 648 } 649 650 /* Some CPUID calls want 'count' to be placed in ecx */ 651 static inline void cpuid_count(unsigned int op, int count, 652 unsigned int *eax, unsigned int *ebx, 653 unsigned int *ecx, unsigned int *edx) 654 { 655 *eax = op; 656 *ecx = count; 657 __cpuid(eax, ebx, ecx, edx); 658 } 659 660 /* 661 * CPUID functions returning a single datum 662 */ 663 static inline unsigned int cpuid_eax(unsigned int op) 664 { 665 unsigned int eax, ebx, ecx, edx; 666 667 cpuid(op, &eax, &ebx, &ecx, &edx); 668 669 return eax; 670 } 671 672 static inline unsigned int cpuid_ebx(unsigned int op) 673 { 674 unsigned int eax, ebx, ecx, edx; 675 676 cpuid(op, &eax, &ebx, &ecx, &edx); 677 678 return ebx; 679 } 680 681 static inline unsigned int cpuid_ecx(unsigned int op) 682 { 683 unsigned int eax, ebx, ecx, edx; 684 685 cpuid(op, &eax, &ebx, &ecx, &edx); 686 687 return ecx; 688 } 689 690 static inline unsigned int cpuid_edx(unsigned int op) 691 { 692 unsigned int eax, ebx, ecx, edx; 693 694 cpuid(op, &eax, &ebx, &ecx, &edx); 695 696 return edx; 697 } 698 699 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 700 static inline void rep_nop(void) 701 { 702 asm volatile("rep; nop" ::: "memory"); 703 } 704 705 static inline void cpu_relax(void) 706 { 707 rep_nop(); 708 } 709 710 /* Stop speculative execution: */ 711 static inline void sync_core(void) 712 { 713 int tmp; 714 715 asm volatile("cpuid" : "=a" (tmp) : "0" (1) 716 : "ebx", "ecx", "edx", "memory"); 717 } 718 719 static inline void __monitor(const void *eax, unsigned long ecx, 720 unsigned long edx) 721 { 722 /* "monitor %eax, %ecx, %edx;" */ 723 asm volatile(".byte 0x0f, 0x01, 0xc8;" 724 :: "a" (eax), "c" (ecx), "d"(edx)); 725 } 726 727 static inline void __mwait(unsigned long eax, unsigned long ecx) 728 { 729 /* "mwait %eax, %ecx;" */ 730 asm volatile(".byte 0x0f, 0x01, 0xc9;" 731 :: "a" (eax), "c" (ecx)); 732 } 733 734 static inline void __sti_mwait(unsigned long eax, unsigned long ecx) 735 { 736 trace_hardirqs_on(); 737 /* "mwait %eax, %ecx;" */ 738 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;" 739 :: "a" (eax), "c" (ecx)); 740 } 741 742 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx); 743 744 extern void select_idle_routine(const struct cpuinfo_x86 *c); 745 extern void init_c1e_mask(void); 746 747 extern unsigned long boot_option_idle_override; 748 extern unsigned long idle_halt; 749 extern unsigned long idle_nomwait; 750 751 /* 752 * on systems with caches, caches must be flashed as the absolute 753 * last instruction before going into a suspended halt. Otherwise, 754 * dirty data can linger in the cache and become stale on resume, 755 * leading to strange errors. 756 * 757 * perform a variety of operations to guarantee that the compiler 758 * will not reorder instructions. wbinvd itself is serializing 759 * so the processor will not reorder. 760 * 761 * Systems without cache can just go into halt. 762 */ 763 static inline void wbinvd_halt(void) 764 { 765 mb(); 766 /* check for clflush to determine if wbinvd is legal */ 767 if (cpu_has_clflush) 768 asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory"); 769 else 770 while (1) 771 halt(); 772 } 773 774 extern void enable_sep_cpu(void); 775 extern int sysenter_setup(void); 776 777 /* Defined in head.S */ 778 extern struct desc_ptr early_gdt_descr; 779 780 extern void cpu_set_gdt(int); 781 extern void switch_to_new_gdt(int); 782 extern void load_percpu_segment(int); 783 extern void cpu_init(void); 784 785 static inline unsigned long get_debugctlmsr(void) 786 { 787 unsigned long debugctlmsr = 0; 788 789 #ifndef CONFIG_X86_DEBUGCTLMSR 790 if (boot_cpu_data.x86 < 6) 791 return 0; 792 #endif 793 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 794 795 return debugctlmsr; 796 } 797 798 static inline void update_debugctlmsr(unsigned long debugctlmsr) 799 { 800 #ifndef CONFIG_X86_DEBUGCTLMSR 801 if (boot_cpu_data.x86 < 6) 802 return; 803 #endif 804 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 805 } 806 807 /* 808 * from system description table in BIOS. Mostly for MCA use, but 809 * others may find it useful: 810 */ 811 extern unsigned int machine_id; 812 extern unsigned int machine_submodel_id; 813 extern unsigned int BIOS_revision; 814 815 /* Boot loader type from the setup header: */ 816 extern int bootloader_type; 817 818 extern char ignore_fpu_irq; 819 820 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 821 #define ARCH_HAS_PREFETCHW 822 #define ARCH_HAS_SPINLOCK_PREFETCH 823 824 #ifdef CONFIG_X86_32 825 # define BASE_PREFETCH ASM_NOP4 826 # define ARCH_HAS_PREFETCH 827 #else 828 # define BASE_PREFETCH "prefetcht0 (%1)" 829 #endif 830 831 /* 832 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 833 * 834 * It's not worth to care about 3dnow prefetches for the K6 835 * because they are microcoded there and very slow. 836 */ 837 static inline void prefetch(const void *x) 838 { 839 alternative_input(BASE_PREFETCH, 840 "prefetchnta (%1)", 841 X86_FEATURE_XMM, 842 "r" (x)); 843 } 844 845 /* 846 * 3dnow prefetch to get an exclusive cache line. 847 * Useful for spinlocks to avoid one state transition in the 848 * cache coherency protocol: 849 */ 850 static inline void prefetchw(const void *x) 851 { 852 alternative_input(BASE_PREFETCH, 853 "prefetchw (%1)", 854 X86_FEATURE_3DNOW, 855 "r" (x)); 856 } 857 858 static inline void spin_lock_prefetch(const void *x) 859 { 860 prefetchw(x); 861 } 862 863 #ifdef CONFIG_X86_32 864 /* 865 * User space process size: 3GB (default). 866 */ 867 #define TASK_SIZE PAGE_OFFSET 868 #define TASK_SIZE_MAX TASK_SIZE 869 #define STACK_TOP TASK_SIZE 870 #define STACK_TOP_MAX STACK_TOP 871 872 #define INIT_THREAD { \ 873 .sp0 = sizeof(init_stack) + (long)&init_stack, \ 874 .vm86_info = NULL, \ 875 .sysenter_cs = __KERNEL_CS, \ 876 .io_bitmap_ptr = NULL, \ 877 .fs = __KERNEL_PERCPU, \ 878 } 879 880 /* 881 * Note that the .io_bitmap member must be extra-big. This is because 882 * the CPU will access an additional byte beyond the end of the IO 883 * permission bitmap. The extra byte must be all 1 bits, and must 884 * be within the limit. 885 */ 886 #define INIT_TSS { \ 887 .x86_tss = { \ 888 .sp0 = sizeof(init_stack) + (long)&init_stack, \ 889 .ss0 = __KERNEL_DS, \ 890 .ss1 = __KERNEL_CS, \ 891 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \ 892 }, \ 893 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \ 894 } 895 896 extern unsigned long thread_saved_pc(struct task_struct *tsk); 897 898 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long)) 899 #define KSTK_TOP(info) \ 900 ({ \ 901 unsigned long *__ptr = (unsigned long *)(info); \ 902 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \ 903 }) 904 905 /* 906 * The below -8 is to reserve 8 bytes on top of the ring0 stack. 907 * This is necessary to guarantee that the entire "struct pt_regs" 908 * is accessable even if the CPU haven't stored the SS/ESP registers 909 * on the stack (interrupt gate does not save these registers 910 * when switching to the same priv ring). 911 * Therefore beware: accessing the ss/esp fields of the 912 * "struct pt_regs" is possible, but they may contain the 913 * completely wrong values. 914 */ 915 #define task_pt_regs(task) \ 916 ({ \ 917 struct pt_regs *__regs__; \ 918 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \ 919 __regs__ - 1; \ 920 }) 921 922 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 923 924 #else 925 /* 926 * User space process size. 47bits minus one guard page. 927 */ 928 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE) 929 930 /* This decides where the kernel will search for a free chunk of vm 931 * space during mmap's. 932 */ 933 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ 934 0xc0000000 : 0xFFFFe000) 935 936 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \ 937 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 938 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \ 939 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 940 941 #define STACK_TOP TASK_SIZE 942 #define STACK_TOP_MAX TASK_SIZE_MAX 943 944 #define INIT_THREAD { \ 945 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ 946 } 947 948 #define INIT_TSS { \ 949 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ 950 } 951 952 /* 953 * Return saved PC of a blocked thread. 954 * What is this good for? it will be always the scheduler or ret_from_fork. 955 */ 956 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8)) 957 958 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) 959 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */ 960 #endif /* CONFIG_X86_64 */ 961 962 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 963 unsigned long new_sp); 964 965 /* 966 * This decides where the kernel will search for a free chunk of vm 967 * space during mmap's. 968 */ 969 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) 970 971 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 972 973 /* Get/set a process' ability to use the timestamp counter instruction */ 974 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 975 #define SET_TSC_CTL(val) set_tsc_mode((val)) 976 977 extern int get_tsc_mode(unsigned long adr); 978 extern int set_tsc_mode(unsigned int val); 979 980 #endif /* _ASM_X86_PROCESSOR_H */ 981