1 #ifndef _ASM_X86_PROCESSOR_H 2 #define _ASM_X86_PROCESSOR_H 3 4 #include <asm/processor-flags.h> 5 6 /* Forward declaration, a strange C thing */ 7 struct task_struct; 8 struct mm_struct; 9 10 #include <asm/vm86.h> 11 #include <asm/math_emu.h> 12 #include <asm/segment.h> 13 #include <asm/types.h> 14 #include <asm/sigcontext.h> 15 #include <asm/current.h> 16 #include <asm/cpufeature.h> 17 #include <asm/page.h> 18 #include <asm/pgtable_types.h> 19 #include <asm/percpu.h> 20 #include <asm/msr.h> 21 #include <asm/desc_defs.h> 22 #include <asm/nops.h> 23 #include <asm/special_insns.h> 24 25 #include <linux/personality.h> 26 #include <linux/cpumask.h> 27 #include <linux/cache.h> 28 #include <linux/threads.h> 29 #include <linux/math64.h> 30 #include <linux/init.h> 31 #include <linux/err.h> 32 #include <linux/irqflags.h> 33 34 /* 35 * We handle most unaligned accesses in hardware. On the other hand 36 * unaligned DMA can be quite expensive on some Nehalem processors. 37 * 38 * Based on this we disable the IP header alignment in network drivers. 39 */ 40 #define NET_IP_ALIGN 0 41 42 #define HBP_NUM 4 43 /* 44 * Default implementation of macro that returns current 45 * instruction pointer ("program counter"). 46 */ 47 static inline void *current_text_addr(void) 48 { 49 void *pc; 50 51 asm volatile("mov $1f, %0; 1:":"=r" (pc)); 52 53 return pc; 54 } 55 56 #ifdef CONFIG_X86_VSMP 57 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 58 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 59 #else 60 # define ARCH_MIN_TASKALIGN 16 61 # define ARCH_MIN_MMSTRUCT_ALIGN 0 62 #endif 63 64 enum tlb_infos { 65 ENTRIES, 66 NR_INFO 67 }; 68 69 extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 70 extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 71 extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 72 extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 73 extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 74 extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 75 extern s8 __read_mostly tlb_flushall_shift; 76 77 /* 78 * CPU type and hardware bug flags. Kept separately for each CPU. 79 * Members of this structure are referenced in head.S, so think twice 80 * before touching them. [mj] 81 */ 82 83 struct cpuinfo_x86 { 84 __u8 x86; /* CPU family */ 85 __u8 x86_vendor; /* CPU vendor */ 86 __u8 x86_model; 87 __u8 x86_mask; 88 #ifdef CONFIG_X86_32 89 char wp_works_ok; /* It doesn't on 386's */ 90 91 /* Problems on some 486Dx4's and old 386's: */ 92 char hard_math; 93 char rfu; 94 char fdiv_bug; 95 char f00f_bug; 96 char coma_bug; 97 char pad0; 98 #else 99 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 100 int x86_tlbsize; 101 #endif 102 __u8 x86_virt_bits; 103 __u8 x86_phys_bits; 104 /* CPUID returned core id bits: */ 105 __u8 x86_coreid_bits; 106 /* Max extended CPUID function supported: */ 107 __u32 extended_cpuid_level; 108 /* Maximum supported CPUID level, -1=no CPUID: */ 109 int cpuid_level; 110 __u32 x86_capability[NCAPINTS]; 111 char x86_vendor_id[16]; 112 char x86_model_id[64]; 113 /* in KB - valid for CPUS which support this call: */ 114 int x86_cache_size; 115 int x86_cache_alignment; /* In bytes */ 116 int x86_power; 117 unsigned long loops_per_jiffy; 118 /* cpuid returned max cores value: */ 119 u16 x86_max_cores; 120 u16 apicid; 121 u16 initial_apicid; 122 u16 x86_clflush_size; 123 /* number of cores as seen by the OS: */ 124 u16 booted_cores; 125 /* Physical processor id: */ 126 u16 phys_proc_id; 127 /* Core id: */ 128 u16 cpu_core_id; 129 /* Compute unit id */ 130 u8 compute_unit_id; 131 /* Index into per_cpu list: */ 132 u16 cpu_index; 133 u32 microcode; 134 } __attribute__((__aligned__(SMP_CACHE_BYTES))); 135 136 #define X86_VENDOR_INTEL 0 137 #define X86_VENDOR_CYRIX 1 138 #define X86_VENDOR_AMD 2 139 #define X86_VENDOR_UMC 3 140 #define X86_VENDOR_CENTAUR 5 141 #define X86_VENDOR_TRANSMETA 7 142 #define X86_VENDOR_NSC 8 143 #define X86_VENDOR_NUM 9 144 145 #define X86_VENDOR_UNKNOWN 0xff 146 147 /* 148 * capabilities of CPUs 149 */ 150 extern struct cpuinfo_x86 boot_cpu_data; 151 extern struct cpuinfo_x86 new_cpu_data; 152 153 extern struct tss_struct doublefault_tss; 154 extern __u32 cpu_caps_cleared[NCAPINTS]; 155 extern __u32 cpu_caps_set[NCAPINTS]; 156 157 #ifdef CONFIG_SMP 158 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 159 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 160 #else 161 #define cpu_info boot_cpu_data 162 #define cpu_data(cpu) boot_cpu_data 163 #endif 164 165 extern const struct seq_operations cpuinfo_op; 166 167 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 168 169 extern void cpu_detect(struct cpuinfo_x86 *c); 170 171 extern void early_cpu_init(void); 172 extern void identify_boot_cpu(void); 173 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 174 extern void print_cpu_info(struct cpuinfo_x86 *); 175 void print_cpu_msr(struct cpuinfo_x86 *); 176 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); 177 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); 178 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); 179 180 extern void detect_extended_topology(struct cpuinfo_x86 *c); 181 extern void detect_ht(struct cpuinfo_x86 *c); 182 183 #ifdef CONFIG_X86_32 184 extern int have_cpuid_p(void); 185 #else 186 static inline int have_cpuid_p(void) 187 { 188 return 1; 189 } 190 #endif 191 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 192 unsigned int *ecx, unsigned int *edx) 193 { 194 /* ecx is often an input as well as an output. */ 195 asm volatile("cpuid" 196 : "=a" (*eax), 197 "=b" (*ebx), 198 "=c" (*ecx), 199 "=d" (*edx) 200 : "0" (*eax), "2" (*ecx) 201 : "memory"); 202 } 203 204 static inline void load_cr3(pgd_t *pgdir) 205 { 206 write_cr3(__pa(pgdir)); 207 } 208 209 #ifdef CONFIG_X86_32 210 /* This is the TSS defined by the hardware. */ 211 struct x86_hw_tss { 212 unsigned short back_link, __blh; 213 unsigned long sp0; 214 unsigned short ss0, __ss0h; 215 unsigned long sp1; 216 /* ss1 caches MSR_IA32_SYSENTER_CS: */ 217 unsigned short ss1, __ss1h; 218 unsigned long sp2; 219 unsigned short ss2, __ss2h; 220 unsigned long __cr3; 221 unsigned long ip; 222 unsigned long flags; 223 unsigned long ax; 224 unsigned long cx; 225 unsigned long dx; 226 unsigned long bx; 227 unsigned long sp; 228 unsigned long bp; 229 unsigned long si; 230 unsigned long di; 231 unsigned short es, __esh; 232 unsigned short cs, __csh; 233 unsigned short ss, __ssh; 234 unsigned short ds, __dsh; 235 unsigned short fs, __fsh; 236 unsigned short gs, __gsh; 237 unsigned short ldt, __ldth; 238 unsigned short trace; 239 unsigned short io_bitmap_base; 240 241 } __attribute__((packed)); 242 #else 243 struct x86_hw_tss { 244 u32 reserved1; 245 u64 sp0; 246 u64 sp1; 247 u64 sp2; 248 u64 reserved2; 249 u64 ist[7]; 250 u32 reserved3; 251 u32 reserved4; 252 u16 reserved5; 253 u16 io_bitmap_base; 254 255 } __attribute__((packed)) ____cacheline_aligned; 256 #endif 257 258 /* 259 * IO-bitmap sizes: 260 */ 261 #define IO_BITMAP_BITS 65536 262 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) 263 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) 264 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) 265 #define INVALID_IO_BITMAP_OFFSET 0x8000 266 267 struct tss_struct { 268 /* 269 * The hardware state: 270 */ 271 struct x86_hw_tss x86_tss; 272 273 /* 274 * The extra 1 is there because the CPU will access an 275 * additional byte beyond the end of the IO permission 276 * bitmap. The extra byte must be all 1 bits, and must 277 * be within the limit. 278 */ 279 unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; 280 281 /* 282 * .. and then another 0x100 bytes for the emergency kernel stack: 283 */ 284 unsigned long stack[64]; 285 286 } ____cacheline_aligned; 287 288 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss); 289 290 /* 291 * Save the original ist values for checking stack pointers during debugging 292 */ 293 struct orig_ist { 294 unsigned long ist[7]; 295 }; 296 297 #define MXCSR_DEFAULT 0x1f80 298 299 struct i387_fsave_struct { 300 u32 cwd; /* FPU Control Word */ 301 u32 swd; /* FPU Status Word */ 302 u32 twd; /* FPU Tag Word */ 303 u32 fip; /* FPU IP Offset */ 304 u32 fcs; /* FPU IP Selector */ 305 u32 foo; /* FPU Operand Pointer Offset */ 306 u32 fos; /* FPU Operand Pointer Selector */ 307 308 /* 8*10 bytes for each FP-reg = 80 bytes: */ 309 u32 st_space[20]; 310 311 /* Software status information [not touched by FSAVE ]: */ 312 u32 status; 313 }; 314 315 struct i387_fxsave_struct { 316 u16 cwd; /* Control Word */ 317 u16 swd; /* Status Word */ 318 u16 twd; /* Tag Word */ 319 u16 fop; /* Last Instruction Opcode */ 320 union { 321 struct { 322 u64 rip; /* Instruction Pointer */ 323 u64 rdp; /* Data Pointer */ 324 }; 325 struct { 326 u32 fip; /* FPU IP Offset */ 327 u32 fcs; /* FPU IP Selector */ 328 u32 foo; /* FPU Operand Offset */ 329 u32 fos; /* FPU Operand Selector */ 330 }; 331 }; 332 u32 mxcsr; /* MXCSR Register State */ 333 u32 mxcsr_mask; /* MXCSR Mask */ 334 335 /* 8*16 bytes for each FP-reg = 128 bytes: */ 336 u32 st_space[32]; 337 338 /* 16*16 bytes for each XMM-reg = 256 bytes: */ 339 u32 xmm_space[64]; 340 341 u32 padding[12]; 342 343 union { 344 u32 padding1[12]; 345 u32 sw_reserved[12]; 346 }; 347 348 } __attribute__((aligned(16))); 349 350 struct i387_soft_struct { 351 u32 cwd; 352 u32 swd; 353 u32 twd; 354 u32 fip; 355 u32 fcs; 356 u32 foo; 357 u32 fos; 358 /* 8*10 bytes for each FP-reg = 80 bytes: */ 359 u32 st_space[20]; 360 u8 ftop; 361 u8 changed; 362 u8 lookahead; 363 u8 no_update; 364 u8 rm; 365 u8 alimit; 366 struct math_emu_info *info; 367 u32 entry_eip; 368 }; 369 370 struct ymmh_struct { 371 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */ 372 u32 ymmh_space[64]; 373 }; 374 375 struct xsave_hdr_struct { 376 u64 xstate_bv; 377 u64 reserved1[2]; 378 u64 reserved2[5]; 379 } __attribute__((packed)); 380 381 struct xsave_struct { 382 struct i387_fxsave_struct i387; 383 struct xsave_hdr_struct xsave_hdr; 384 struct ymmh_struct ymmh; 385 /* new processor state extensions will go here */ 386 } __attribute__ ((packed, aligned (64))); 387 388 union thread_xstate { 389 struct i387_fsave_struct fsave; 390 struct i387_fxsave_struct fxsave; 391 struct i387_soft_struct soft; 392 struct xsave_struct xsave; 393 }; 394 395 struct fpu { 396 unsigned int last_cpu; 397 unsigned int has_fpu; 398 union thread_xstate *state; 399 }; 400 401 #ifdef CONFIG_X86_64 402 DECLARE_PER_CPU(struct orig_ist, orig_ist); 403 404 union irq_stack_union { 405 char irq_stack[IRQ_STACK_SIZE]; 406 /* 407 * GCC hardcodes the stack canary as %gs:40. Since the 408 * irq_stack is the object at %gs:0, we reserve the bottom 409 * 48 bytes of the irq stack for the canary. 410 */ 411 struct { 412 char gs_base[40]; 413 unsigned long stack_canary; 414 }; 415 }; 416 417 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union); 418 DECLARE_INIT_PER_CPU(irq_stack_union); 419 420 DECLARE_PER_CPU(char *, irq_stack_ptr); 421 DECLARE_PER_CPU(unsigned int, irq_count); 422 extern asmlinkage void ignore_sysret(void); 423 #else /* X86_64 */ 424 #ifdef CONFIG_CC_STACKPROTECTOR 425 /* 426 * Make sure stack canary segment base is cached-aligned: 427 * "For Intel Atom processors, avoid non zero segment base address 428 * that is not aligned to cache line boundary at all cost." 429 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) 430 */ 431 struct stack_canary { 432 char __pad[20]; /* canary at %gs:20 */ 433 unsigned long canary; 434 }; 435 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 436 #endif 437 #endif /* X86_64 */ 438 439 extern unsigned int xstate_size; 440 extern void free_thread_xstate(struct task_struct *); 441 extern struct kmem_cache *task_xstate_cachep; 442 443 struct perf_event; 444 445 struct thread_struct { 446 /* Cached TLS descriptors: */ 447 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 448 unsigned long sp0; 449 unsigned long sp; 450 #ifdef CONFIG_X86_32 451 unsigned long sysenter_cs; 452 #else 453 unsigned long usersp; /* Copy from PDA */ 454 unsigned short es; 455 unsigned short ds; 456 unsigned short fsindex; 457 unsigned short gsindex; 458 #endif 459 #ifdef CONFIG_X86_32 460 unsigned long ip; 461 #endif 462 #ifdef CONFIG_X86_64 463 unsigned long fs; 464 #endif 465 unsigned long gs; 466 /* Save middle states of ptrace breakpoints */ 467 struct perf_event *ptrace_bps[HBP_NUM]; 468 /* Debug status used for traps, single steps, etc... */ 469 unsigned long debugreg6; 470 /* Keep track of the exact dr7 value set by the user */ 471 unsigned long ptrace_dr7; 472 /* Fault info: */ 473 unsigned long cr2; 474 unsigned long trap_nr; 475 unsigned long error_code; 476 /* floating point and extended processor state */ 477 struct fpu fpu; 478 #ifdef CONFIG_X86_32 479 /* Virtual 86 mode info */ 480 struct vm86_struct __user *vm86_info; 481 unsigned long screen_bitmap; 482 unsigned long v86flags; 483 unsigned long v86mask; 484 unsigned long saved_sp0; 485 unsigned int saved_fs; 486 unsigned int saved_gs; 487 #endif 488 /* IO permissions: */ 489 unsigned long *io_bitmap_ptr; 490 unsigned long iopl; 491 /* Max allowed port in the bitmap, in bytes: */ 492 unsigned io_bitmap_max; 493 }; 494 495 /* 496 * Set IOPL bits in EFLAGS from given mask 497 */ 498 static inline void native_set_iopl_mask(unsigned mask) 499 { 500 #ifdef CONFIG_X86_32 501 unsigned int reg; 502 503 asm volatile ("pushfl;" 504 "popl %0;" 505 "andl %1, %0;" 506 "orl %2, %0;" 507 "pushl %0;" 508 "popfl" 509 : "=&r" (reg) 510 : "i" (~X86_EFLAGS_IOPL), "r" (mask)); 511 #endif 512 } 513 514 static inline void 515 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread) 516 { 517 tss->x86_tss.sp0 = thread->sp0; 518 #ifdef CONFIG_X86_32 519 /* Only happens when SEP is enabled, no need to test "SEP"arately: */ 520 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { 521 tss->x86_tss.ss1 = thread->sysenter_cs; 522 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); 523 } 524 #endif 525 } 526 527 static inline void native_swapgs(void) 528 { 529 #ifdef CONFIG_X86_64 530 asm volatile("swapgs" ::: "memory"); 531 #endif 532 } 533 534 #ifdef CONFIG_PARAVIRT 535 #include <asm/paravirt.h> 536 #else 537 #define __cpuid native_cpuid 538 #define paravirt_enabled() 0 539 540 static inline void load_sp0(struct tss_struct *tss, 541 struct thread_struct *thread) 542 { 543 native_load_sp0(tss, thread); 544 } 545 546 #define set_iopl_mask native_set_iopl_mask 547 #endif /* CONFIG_PARAVIRT */ 548 549 /* 550 * Save the cr4 feature set we're using (ie 551 * Pentium 4MB enable and PPro Global page 552 * enable), so that any CPU's that boot up 553 * after us can get the correct flags. 554 */ 555 extern unsigned long mmu_cr4_features; 556 extern u32 *trampoline_cr4_features; 557 558 static inline void set_in_cr4(unsigned long mask) 559 { 560 unsigned long cr4; 561 562 mmu_cr4_features |= mask; 563 if (trampoline_cr4_features) 564 *trampoline_cr4_features = mmu_cr4_features; 565 cr4 = read_cr4(); 566 cr4 |= mask; 567 write_cr4(cr4); 568 } 569 570 static inline void clear_in_cr4(unsigned long mask) 571 { 572 unsigned long cr4; 573 574 mmu_cr4_features &= ~mask; 575 if (trampoline_cr4_features) 576 *trampoline_cr4_features = mmu_cr4_features; 577 cr4 = read_cr4(); 578 cr4 &= ~mask; 579 write_cr4(cr4); 580 } 581 582 typedef struct { 583 unsigned long seg; 584 } mm_segment_t; 585 586 587 /* Free all resources held by a thread. */ 588 extern void release_thread(struct task_struct *); 589 590 unsigned long get_wchan(struct task_struct *p); 591 592 /* 593 * Generic CPUID function 594 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 595 * resulting in stale register contents being returned. 596 */ 597 static inline void cpuid(unsigned int op, 598 unsigned int *eax, unsigned int *ebx, 599 unsigned int *ecx, unsigned int *edx) 600 { 601 *eax = op; 602 *ecx = 0; 603 __cpuid(eax, ebx, ecx, edx); 604 } 605 606 /* Some CPUID calls want 'count' to be placed in ecx */ 607 static inline void cpuid_count(unsigned int op, int count, 608 unsigned int *eax, unsigned int *ebx, 609 unsigned int *ecx, unsigned int *edx) 610 { 611 *eax = op; 612 *ecx = count; 613 __cpuid(eax, ebx, ecx, edx); 614 } 615 616 /* 617 * CPUID functions returning a single datum 618 */ 619 static inline unsigned int cpuid_eax(unsigned int op) 620 { 621 unsigned int eax, ebx, ecx, edx; 622 623 cpuid(op, &eax, &ebx, &ecx, &edx); 624 625 return eax; 626 } 627 628 static inline unsigned int cpuid_ebx(unsigned int op) 629 { 630 unsigned int eax, ebx, ecx, edx; 631 632 cpuid(op, &eax, &ebx, &ecx, &edx); 633 634 return ebx; 635 } 636 637 static inline unsigned int cpuid_ecx(unsigned int op) 638 { 639 unsigned int eax, ebx, ecx, edx; 640 641 cpuid(op, &eax, &ebx, &ecx, &edx); 642 643 return ecx; 644 } 645 646 static inline unsigned int cpuid_edx(unsigned int op) 647 { 648 unsigned int eax, ebx, ecx, edx; 649 650 cpuid(op, &eax, &ebx, &ecx, &edx); 651 652 return edx; 653 } 654 655 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 656 static inline void rep_nop(void) 657 { 658 asm volatile("rep; nop" ::: "memory"); 659 } 660 661 static inline void cpu_relax(void) 662 { 663 rep_nop(); 664 } 665 666 /* Stop speculative execution and prefetching of modified code. */ 667 static inline void sync_core(void) 668 { 669 int tmp; 670 671 #ifdef CONFIG_M486 672 /* 673 * Do a CPUID if available, otherwise do a jump. The jump 674 * can conveniently enough be the jump around CPUID. 675 */ 676 asm volatile("cmpl %2,%1\n\t" 677 "jl 1f\n\t" 678 "cpuid\n" 679 "1:" 680 : "=a" (tmp) 681 : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1) 682 : "ebx", "ecx", "edx", "memory"); 683 #else 684 /* 685 * CPUID is a barrier to speculative execution. 686 * Prefetched instructions are automatically 687 * invalidated when modified. 688 */ 689 asm volatile("cpuid" 690 : "=a" (tmp) 691 : "0" (1) 692 : "ebx", "ecx", "edx", "memory"); 693 #endif 694 } 695 696 static inline void __monitor(const void *eax, unsigned long ecx, 697 unsigned long edx) 698 { 699 /* "monitor %eax, %ecx, %edx;" */ 700 asm volatile(".byte 0x0f, 0x01, 0xc8;" 701 :: "a" (eax), "c" (ecx), "d"(edx)); 702 } 703 704 static inline void __mwait(unsigned long eax, unsigned long ecx) 705 { 706 /* "mwait %eax, %ecx;" */ 707 asm volatile(".byte 0x0f, 0x01, 0xc9;" 708 :: "a" (eax), "c" (ecx)); 709 } 710 711 static inline void __sti_mwait(unsigned long eax, unsigned long ecx) 712 { 713 trace_hardirqs_on(); 714 /* "mwait %eax, %ecx;" */ 715 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;" 716 :: "a" (eax), "c" (ecx)); 717 } 718 719 extern void select_idle_routine(const struct cpuinfo_x86 *c); 720 extern void init_amd_e400_c1e_mask(void); 721 722 extern unsigned long boot_option_idle_override; 723 extern bool amd_e400_c1e_detected; 724 725 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 726 IDLE_POLL}; 727 728 extern void enable_sep_cpu(void); 729 extern int sysenter_setup(void); 730 731 extern void early_trap_init(void); 732 void early_trap_pf_init(void); 733 734 /* Defined in head.S */ 735 extern struct desc_ptr early_gdt_descr; 736 737 extern void cpu_set_gdt(int); 738 extern void switch_to_new_gdt(int); 739 extern void load_percpu_segment(int); 740 extern void cpu_init(void); 741 742 static inline unsigned long get_debugctlmsr(void) 743 { 744 unsigned long debugctlmsr = 0; 745 746 #ifndef CONFIG_X86_DEBUGCTLMSR 747 if (boot_cpu_data.x86 < 6) 748 return 0; 749 #endif 750 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 751 752 return debugctlmsr; 753 } 754 755 static inline void update_debugctlmsr(unsigned long debugctlmsr) 756 { 757 #ifndef CONFIG_X86_DEBUGCTLMSR 758 if (boot_cpu_data.x86 < 6) 759 return; 760 #endif 761 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 762 } 763 764 extern void set_task_blockstep(struct task_struct *task, bool on); 765 766 /* 767 * from system description table in BIOS. Mostly for MCA use, but 768 * others may find it useful: 769 */ 770 extern unsigned int machine_id; 771 extern unsigned int machine_submodel_id; 772 extern unsigned int BIOS_revision; 773 774 /* Boot loader type from the setup header: */ 775 extern int bootloader_type; 776 extern int bootloader_version; 777 778 extern char ignore_fpu_irq; 779 780 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 781 #define ARCH_HAS_PREFETCHW 782 #define ARCH_HAS_SPINLOCK_PREFETCH 783 784 #ifdef CONFIG_X86_32 785 # define BASE_PREFETCH ASM_NOP4 786 # define ARCH_HAS_PREFETCH 787 #else 788 # define BASE_PREFETCH "prefetcht0 (%1)" 789 #endif 790 791 /* 792 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 793 * 794 * It's not worth to care about 3dnow prefetches for the K6 795 * because they are microcoded there and very slow. 796 */ 797 static inline void prefetch(const void *x) 798 { 799 alternative_input(BASE_PREFETCH, 800 "prefetchnta (%1)", 801 X86_FEATURE_XMM, 802 "r" (x)); 803 } 804 805 /* 806 * 3dnow prefetch to get an exclusive cache line. 807 * Useful for spinlocks to avoid one state transition in the 808 * cache coherency protocol: 809 */ 810 static inline void prefetchw(const void *x) 811 { 812 alternative_input(BASE_PREFETCH, 813 "prefetchw (%1)", 814 X86_FEATURE_3DNOW, 815 "r" (x)); 816 } 817 818 static inline void spin_lock_prefetch(const void *x) 819 { 820 prefetchw(x); 821 } 822 823 #ifdef CONFIG_X86_32 824 /* 825 * User space process size: 3GB (default). 826 */ 827 #define TASK_SIZE PAGE_OFFSET 828 #define TASK_SIZE_MAX TASK_SIZE 829 #define STACK_TOP TASK_SIZE 830 #define STACK_TOP_MAX STACK_TOP 831 832 #define INIT_THREAD { \ 833 .sp0 = sizeof(init_stack) + (long)&init_stack, \ 834 .vm86_info = NULL, \ 835 .sysenter_cs = __KERNEL_CS, \ 836 .io_bitmap_ptr = NULL, \ 837 } 838 839 /* 840 * Note that the .io_bitmap member must be extra-big. This is because 841 * the CPU will access an additional byte beyond the end of the IO 842 * permission bitmap. The extra byte must be all 1 bits, and must 843 * be within the limit. 844 */ 845 #define INIT_TSS { \ 846 .x86_tss = { \ 847 .sp0 = sizeof(init_stack) + (long)&init_stack, \ 848 .ss0 = __KERNEL_DS, \ 849 .ss1 = __KERNEL_CS, \ 850 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \ 851 }, \ 852 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \ 853 } 854 855 extern unsigned long thread_saved_pc(struct task_struct *tsk); 856 857 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long)) 858 #define KSTK_TOP(info) \ 859 ({ \ 860 unsigned long *__ptr = (unsigned long *)(info); \ 861 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \ 862 }) 863 864 /* 865 * The below -8 is to reserve 8 bytes on top of the ring0 stack. 866 * This is necessary to guarantee that the entire "struct pt_regs" 867 * is accessible even if the CPU haven't stored the SS/ESP registers 868 * on the stack (interrupt gate does not save these registers 869 * when switching to the same priv ring). 870 * Therefore beware: accessing the ss/esp fields of the 871 * "struct pt_regs" is possible, but they may contain the 872 * completely wrong values. 873 */ 874 #define task_pt_regs(task) \ 875 ({ \ 876 struct pt_regs *__regs__; \ 877 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \ 878 __regs__ - 1; \ 879 }) 880 881 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 882 883 #else 884 /* 885 * User space process size. 47bits minus one guard page. 886 */ 887 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE) 888 889 /* This decides where the kernel will search for a free chunk of vm 890 * space during mmap's. 891 */ 892 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ 893 0xc0000000 : 0xFFFFe000) 894 895 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ 896 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 897 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ 898 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 899 900 #define STACK_TOP TASK_SIZE 901 #define STACK_TOP_MAX TASK_SIZE_MAX 902 903 #define INIT_THREAD { \ 904 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ 905 } 906 907 #define INIT_TSS { \ 908 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ 909 } 910 911 /* 912 * Return saved PC of a blocked thread. 913 * What is this good for? it will be always the scheduler or ret_from_fork. 914 */ 915 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8)) 916 917 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) 918 extern unsigned long KSTK_ESP(struct task_struct *task); 919 920 /* 921 * User space RSP while inside the SYSCALL fast path 922 */ 923 DECLARE_PER_CPU(unsigned long, old_rsp); 924 925 #endif /* CONFIG_X86_64 */ 926 927 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 928 unsigned long new_sp); 929 930 /* 931 * This decides where the kernel will search for a free chunk of vm 932 * space during mmap's. 933 */ 934 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) 935 936 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 937 938 /* Get/set a process' ability to use the timestamp counter instruction */ 939 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 940 #define SET_TSC_CTL(val) set_tsc_mode((val)) 941 942 extern int get_tsc_mode(unsigned long adr); 943 extern int set_tsc_mode(unsigned int val); 944 945 extern u16 amd_get_nb_id(int cpu); 946 947 struct aperfmperf { 948 u64 aperf, mperf; 949 }; 950 951 static inline void get_aperfmperf(struct aperfmperf *am) 952 { 953 WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF)); 954 955 rdmsrl(MSR_IA32_APERF, am->aperf); 956 rdmsrl(MSR_IA32_MPERF, am->mperf); 957 } 958 959 #define APERFMPERF_SHIFT 10 960 961 static inline 962 unsigned long calc_aperfmperf_ratio(struct aperfmperf *old, 963 struct aperfmperf *new) 964 { 965 u64 aperf = new->aperf - old->aperf; 966 u64 mperf = new->mperf - old->mperf; 967 unsigned long ratio = aperf; 968 969 mperf >>= APERFMPERF_SHIFT; 970 if (mperf) 971 ratio = div64_u64(aperf, mperf); 972 973 return ratio; 974 } 975 976 /* 977 * AMD errata checking 978 */ 979 #ifdef CONFIG_CPU_SUP_AMD 980 extern const int amd_erratum_383[]; 981 extern const int amd_erratum_400[]; 982 extern bool cpu_has_amd_erratum(const int *); 983 984 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } 985 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } 986 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ 987 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) 988 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) 989 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) 990 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) 991 992 #else 993 #define cpu_has_amd_erratum(x) (false) 994 #endif /* CONFIG_CPU_SUP_AMD */ 995 996 extern unsigned long arch_align_stack(unsigned long sp); 997 extern void free_init_pages(char *what, unsigned long begin, unsigned long end); 998 999 void default_idle(void); 1000 #ifdef CONFIG_XEN 1001 bool xen_set_default_idle(void); 1002 #else 1003 #define xen_set_default_idle 0 1004 #endif 1005 1006 void stop_this_cpu(void *dummy); 1007 1008 #endif /* _ASM_X86_PROCESSOR_H */ 1009