1 #ifndef _ASM_X86_PROCESSOR_H 2 #define _ASM_X86_PROCESSOR_H 3 4 #include <asm/processor-flags.h> 5 6 /* Forward declaration, a strange C thing */ 7 struct task_struct; 8 struct mm_struct; 9 10 #include <asm/vm86.h> 11 #include <asm/math_emu.h> 12 #include <asm/segment.h> 13 #include <asm/types.h> 14 #include <asm/sigcontext.h> 15 #include <asm/current.h> 16 #include <asm/cpufeature.h> 17 #include <asm/system.h> 18 #include <asm/page.h> 19 #include <asm/pgtable_types.h> 20 #include <asm/percpu.h> 21 #include <asm/msr.h> 22 #include <asm/desc_defs.h> 23 #include <asm/nops.h> 24 #include <asm/ds.h> 25 26 #include <linux/personality.h> 27 #include <linux/cpumask.h> 28 #include <linux/cache.h> 29 #include <linux/threads.h> 30 #include <linux/init.h> 31 32 /* 33 * Default implementation of macro that returns current 34 * instruction pointer ("program counter"). 35 */ 36 static inline void *current_text_addr(void) 37 { 38 void *pc; 39 40 asm volatile("mov $1f, %0; 1:":"=r" (pc)); 41 42 return pc; 43 } 44 45 #ifdef CONFIG_X86_VSMP 46 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 47 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 48 #else 49 # define ARCH_MIN_TASKALIGN 16 50 # define ARCH_MIN_MMSTRUCT_ALIGN 0 51 #endif 52 53 /* 54 * CPU type and hardware bug flags. Kept separately for each CPU. 55 * Members of this structure are referenced in head.S, so think twice 56 * before touching them. [mj] 57 */ 58 59 struct cpuinfo_x86 { 60 __u8 x86; /* CPU family */ 61 __u8 x86_vendor; /* CPU vendor */ 62 __u8 x86_model; 63 __u8 x86_mask; 64 #ifdef CONFIG_X86_32 65 char wp_works_ok; /* It doesn't on 386's */ 66 67 /* Problems on some 486Dx4's and old 386's: */ 68 char hlt_works_ok; 69 char hard_math; 70 char rfu; 71 char fdiv_bug; 72 char f00f_bug; 73 char coma_bug; 74 char pad0; 75 #else 76 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 77 int x86_tlbsize; 78 #endif 79 __u8 x86_virt_bits; 80 __u8 x86_phys_bits; 81 /* CPUID returned core id bits: */ 82 __u8 x86_coreid_bits; 83 /* Max extended CPUID function supported: */ 84 __u32 extended_cpuid_level; 85 /* Maximum supported CPUID level, -1=no CPUID: */ 86 int cpuid_level; 87 __u32 x86_capability[NCAPINTS]; 88 char x86_vendor_id[16]; 89 char x86_model_id[64]; 90 /* in KB - valid for CPUS which support this call: */ 91 int x86_cache_size; 92 int x86_cache_alignment; /* In bytes */ 93 int x86_power; 94 unsigned long loops_per_jiffy; 95 #ifdef CONFIG_SMP 96 /* cpus sharing the last level cache: */ 97 cpumask_var_t llc_shared_map; 98 #endif 99 /* cpuid returned max cores value: */ 100 u16 x86_max_cores; 101 u16 apicid; 102 u16 initial_apicid; 103 u16 x86_clflush_size; 104 #ifdef CONFIG_SMP 105 /* number of cores as seen by the OS: */ 106 u16 booted_cores; 107 /* Physical processor id: */ 108 u16 phys_proc_id; 109 /* Core id: */ 110 u16 cpu_core_id; 111 /* Index into per_cpu list: */ 112 u16 cpu_index; 113 #endif 114 unsigned int x86_hyper_vendor; 115 } __attribute__((__aligned__(SMP_CACHE_BYTES))); 116 117 #define X86_VENDOR_INTEL 0 118 #define X86_VENDOR_CYRIX 1 119 #define X86_VENDOR_AMD 2 120 #define X86_VENDOR_UMC 3 121 #define X86_VENDOR_CENTAUR 5 122 #define X86_VENDOR_TRANSMETA 7 123 #define X86_VENDOR_NSC 8 124 #define X86_VENDOR_NUM 9 125 126 #define X86_VENDOR_UNKNOWN 0xff 127 128 #define X86_HYPER_VENDOR_NONE 0 129 #define X86_HYPER_VENDOR_VMWARE 1 130 131 /* 132 * capabilities of CPUs 133 */ 134 extern struct cpuinfo_x86 boot_cpu_data; 135 extern struct cpuinfo_x86 new_cpu_data; 136 137 extern struct tss_struct doublefault_tss; 138 extern __u32 cpu_caps_cleared[NCAPINTS]; 139 extern __u32 cpu_caps_set[NCAPINTS]; 140 141 #ifdef CONFIG_SMP 142 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 143 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 144 #define current_cpu_data __get_cpu_var(cpu_info) 145 #else 146 #define cpu_data(cpu) boot_cpu_data 147 #define current_cpu_data boot_cpu_data 148 #endif 149 150 extern const struct seq_operations cpuinfo_op; 151 152 static inline int hlt_works(int cpu) 153 { 154 #ifdef CONFIG_X86_32 155 return cpu_data(cpu).hlt_works_ok; 156 #else 157 return 1; 158 #endif 159 } 160 161 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 162 163 extern void cpu_detect(struct cpuinfo_x86 *c); 164 165 extern struct pt_regs *idle_regs(struct pt_regs *); 166 167 extern void early_cpu_init(void); 168 extern void identify_boot_cpu(void); 169 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 170 extern void print_cpu_info(struct cpuinfo_x86 *); 171 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); 172 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); 173 extern unsigned short num_cache_leaves; 174 175 extern void detect_extended_topology(struct cpuinfo_x86 *c); 176 extern void detect_ht(struct cpuinfo_x86 *c); 177 178 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 179 unsigned int *ecx, unsigned int *edx) 180 { 181 /* ecx is often an input as well as an output. */ 182 asm("cpuid" 183 : "=a" (*eax), 184 "=b" (*ebx), 185 "=c" (*ecx), 186 "=d" (*edx) 187 : "0" (*eax), "2" (*ecx)); 188 } 189 190 static inline void load_cr3(pgd_t *pgdir) 191 { 192 write_cr3(__pa(pgdir)); 193 } 194 195 #ifdef CONFIG_X86_32 196 /* This is the TSS defined by the hardware. */ 197 struct x86_hw_tss { 198 unsigned short back_link, __blh; 199 unsigned long sp0; 200 unsigned short ss0, __ss0h; 201 unsigned long sp1; 202 /* ss1 caches MSR_IA32_SYSENTER_CS: */ 203 unsigned short ss1, __ss1h; 204 unsigned long sp2; 205 unsigned short ss2, __ss2h; 206 unsigned long __cr3; 207 unsigned long ip; 208 unsigned long flags; 209 unsigned long ax; 210 unsigned long cx; 211 unsigned long dx; 212 unsigned long bx; 213 unsigned long sp; 214 unsigned long bp; 215 unsigned long si; 216 unsigned long di; 217 unsigned short es, __esh; 218 unsigned short cs, __csh; 219 unsigned short ss, __ssh; 220 unsigned short ds, __dsh; 221 unsigned short fs, __fsh; 222 unsigned short gs, __gsh; 223 unsigned short ldt, __ldth; 224 unsigned short trace; 225 unsigned short io_bitmap_base; 226 227 } __attribute__((packed)); 228 #else 229 struct x86_hw_tss { 230 u32 reserved1; 231 u64 sp0; 232 u64 sp1; 233 u64 sp2; 234 u64 reserved2; 235 u64 ist[7]; 236 u32 reserved3; 237 u32 reserved4; 238 u16 reserved5; 239 u16 io_bitmap_base; 240 241 } __attribute__((packed)) ____cacheline_aligned; 242 #endif 243 244 /* 245 * IO-bitmap sizes: 246 */ 247 #define IO_BITMAP_BITS 65536 248 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) 249 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) 250 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) 251 #define INVALID_IO_BITMAP_OFFSET 0x8000 252 253 struct tss_struct { 254 /* 255 * The hardware state: 256 */ 257 struct x86_hw_tss x86_tss; 258 259 /* 260 * The extra 1 is there because the CPU will access an 261 * additional byte beyond the end of the IO permission 262 * bitmap. The extra byte must be all 1 bits, and must 263 * be within the limit. 264 */ 265 unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; 266 267 /* 268 * .. and then another 0x100 bytes for the emergency kernel stack: 269 */ 270 unsigned long stack[64]; 271 272 } ____cacheline_aligned; 273 274 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss); 275 276 /* 277 * Save the original ist values for checking stack pointers during debugging 278 */ 279 struct orig_ist { 280 unsigned long ist[7]; 281 }; 282 283 #define MXCSR_DEFAULT 0x1f80 284 285 struct i387_fsave_struct { 286 u32 cwd; /* FPU Control Word */ 287 u32 swd; /* FPU Status Word */ 288 u32 twd; /* FPU Tag Word */ 289 u32 fip; /* FPU IP Offset */ 290 u32 fcs; /* FPU IP Selector */ 291 u32 foo; /* FPU Operand Pointer Offset */ 292 u32 fos; /* FPU Operand Pointer Selector */ 293 294 /* 8*10 bytes for each FP-reg = 80 bytes: */ 295 u32 st_space[20]; 296 297 /* Software status information [not touched by FSAVE ]: */ 298 u32 status; 299 }; 300 301 struct i387_fxsave_struct { 302 u16 cwd; /* Control Word */ 303 u16 swd; /* Status Word */ 304 u16 twd; /* Tag Word */ 305 u16 fop; /* Last Instruction Opcode */ 306 union { 307 struct { 308 u64 rip; /* Instruction Pointer */ 309 u64 rdp; /* Data Pointer */ 310 }; 311 struct { 312 u32 fip; /* FPU IP Offset */ 313 u32 fcs; /* FPU IP Selector */ 314 u32 foo; /* FPU Operand Offset */ 315 u32 fos; /* FPU Operand Selector */ 316 }; 317 }; 318 u32 mxcsr; /* MXCSR Register State */ 319 u32 mxcsr_mask; /* MXCSR Mask */ 320 321 /* 8*16 bytes for each FP-reg = 128 bytes: */ 322 u32 st_space[32]; 323 324 /* 16*16 bytes for each XMM-reg = 256 bytes: */ 325 u32 xmm_space[64]; 326 327 u32 padding[12]; 328 329 union { 330 u32 padding1[12]; 331 u32 sw_reserved[12]; 332 }; 333 334 } __attribute__((aligned(16))); 335 336 struct i387_soft_struct { 337 u32 cwd; 338 u32 swd; 339 u32 twd; 340 u32 fip; 341 u32 fcs; 342 u32 foo; 343 u32 fos; 344 /* 8*10 bytes for each FP-reg = 80 bytes: */ 345 u32 st_space[20]; 346 u8 ftop; 347 u8 changed; 348 u8 lookahead; 349 u8 no_update; 350 u8 rm; 351 u8 alimit; 352 struct math_emu_info *info; 353 u32 entry_eip; 354 }; 355 356 struct ymmh_struct { 357 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */ 358 u32 ymmh_space[64]; 359 }; 360 361 struct xsave_hdr_struct { 362 u64 xstate_bv; 363 u64 reserved1[2]; 364 u64 reserved2[5]; 365 } __attribute__((packed)); 366 367 struct xsave_struct { 368 struct i387_fxsave_struct i387; 369 struct xsave_hdr_struct xsave_hdr; 370 struct ymmh_struct ymmh; 371 /* new processor state extensions will go here */ 372 } __attribute__ ((packed, aligned (64))); 373 374 union thread_xstate { 375 struct i387_fsave_struct fsave; 376 struct i387_fxsave_struct fxsave; 377 struct i387_soft_struct soft; 378 struct xsave_struct xsave; 379 }; 380 381 #ifdef CONFIG_X86_64 382 DECLARE_PER_CPU(struct orig_ist, orig_ist); 383 384 union irq_stack_union { 385 char irq_stack[IRQ_STACK_SIZE]; 386 /* 387 * GCC hardcodes the stack canary as %gs:40. Since the 388 * irq_stack is the object at %gs:0, we reserve the bottom 389 * 48 bytes of the irq stack for the canary. 390 */ 391 struct { 392 char gs_base[40]; 393 unsigned long stack_canary; 394 }; 395 }; 396 397 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union); 398 DECLARE_INIT_PER_CPU(irq_stack_union); 399 400 DECLARE_PER_CPU(char *, irq_stack_ptr); 401 DECLARE_PER_CPU(unsigned int, irq_count); 402 extern unsigned long kernel_eflags; 403 extern asmlinkage void ignore_sysret(void); 404 #else /* X86_64 */ 405 #ifdef CONFIG_CC_STACKPROTECTOR 406 DECLARE_PER_CPU(unsigned long, stack_canary); 407 #endif 408 #endif /* X86_64 */ 409 410 extern unsigned int xstate_size; 411 extern void free_thread_xstate(struct task_struct *); 412 extern struct kmem_cache *task_xstate_cachep; 413 414 struct thread_struct { 415 /* Cached TLS descriptors: */ 416 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 417 unsigned long sp0; 418 unsigned long sp; 419 #ifdef CONFIG_X86_32 420 unsigned long sysenter_cs; 421 #else 422 unsigned long usersp; /* Copy from PDA */ 423 unsigned short es; 424 unsigned short ds; 425 unsigned short fsindex; 426 unsigned short gsindex; 427 #endif 428 #ifdef CONFIG_X86_32 429 unsigned long ip; 430 #endif 431 #ifdef CONFIG_X86_64 432 unsigned long fs; 433 #endif 434 unsigned long gs; 435 /* Hardware debugging registers: */ 436 unsigned long debugreg0; 437 unsigned long debugreg1; 438 unsigned long debugreg2; 439 unsigned long debugreg3; 440 unsigned long debugreg6; 441 unsigned long debugreg7; 442 /* Fault info: */ 443 unsigned long cr2; 444 unsigned long trap_no; 445 unsigned long error_code; 446 /* floating point and extended processor state */ 447 union thread_xstate *xstate; 448 #ifdef CONFIG_X86_32 449 /* Virtual 86 mode info */ 450 struct vm86_struct __user *vm86_info; 451 unsigned long screen_bitmap; 452 unsigned long v86flags; 453 unsigned long v86mask; 454 unsigned long saved_sp0; 455 unsigned int saved_fs; 456 unsigned int saved_gs; 457 #endif 458 /* IO permissions: */ 459 unsigned long *io_bitmap_ptr; 460 unsigned long iopl; 461 /* Max allowed port in the bitmap, in bytes: */ 462 unsigned io_bitmap_max; 463 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */ 464 unsigned long debugctlmsr; 465 /* Debug Store context; see asm/ds.h */ 466 struct ds_context *ds_ctx; 467 }; 468 469 static inline unsigned long native_get_debugreg(int regno) 470 { 471 unsigned long val = 0; /* Damn you, gcc! */ 472 473 switch (regno) { 474 case 0: 475 asm("mov %%db0, %0" :"=r" (val)); 476 break; 477 case 1: 478 asm("mov %%db1, %0" :"=r" (val)); 479 break; 480 case 2: 481 asm("mov %%db2, %0" :"=r" (val)); 482 break; 483 case 3: 484 asm("mov %%db3, %0" :"=r" (val)); 485 break; 486 case 6: 487 asm("mov %%db6, %0" :"=r" (val)); 488 break; 489 case 7: 490 asm("mov %%db7, %0" :"=r" (val)); 491 break; 492 default: 493 BUG(); 494 } 495 return val; 496 } 497 498 static inline void native_set_debugreg(int regno, unsigned long value) 499 { 500 switch (regno) { 501 case 0: 502 asm("mov %0, %%db0" ::"r" (value)); 503 break; 504 case 1: 505 asm("mov %0, %%db1" ::"r" (value)); 506 break; 507 case 2: 508 asm("mov %0, %%db2" ::"r" (value)); 509 break; 510 case 3: 511 asm("mov %0, %%db3" ::"r" (value)); 512 break; 513 case 6: 514 asm("mov %0, %%db6" ::"r" (value)); 515 break; 516 case 7: 517 asm("mov %0, %%db7" ::"r" (value)); 518 break; 519 default: 520 BUG(); 521 } 522 } 523 524 /* 525 * Set IOPL bits in EFLAGS from given mask 526 */ 527 static inline void native_set_iopl_mask(unsigned mask) 528 { 529 #ifdef CONFIG_X86_32 530 unsigned int reg; 531 532 asm volatile ("pushfl;" 533 "popl %0;" 534 "andl %1, %0;" 535 "orl %2, %0;" 536 "pushl %0;" 537 "popfl" 538 : "=&r" (reg) 539 : "i" (~X86_EFLAGS_IOPL), "r" (mask)); 540 #endif 541 } 542 543 static inline void 544 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread) 545 { 546 tss->x86_tss.sp0 = thread->sp0; 547 #ifdef CONFIG_X86_32 548 /* Only happens when SEP is enabled, no need to test "SEP"arately: */ 549 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { 550 tss->x86_tss.ss1 = thread->sysenter_cs; 551 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); 552 } 553 #endif 554 } 555 556 static inline void native_swapgs(void) 557 { 558 #ifdef CONFIG_X86_64 559 asm volatile("swapgs" ::: "memory"); 560 #endif 561 } 562 563 #ifdef CONFIG_PARAVIRT 564 #include <asm/paravirt.h> 565 #else 566 #define __cpuid native_cpuid 567 #define paravirt_enabled() 0 568 569 /* 570 * These special macros can be used to get or set a debugging register 571 */ 572 #define get_debugreg(var, register) \ 573 (var) = native_get_debugreg(register) 574 #define set_debugreg(value, register) \ 575 native_set_debugreg(register, value) 576 577 static inline void load_sp0(struct tss_struct *tss, 578 struct thread_struct *thread) 579 { 580 native_load_sp0(tss, thread); 581 } 582 583 #define set_iopl_mask native_set_iopl_mask 584 #endif /* CONFIG_PARAVIRT */ 585 586 /* 587 * Save the cr4 feature set we're using (ie 588 * Pentium 4MB enable and PPro Global page 589 * enable), so that any CPU's that boot up 590 * after us can get the correct flags. 591 */ 592 extern unsigned long mmu_cr4_features; 593 594 static inline void set_in_cr4(unsigned long mask) 595 { 596 unsigned cr4; 597 598 mmu_cr4_features |= mask; 599 cr4 = read_cr4(); 600 cr4 |= mask; 601 write_cr4(cr4); 602 } 603 604 static inline void clear_in_cr4(unsigned long mask) 605 { 606 unsigned cr4; 607 608 mmu_cr4_features &= ~mask; 609 cr4 = read_cr4(); 610 cr4 &= ~mask; 611 write_cr4(cr4); 612 } 613 614 typedef struct { 615 unsigned long seg; 616 } mm_segment_t; 617 618 619 /* 620 * create a kernel thread without removing it from tasklists 621 */ 622 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); 623 624 /* Free all resources held by a thread. */ 625 extern void release_thread(struct task_struct *); 626 627 /* Prepare to copy thread state - unlazy all lazy state */ 628 extern void prepare_to_copy(struct task_struct *tsk); 629 630 unsigned long get_wchan(struct task_struct *p); 631 632 /* 633 * Generic CPUID function 634 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 635 * resulting in stale register contents being returned. 636 */ 637 static inline void cpuid(unsigned int op, 638 unsigned int *eax, unsigned int *ebx, 639 unsigned int *ecx, unsigned int *edx) 640 { 641 *eax = op; 642 *ecx = 0; 643 __cpuid(eax, ebx, ecx, edx); 644 } 645 646 /* Some CPUID calls want 'count' to be placed in ecx */ 647 static inline void cpuid_count(unsigned int op, int count, 648 unsigned int *eax, unsigned int *ebx, 649 unsigned int *ecx, unsigned int *edx) 650 { 651 *eax = op; 652 *ecx = count; 653 __cpuid(eax, ebx, ecx, edx); 654 } 655 656 /* 657 * CPUID functions returning a single datum 658 */ 659 static inline unsigned int cpuid_eax(unsigned int op) 660 { 661 unsigned int eax, ebx, ecx, edx; 662 663 cpuid(op, &eax, &ebx, &ecx, &edx); 664 665 return eax; 666 } 667 668 static inline unsigned int cpuid_ebx(unsigned int op) 669 { 670 unsigned int eax, ebx, ecx, edx; 671 672 cpuid(op, &eax, &ebx, &ecx, &edx); 673 674 return ebx; 675 } 676 677 static inline unsigned int cpuid_ecx(unsigned int op) 678 { 679 unsigned int eax, ebx, ecx, edx; 680 681 cpuid(op, &eax, &ebx, &ecx, &edx); 682 683 return ecx; 684 } 685 686 static inline unsigned int cpuid_edx(unsigned int op) 687 { 688 unsigned int eax, ebx, ecx, edx; 689 690 cpuid(op, &eax, &ebx, &ecx, &edx); 691 692 return edx; 693 } 694 695 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 696 static inline void rep_nop(void) 697 { 698 asm volatile("rep; nop" ::: "memory"); 699 } 700 701 static inline void cpu_relax(void) 702 { 703 rep_nop(); 704 } 705 706 /* Stop speculative execution: */ 707 static inline void sync_core(void) 708 { 709 int tmp; 710 711 asm volatile("cpuid" : "=a" (tmp) : "0" (1) 712 : "ebx", "ecx", "edx", "memory"); 713 } 714 715 static inline void __monitor(const void *eax, unsigned long ecx, 716 unsigned long edx) 717 { 718 /* "monitor %eax, %ecx, %edx;" */ 719 asm volatile(".byte 0x0f, 0x01, 0xc8;" 720 :: "a" (eax), "c" (ecx), "d"(edx)); 721 } 722 723 static inline void __mwait(unsigned long eax, unsigned long ecx) 724 { 725 /* "mwait %eax, %ecx;" */ 726 asm volatile(".byte 0x0f, 0x01, 0xc9;" 727 :: "a" (eax), "c" (ecx)); 728 } 729 730 static inline void __sti_mwait(unsigned long eax, unsigned long ecx) 731 { 732 trace_hardirqs_on(); 733 /* "mwait %eax, %ecx;" */ 734 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;" 735 :: "a" (eax), "c" (ecx)); 736 } 737 738 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx); 739 740 extern void select_idle_routine(const struct cpuinfo_x86 *c); 741 extern void init_c1e_mask(void); 742 743 extern unsigned long boot_option_idle_override; 744 extern unsigned long idle_halt; 745 extern unsigned long idle_nomwait; 746 747 /* 748 * on systems with caches, caches must be flashed as the absolute 749 * last instruction before going into a suspended halt. Otherwise, 750 * dirty data can linger in the cache and become stale on resume, 751 * leading to strange errors. 752 * 753 * perform a variety of operations to guarantee that the compiler 754 * will not reorder instructions. wbinvd itself is serializing 755 * so the processor will not reorder. 756 * 757 * Systems without cache can just go into halt. 758 */ 759 static inline void wbinvd_halt(void) 760 { 761 mb(); 762 /* check for clflush to determine if wbinvd is legal */ 763 if (cpu_has_clflush) 764 asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory"); 765 else 766 while (1) 767 halt(); 768 } 769 770 extern void enable_sep_cpu(void); 771 extern int sysenter_setup(void); 772 773 /* Defined in head.S */ 774 extern struct desc_ptr early_gdt_descr; 775 776 extern void cpu_set_gdt(int); 777 extern void switch_to_new_gdt(int); 778 extern void load_percpu_segment(int); 779 extern void cpu_init(void); 780 781 static inline unsigned long get_debugctlmsr(void) 782 { 783 unsigned long debugctlmsr = 0; 784 785 #ifndef CONFIG_X86_DEBUGCTLMSR 786 if (boot_cpu_data.x86 < 6) 787 return 0; 788 #endif 789 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 790 791 return debugctlmsr; 792 } 793 794 static inline unsigned long get_debugctlmsr_on_cpu(int cpu) 795 { 796 u64 debugctlmsr = 0; 797 u32 val1, val2; 798 799 #ifndef CONFIG_X86_DEBUGCTLMSR 800 if (boot_cpu_data.x86 < 6) 801 return 0; 802 #endif 803 rdmsr_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR, &val1, &val2); 804 debugctlmsr = val1 | ((u64)val2 << 32); 805 806 return debugctlmsr; 807 } 808 809 static inline void update_debugctlmsr(unsigned long debugctlmsr) 810 { 811 #ifndef CONFIG_X86_DEBUGCTLMSR 812 if (boot_cpu_data.x86 < 6) 813 return; 814 #endif 815 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 816 } 817 818 static inline void update_debugctlmsr_on_cpu(int cpu, 819 unsigned long debugctlmsr) 820 { 821 #ifndef CONFIG_X86_DEBUGCTLMSR 822 if (boot_cpu_data.x86 < 6) 823 return; 824 #endif 825 wrmsr_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR, 826 (u32)((u64)debugctlmsr), 827 (u32)((u64)debugctlmsr >> 32)); 828 } 829 830 /* 831 * from system description table in BIOS. Mostly for MCA use, but 832 * others may find it useful: 833 */ 834 extern unsigned int machine_id; 835 extern unsigned int machine_submodel_id; 836 extern unsigned int BIOS_revision; 837 838 /* Boot loader type from the setup header: */ 839 extern int bootloader_type; 840 extern int bootloader_version; 841 842 extern char ignore_fpu_irq; 843 844 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 845 #define ARCH_HAS_PREFETCHW 846 #define ARCH_HAS_SPINLOCK_PREFETCH 847 848 #ifdef CONFIG_X86_32 849 # define BASE_PREFETCH ASM_NOP4 850 # define ARCH_HAS_PREFETCH 851 #else 852 # define BASE_PREFETCH "prefetcht0 (%1)" 853 #endif 854 855 /* 856 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 857 * 858 * It's not worth to care about 3dnow prefetches for the K6 859 * because they are microcoded there and very slow. 860 */ 861 static inline void prefetch(const void *x) 862 { 863 alternative_input(BASE_PREFETCH, 864 "prefetchnta (%1)", 865 X86_FEATURE_XMM, 866 "r" (x)); 867 } 868 869 /* 870 * 3dnow prefetch to get an exclusive cache line. 871 * Useful for spinlocks to avoid one state transition in the 872 * cache coherency protocol: 873 */ 874 static inline void prefetchw(const void *x) 875 { 876 alternative_input(BASE_PREFETCH, 877 "prefetchw (%1)", 878 X86_FEATURE_3DNOW, 879 "r" (x)); 880 } 881 882 static inline void spin_lock_prefetch(const void *x) 883 { 884 prefetchw(x); 885 } 886 887 #ifdef CONFIG_X86_32 888 /* 889 * User space process size: 3GB (default). 890 */ 891 #define TASK_SIZE PAGE_OFFSET 892 #define TASK_SIZE_MAX TASK_SIZE 893 #define STACK_TOP TASK_SIZE 894 #define STACK_TOP_MAX STACK_TOP 895 896 #define INIT_THREAD { \ 897 .sp0 = sizeof(init_stack) + (long)&init_stack, \ 898 .vm86_info = NULL, \ 899 .sysenter_cs = __KERNEL_CS, \ 900 .io_bitmap_ptr = NULL, \ 901 } 902 903 /* 904 * Note that the .io_bitmap member must be extra-big. This is because 905 * the CPU will access an additional byte beyond the end of the IO 906 * permission bitmap. The extra byte must be all 1 bits, and must 907 * be within the limit. 908 */ 909 #define INIT_TSS { \ 910 .x86_tss = { \ 911 .sp0 = sizeof(init_stack) + (long)&init_stack, \ 912 .ss0 = __KERNEL_DS, \ 913 .ss1 = __KERNEL_CS, \ 914 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \ 915 }, \ 916 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \ 917 } 918 919 extern unsigned long thread_saved_pc(struct task_struct *tsk); 920 921 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long)) 922 #define KSTK_TOP(info) \ 923 ({ \ 924 unsigned long *__ptr = (unsigned long *)(info); \ 925 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \ 926 }) 927 928 /* 929 * The below -8 is to reserve 8 bytes on top of the ring0 stack. 930 * This is necessary to guarantee that the entire "struct pt_regs" 931 * is accessable even if the CPU haven't stored the SS/ESP registers 932 * on the stack (interrupt gate does not save these registers 933 * when switching to the same priv ring). 934 * Therefore beware: accessing the ss/esp fields of the 935 * "struct pt_regs" is possible, but they may contain the 936 * completely wrong values. 937 */ 938 #define task_pt_regs(task) \ 939 ({ \ 940 struct pt_regs *__regs__; \ 941 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \ 942 __regs__ - 1; \ 943 }) 944 945 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 946 947 #else 948 /* 949 * User space process size. 47bits minus one guard page. 950 */ 951 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE) 952 953 /* This decides where the kernel will search for a free chunk of vm 954 * space during mmap's. 955 */ 956 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ 957 0xc0000000 : 0xFFFFe000) 958 959 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \ 960 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 961 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \ 962 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 963 964 #define STACK_TOP TASK_SIZE 965 #define STACK_TOP_MAX TASK_SIZE_MAX 966 967 #define INIT_THREAD { \ 968 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ 969 } 970 971 #define INIT_TSS { \ 972 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ 973 } 974 975 /* 976 * Return saved PC of a blocked thread. 977 * What is this good for? it will be always the scheduler or ret_from_fork. 978 */ 979 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8)) 980 981 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) 982 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */ 983 #endif /* CONFIG_X86_64 */ 984 985 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 986 unsigned long new_sp); 987 988 /* 989 * This decides where the kernel will search for a free chunk of vm 990 * space during mmap's. 991 */ 992 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) 993 994 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 995 996 /* Get/set a process' ability to use the timestamp counter instruction */ 997 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 998 #define SET_TSC_CTL(val) set_tsc_mode((val)) 999 1000 extern int get_tsc_mode(unsigned long adr); 1001 extern int set_tsc_mode(unsigned int val); 1002 1003 #endif /* _ASM_X86_PROCESSOR_H */ 1004