1 #ifndef _ASM_X86_PROCESSOR_H 2 #define _ASM_X86_PROCESSOR_H 3 4 #include <asm/processor-flags.h> 5 6 /* Forward declaration, a strange C thing */ 7 struct task_struct; 8 struct mm_struct; 9 struct vm86; 10 11 #include <asm/math_emu.h> 12 #include <asm/segment.h> 13 #include <asm/types.h> 14 #include <uapi/asm/sigcontext.h> 15 #include <asm/current.h> 16 #include <asm/cpufeatures.h> 17 #include <asm/page.h> 18 #include <asm/pgtable_types.h> 19 #include <asm/percpu.h> 20 #include <asm/msr.h> 21 #include <asm/desc_defs.h> 22 #include <asm/nops.h> 23 #include <asm/special_insns.h> 24 #include <asm/fpu/types.h> 25 26 #include <linux/personality.h> 27 #include <linux/cache.h> 28 #include <linux/threads.h> 29 #include <linux/math64.h> 30 #include <linux/err.h> 31 #include <linux/irqflags.h> 32 33 /* 34 * We handle most unaligned accesses in hardware. On the other hand 35 * unaligned DMA can be quite expensive on some Nehalem processors. 36 * 37 * Based on this we disable the IP header alignment in network drivers. 38 */ 39 #define NET_IP_ALIGN 0 40 41 #define HBP_NUM 4 42 /* 43 * Default implementation of macro that returns current 44 * instruction pointer ("program counter"). 45 */ 46 static inline void *current_text_addr(void) 47 { 48 void *pc; 49 50 asm volatile("mov $1f, %0; 1:":"=r" (pc)); 51 52 return pc; 53 } 54 55 /* 56 * These alignment constraints are for performance in the vSMP case, 57 * but in the task_struct case we must also meet hardware imposed 58 * alignment requirements of the FPU state: 59 */ 60 #ifdef CONFIG_X86_VSMP 61 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 62 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 63 #else 64 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state) 65 # define ARCH_MIN_MMSTRUCT_ALIGN 0 66 #endif 67 68 enum tlb_infos { 69 ENTRIES, 70 NR_INFO 71 }; 72 73 extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 74 extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 75 extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 76 extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 77 extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 78 extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 79 extern u16 __read_mostly tlb_lld_1g[NR_INFO]; 80 81 /* 82 * CPU type and hardware bug flags. Kept separately for each CPU. 83 * Members of this structure are referenced in head.S, so think twice 84 * before touching them. [mj] 85 */ 86 87 struct cpuinfo_x86 { 88 __u8 x86; /* CPU family */ 89 __u8 x86_vendor; /* CPU vendor */ 90 __u8 x86_model; 91 __u8 x86_mask; 92 #ifdef CONFIG_X86_32 93 char wp_works_ok; /* It doesn't on 386's */ 94 95 /* Problems on some 486Dx4's and old 386's: */ 96 char rfu; 97 char pad0; 98 char pad1; 99 #else 100 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 101 int x86_tlbsize; 102 #endif 103 __u8 x86_virt_bits; 104 __u8 x86_phys_bits; 105 /* CPUID returned core id bits: */ 106 __u8 x86_coreid_bits; 107 /* Max extended CPUID function supported: */ 108 __u32 extended_cpuid_level; 109 /* Maximum supported CPUID level, -1=no CPUID: */ 110 int cpuid_level; 111 __u32 x86_capability[NCAPINTS + NBUGINTS]; 112 char x86_vendor_id[16]; 113 char x86_model_id[64]; 114 /* in KB - valid for CPUS which support this call: */ 115 int x86_cache_size; 116 int x86_cache_alignment; /* In bytes */ 117 /* Cache QoS architectural values: */ 118 int x86_cache_max_rmid; /* max index */ 119 int x86_cache_occ_scale; /* scale to bytes */ 120 int x86_power; 121 unsigned long loops_per_jiffy; 122 /* cpuid returned max cores value: */ 123 u16 x86_max_cores; 124 u16 apicid; 125 u16 initial_apicid; 126 u16 x86_clflush_size; 127 /* number of cores as seen by the OS: */ 128 u16 booted_cores; 129 /* Physical processor id: */ 130 u16 phys_proc_id; 131 /* Logical processor id: */ 132 u16 logical_proc_id; 133 /* Core id: */ 134 u16 cpu_core_id; 135 /* Index into per_cpu list: */ 136 u16 cpu_index; 137 u32 microcode; 138 }; 139 140 #define X86_VENDOR_INTEL 0 141 #define X86_VENDOR_CYRIX 1 142 #define X86_VENDOR_AMD 2 143 #define X86_VENDOR_UMC 3 144 #define X86_VENDOR_CENTAUR 5 145 #define X86_VENDOR_TRANSMETA 7 146 #define X86_VENDOR_NSC 8 147 #define X86_VENDOR_NUM 9 148 149 #define X86_VENDOR_UNKNOWN 0xff 150 151 /* 152 * capabilities of CPUs 153 */ 154 extern struct cpuinfo_x86 boot_cpu_data; 155 extern struct cpuinfo_x86 new_cpu_data; 156 157 extern struct tss_struct doublefault_tss; 158 extern __u32 cpu_caps_cleared[NCAPINTS]; 159 extern __u32 cpu_caps_set[NCAPINTS]; 160 161 #ifdef CONFIG_SMP 162 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 163 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 164 #else 165 #define cpu_info boot_cpu_data 166 #define cpu_data(cpu) boot_cpu_data 167 #endif 168 169 extern const struct seq_operations cpuinfo_op; 170 171 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 172 173 extern void cpu_detect(struct cpuinfo_x86 *c); 174 175 extern void early_cpu_init(void); 176 extern void identify_boot_cpu(void); 177 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 178 extern void print_cpu_info(struct cpuinfo_x86 *); 179 void print_cpu_msr(struct cpuinfo_x86 *); 180 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); 181 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); 182 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); 183 184 extern void detect_extended_topology(struct cpuinfo_x86 *c); 185 extern void detect_ht(struct cpuinfo_x86 *c); 186 187 #ifdef CONFIG_X86_32 188 extern int have_cpuid_p(void); 189 #else 190 static inline int have_cpuid_p(void) 191 { 192 return 1; 193 } 194 #endif 195 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 196 unsigned int *ecx, unsigned int *edx) 197 { 198 /* ecx is often an input as well as an output. */ 199 asm volatile("cpuid" 200 : "=a" (*eax), 201 "=b" (*ebx), 202 "=c" (*ecx), 203 "=d" (*edx) 204 : "0" (*eax), "2" (*ecx) 205 : "memory"); 206 } 207 208 static inline void load_cr3(pgd_t *pgdir) 209 { 210 write_cr3(__pa(pgdir)); 211 } 212 213 #ifdef CONFIG_X86_32 214 /* This is the TSS defined by the hardware. */ 215 struct x86_hw_tss { 216 unsigned short back_link, __blh; 217 unsigned long sp0; 218 unsigned short ss0, __ss0h; 219 unsigned long sp1; 220 221 /* 222 * We don't use ring 1, so ss1 is a convenient scratch space in 223 * the same cacheline as sp0. We use ss1 to cache the value in 224 * MSR_IA32_SYSENTER_CS. When we context switch 225 * MSR_IA32_SYSENTER_CS, we first check if the new value being 226 * written matches ss1, and, if it's not, then we wrmsr the new 227 * value and update ss1. 228 * 229 * The only reason we context switch MSR_IA32_SYSENTER_CS is 230 * that we set it to zero in vm86 tasks to avoid corrupting the 231 * stack if we were to go through the sysenter path from vm86 232 * mode. 233 */ 234 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ 235 236 unsigned short __ss1h; 237 unsigned long sp2; 238 unsigned short ss2, __ss2h; 239 unsigned long __cr3; 240 unsigned long ip; 241 unsigned long flags; 242 unsigned long ax; 243 unsigned long cx; 244 unsigned long dx; 245 unsigned long bx; 246 unsigned long sp; 247 unsigned long bp; 248 unsigned long si; 249 unsigned long di; 250 unsigned short es, __esh; 251 unsigned short cs, __csh; 252 unsigned short ss, __ssh; 253 unsigned short ds, __dsh; 254 unsigned short fs, __fsh; 255 unsigned short gs, __gsh; 256 unsigned short ldt, __ldth; 257 unsigned short trace; 258 unsigned short io_bitmap_base; 259 260 } __attribute__((packed)); 261 #else 262 struct x86_hw_tss { 263 u32 reserved1; 264 u64 sp0; 265 u64 sp1; 266 u64 sp2; 267 u64 reserved2; 268 u64 ist[7]; 269 u32 reserved3; 270 u32 reserved4; 271 u16 reserved5; 272 u16 io_bitmap_base; 273 274 } __attribute__((packed)) ____cacheline_aligned; 275 #endif 276 277 /* 278 * IO-bitmap sizes: 279 */ 280 #define IO_BITMAP_BITS 65536 281 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) 282 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) 283 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) 284 #define INVALID_IO_BITMAP_OFFSET 0x8000 285 286 struct tss_struct { 287 /* 288 * The hardware state: 289 */ 290 struct x86_hw_tss x86_tss; 291 292 /* 293 * The extra 1 is there because the CPU will access an 294 * additional byte beyond the end of the IO permission 295 * bitmap. The extra byte must be all 1 bits, and must 296 * be within the limit. 297 */ 298 unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; 299 300 #ifdef CONFIG_X86_32 301 /* 302 * Space for the temporary SYSENTER stack. 303 */ 304 unsigned long SYSENTER_stack_canary; 305 unsigned long SYSENTER_stack[64]; 306 #endif 307 308 } ____cacheline_aligned; 309 310 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss); 311 312 #ifdef CONFIG_X86_32 313 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack); 314 #endif 315 316 /* 317 * Save the original ist values for checking stack pointers during debugging 318 */ 319 struct orig_ist { 320 unsigned long ist[7]; 321 }; 322 323 #ifdef CONFIG_X86_64 324 DECLARE_PER_CPU(struct orig_ist, orig_ist); 325 326 union irq_stack_union { 327 char irq_stack[IRQ_STACK_SIZE]; 328 /* 329 * GCC hardcodes the stack canary as %gs:40. Since the 330 * irq_stack is the object at %gs:0, we reserve the bottom 331 * 48 bytes of the irq stack for the canary. 332 */ 333 struct { 334 char gs_base[40]; 335 unsigned long stack_canary; 336 }; 337 }; 338 339 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible; 340 DECLARE_INIT_PER_CPU(irq_stack_union); 341 342 DECLARE_PER_CPU(char *, irq_stack_ptr); 343 DECLARE_PER_CPU(unsigned int, irq_count); 344 extern asmlinkage void ignore_sysret(void); 345 #else /* X86_64 */ 346 #ifdef CONFIG_CC_STACKPROTECTOR 347 /* 348 * Make sure stack canary segment base is cached-aligned: 349 * "For Intel Atom processors, avoid non zero segment base address 350 * that is not aligned to cache line boundary at all cost." 351 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) 352 */ 353 struct stack_canary { 354 char __pad[20]; /* canary at %gs:20 */ 355 unsigned long canary; 356 }; 357 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 358 #endif 359 /* 360 * per-CPU IRQ handling stacks 361 */ 362 struct irq_stack { 363 u32 stack[THREAD_SIZE/sizeof(u32)]; 364 } __aligned(THREAD_SIZE); 365 366 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack); 367 DECLARE_PER_CPU(struct irq_stack *, softirq_stack); 368 #endif /* X86_64 */ 369 370 extern unsigned int fpu_kernel_xstate_size; 371 extern unsigned int fpu_user_xstate_size; 372 373 struct perf_event; 374 375 typedef struct { 376 unsigned long seg; 377 } mm_segment_t; 378 379 struct thread_struct { 380 /* Cached TLS descriptors: */ 381 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 382 unsigned long sp0; 383 unsigned long sp; 384 #ifdef CONFIG_X86_32 385 unsigned long sysenter_cs; 386 #else 387 unsigned short es; 388 unsigned short ds; 389 unsigned short fsindex; 390 unsigned short gsindex; 391 #endif 392 393 u32 status; /* thread synchronous flags */ 394 395 #ifdef CONFIG_X86_64 396 unsigned long fsbase; 397 unsigned long gsbase; 398 #else 399 /* 400 * XXX: this could presumably be unsigned short. Alternatively, 401 * 32-bit kernels could be taught to use fsindex instead. 402 */ 403 unsigned long fs; 404 unsigned long gs; 405 #endif 406 407 /* Save middle states of ptrace breakpoints */ 408 struct perf_event *ptrace_bps[HBP_NUM]; 409 /* Debug status used for traps, single steps, etc... */ 410 unsigned long debugreg6; 411 /* Keep track of the exact dr7 value set by the user */ 412 unsigned long ptrace_dr7; 413 /* Fault info: */ 414 unsigned long cr2; 415 unsigned long trap_nr; 416 unsigned long error_code; 417 #ifdef CONFIG_VM86 418 /* Virtual 86 mode info */ 419 struct vm86 *vm86; 420 #endif 421 /* IO permissions: */ 422 unsigned long *io_bitmap_ptr; 423 unsigned long iopl; 424 /* Max allowed port in the bitmap, in bytes: */ 425 unsigned io_bitmap_max; 426 427 mm_segment_t addr_limit; 428 429 unsigned int sig_on_uaccess_err:1; 430 unsigned int uaccess_err:1; /* uaccess failed */ 431 432 /* Floating point and extended processor state */ 433 struct fpu fpu; 434 /* 435 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at 436 * the end. 437 */ 438 }; 439 440 /* 441 * Thread-synchronous status. 442 * 443 * This is different from the flags in that nobody else 444 * ever touches our thread-synchronous status, so we don't 445 * have to worry about atomic accesses. 446 */ 447 #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/ 448 449 /* 450 * Set IOPL bits in EFLAGS from given mask 451 */ 452 static inline void native_set_iopl_mask(unsigned mask) 453 { 454 #ifdef CONFIG_X86_32 455 unsigned int reg; 456 457 asm volatile ("pushfl;" 458 "popl %0;" 459 "andl %1, %0;" 460 "orl %2, %0;" 461 "pushl %0;" 462 "popfl" 463 : "=&r" (reg) 464 : "i" (~X86_EFLAGS_IOPL), "r" (mask)); 465 #endif 466 } 467 468 static inline void 469 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread) 470 { 471 tss->x86_tss.sp0 = thread->sp0; 472 #ifdef CONFIG_X86_32 473 /* Only happens when SEP is enabled, no need to test "SEP"arately: */ 474 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { 475 tss->x86_tss.ss1 = thread->sysenter_cs; 476 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); 477 } 478 #endif 479 } 480 481 static inline void native_swapgs(void) 482 { 483 #ifdef CONFIG_X86_64 484 asm volatile("swapgs" ::: "memory"); 485 #endif 486 } 487 488 static inline unsigned long current_top_of_stack(void) 489 { 490 #ifdef CONFIG_X86_64 491 return this_cpu_read_stable(cpu_tss.x86_tss.sp0); 492 #else 493 /* sp0 on x86_32 is special in and around vm86 mode. */ 494 return this_cpu_read_stable(cpu_current_top_of_stack); 495 #endif 496 } 497 498 #ifdef CONFIG_PARAVIRT 499 #include <asm/paravirt.h> 500 #else 501 #define __cpuid native_cpuid 502 503 static inline void load_sp0(struct tss_struct *tss, 504 struct thread_struct *thread) 505 { 506 native_load_sp0(tss, thread); 507 } 508 509 #define set_iopl_mask native_set_iopl_mask 510 #endif /* CONFIG_PARAVIRT */ 511 512 /* Free all resources held by a thread. */ 513 extern void release_thread(struct task_struct *); 514 515 unsigned long get_wchan(struct task_struct *p); 516 517 /* 518 * Generic CPUID function 519 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 520 * resulting in stale register contents being returned. 521 */ 522 static inline void cpuid(unsigned int op, 523 unsigned int *eax, unsigned int *ebx, 524 unsigned int *ecx, unsigned int *edx) 525 { 526 *eax = op; 527 *ecx = 0; 528 __cpuid(eax, ebx, ecx, edx); 529 } 530 531 /* Some CPUID calls want 'count' to be placed in ecx */ 532 static inline void cpuid_count(unsigned int op, int count, 533 unsigned int *eax, unsigned int *ebx, 534 unsigned int *ecx, unsigned int *edx) 535 { 536 *eax = op; 537 *ecx = count; 538 __cpuid(eax, ebx, ecx, edx); 539 } 540 541 /* 542 * CPUID functions returning a single datum 543 */ 544 static inline unsigned int cpuid_eax(unsigned int op) 545 { 546 unsigned int eax, ebx, ecx, edx; 547 548 cpuid(op, &eax, &ebx, &ecx, &edx); 549 550 return eax; 551 } 552 553 static inline unsigned int cpuid_ebx(unsigned int op) 554 { 555 unsigned int eax, ebx, ecx, edx; 556 557 cpuid(op, &eax, &ebx, &ecx, &edx); 558 559 return ebx; 560 } 561 562 static inline unsigned int cpuid_ecx(unsigned int op) 563 { 564 unsigned int eax, ebx, ecx, edx; 565 566 cpuid(op, &eax, &ebx, &ecx, &edx); 567 568 return ecx; 569 } 570 571 static inline unsigned int cpuid_edx(unsigned int op) 572 { 573 unsigned int eax, ebx, ecx, edx; 574 575 cpuid(op, &eax, &ebx, &ecx, &edx); 576 577 return edx; 578 } 579 580 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 581 static __always_inline void rep_nop(void) 582 { 583 asm volatile("rep; nop" ::: "memory"); 584 } 585 586 static __always_inline void cpu_relax(void) 587 { 588 rep_nop(); 589 } 590 591 /* Stop speculative execution and prefetching of modified code. */ 592 static inline void sync_core(void) 593 { 594 int tmp; 595 596 #ifdef CONFIG_M486 597 /* 598 * Do a CPUID if available, otherwise do a jump. The jump 599 * can conveniently enough be the jump around CPUID. 600 */ 601 asm volatile("cmpl %2,%1\n\t" 602 "jl 1f\n\t" 603 "cpuid\n" 604 "1:" 605 : "=a" (tmp) 606 : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1) 607 : "ebx", "ecx", "edx", "memory"); 608 #else 609 /* 610 * CPUID is a barrier to speculative execution. 611 * Prefetched instructions are automatically 612 * invalidated when modified. 613 */ 614 asm volatile("cpuid" 615 : "=a" (tmp) 616 : "0" (1) 617 : "ebx", "ecx", "edx", "memory"); 618 #endif 619 } 620 621 extern void select_idle_routine(const struct cpuinfo_x86 *c); 622 extern void init_amd_e400_c1e_mask(void); 623 624 extern unsigned long boot_option_idle_override; 625 extern bool amd_e400_c1e_detected; 626 627 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 628 IDLE_POLL}; 629 630 extern void enable_sep_cpu(void); 631 extern int sysenter_setup(void); 632 633 extern void early_trap_init(void); 634 void early_trap_pf_init(void); 635 636 /* Defined in head.S */ 637 extern struct desc_ptr early_gdt_descr; 638 639 extern void cpu_set_gdt(int); 640 extern void switch_to_new_gdt(int); 641 extern void load_percpu_segment(int); 642 extern void cpu_init(void); 643 644 static inline unsigned long get_debugctlmsr(void) 645 { 646 unsigned long debugctlmsr = 0; 647 648 #ifndef CONFIG_X86_DEBUGCTLMSR 649 if (boot_cpu_data.x86 < 6) 650 return 0; 651 #endif 652 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 653 654 return debugctlmsr; 655 } 656 657 static inline void update_debugctlmsr(unsigned long debugctlmsr) 658 { 659 #ifndef CONFIG_X86_DEBUGCTLMSR 660 if (boot_cpu_data.x86 < 6) 661 return; 662 #endif 663 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 664 } 665 666 extern void set_task_blockstep(struct task_struct *task, bool on); 667 668 /* Boot loader type from the setup header: */ 669 extern int bootloader_type; 670 extern int bootloader_version; 671 672 extern char ignore_fpu_irq; 673 674 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 675 #define ARCH_HAS_PREFETCHW 676 #define ARCH_HAS_SPINLOCK_PREFETCH 677 678 #ifdef CONFIG_X86_32 679 # define BASE_PREFETCH "" 680 # define ARCH_HAS_PREFETCH 681 #else 682 # define BASE_PREFETCH "prefetcht0 %P1" 683 #endif 684 685 /* 686 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 687 * 688 * It's not worth to care about 3dnow prefetches for the K6 689 * because they are microcoded there and very slow. 690 */ 691 static inline void prefetch(const void *x) 692 { 693 alternative_input(BASE_PREFETCH, "prefetchnta %P1", 694 X86_FEATURE_XMM, 695 "m" (*(const char *)x)); 696 } 697 698 /* 699 * 3dnow prefetch to get an exclusive cache line. 700 * Useful for spinlocks to avoid one state transition in the 701 * cache coherency protocol: 702 */ 703 static inline void prefetchw(const void *x) 704 { 705 alternative_input(BASE_PREFETCH, "prefetchw %P1", 706 X86_FEATURE_3DNOWPREFETCH, 707 "m" (*(const char *)x)); 708 } 709 710 static inline void spin_lock_prefetch(const void *x) 711 { 712 prefetchw(x); 713 } 714 715 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ 716 TOP_OF_KERNEL_STACK_PADDING) 717 718 #ifdef CONFIG_X86_32 719 /* 720 * User space process size: 3GB (default). 721 */ 722 #define TASK_SIZE PAGE_OFFSET 723 #define TASK_SIZE_MAX TASK_SIZE 724 #define STACK_TOP TASK_SIZE 725 #define STACK_TOP_MAX STACK_TOP 726 727 #define INIT_THREAD { \ 728 .sp0 = TOP_OF_INIT_STACK, \ 729 .sysenter_cs = __KERNEL_CS, \ 730 .io_bitmap_ptr = NULL, \ 731 .addr_limit = KERNEL_DS, \ 732 } 733 734 /* 735 * TOP_OF_KERNEL_STACK_PADDING reserves 8 bytes on top of the ring0 stack. 736 * This is necessary to guarantee that the entire "struct pt_regs" 737 * is accessible even if the CPU haven't stored the SS/ESP registers 738 * on the stack (interrupt gate does not save these registers 739 * when switching to the same priv ring). 740 * Therefore beware: accessing the ss/esp fields of the 741 * "struct pt_regs" is possible, but they may contain the 742 * completely wrong values. 743 */ 744 #define task_pt_regs(task) \ 745 ({ \ 746 unsigned long __ptr = (unsigned long)task_stack_page(task); \ 747 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ 748 ((struct pt_regs *)__ptr) - 1; \ 749 }) 750 751 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 752 753 #else 754 /* 755 * User space process size. 47bits minus one guard page. The guard 756 * page is necessary on Intel CPUs: if a SYSCALL instruction is at 757 * the highest possible canonical userspace address, then that 758 * syscall will enter the kernel with a non-canonical return 759 * address, and SYSRET will explode dangerously. We avoid this 760 * particular problem by preventing anything from being mapped 761 * at the maximum canonical address. 762 */ 763 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE) 764 765 /* This decides where the kernel will search for a free chunk of vm 766 * space during mmap's. 767 */ 768 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ 769 0xc0000000 : 0xFFFFe000) 770 771 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ 772 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 773 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ 774 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 775 776 #define STACK_TOP TASK_SIZE 777 #define STACK_TOP_MAX TASK_SIZE_MAX 778 779 #define INIT_THREAD { \ 780 .sp0 = TOP_OF_INIT_STACK, \ 781 .addr_limit = KERNEL_DS, \ 782 } 783 784 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) 785 extern unsigned long KSTK_ESP(struct task_struct *task); 786 787 #endif /* CONFIG_X86_64 */ 788 789 extern unsigned long thread_saved_pc(struct task_struct *tsk); 790 791 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 792 unsigned long new_sp); 793 794 /* 795 * This decides where the kernel will search for a free chunk of vm 796 * space during mmap's. 797 */ 798 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) 799 800 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 801 802 /* Get/set a process' ability to use the timestamp counter instruction */ 803 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 804 #define SET_TSC_CTL(val) set_tsc_mode((val)) 805 806 extern int get_tsc_mode(unsigned long adr); 807 extern int set_tsc_mode(unsigned int val); 808 809 /* Register/unregister a process' MPX related resource */ 810 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management() 811 #define MPX_DISABLE_MANAGEMENT() mpx_disable_management() 812 813 #ifdef CONFIG_X86_INTEL_MPX 814 extern int mpx_enable_management(void); 815 extern int mpx_disable_management(void); 816 #else 817 static inline int mpx_enable_management(void) 818 { 819 return -EINVAL; 820 } 821 static inline int mpx_disable_management(void) 822 { 823 return -EINVAL; 824 } 825 #endif /* CONFIG_X86_INTEL_MPX */ 826 827 extern u16 amd_get_nb_id(int cpu); 828 extern u32 amd_get_nodes_per_socket(void); 829 830 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves) 831 { 832 uint32_t base, eax, signature[3]; 833 834 for (base = 0x40000000; base < 0x40010000; base += 0x100) { 835 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); 836 837 if (!memcmp(sig, signature, 12) && 838 (leaves == 0 || ((eax - base) >= leaves))) 839 return base; 840 } 841 842 return 0; 843 } 844 845 extern unsigned long arch_align_stack(unsigned long sp); 846 extern void free_init_pages(char *what, unsigned long begin, unsigned long end); 847 848 void default_idle(void); 849 #ifdef CONFIG_XEN 850 bool xen_set_default_idle(void); 851 #else 852 #define xen_set_default_idle 0 853 #endif 854 855 void stop_this_cpu(void *dummy); 856 void df_debug(struct pt_regs *regs, long error_code); 857 #endif /* _ASM_X86_PROCESSOR_H */ 858