1 #ifndef _ASM_X86_PROCESSOR_H 2 #define _ASM_X86_PROCESSOR_H 3 4 #include <asm/processor-flags.h> 5 6 /* Forward declaration, a strange C thing */ 7 struct task_struct; 8 struct mm_struct; 9 10 #include <asm/vm86.h> 11 #include <asm/math_emu.h> 12 #include <asm/segment.h> 13 #include <asm/types.h> 14 #include <asm/sigcontext.h> 15 #include <asm/current.h> 16 #include <asm/cpufeature.h> 17 #include <asm/page.h> 18 #include <asm/pgtable_types.h> 19 #include <asm/percpu.h> 20 #include <asm/msr.h> 21 #include <asm/desc_defs.h> 22 #include <asm/nops.h> 23 #include <asm/special_insns.h> 24 25 #include <linux/personality.h> 26 #include <linux/cpumask.h> 27 #include <linux/cache.h> 28 #include <linux/threads.h> 29 #include <linux/math64.h> 30 #include <linux/err.h> 31 #include <linux/irqflags.h> 32 33 /* 34 * We handle most unaligned accesses in hardware. On the other hand 35 * unaligned DMA can be quite expensive on some Nehalem processors. 36 * 37 * Based on this we disable the IP header alignment in network drivers. 38 */ 39 #define NET_IP_ALIGN 0 40 41 #define HBP_NUM 4 42 /* 43 * Default implementation of macro that returns current 44 * instruction pointer ("program counter"). 45 */ 46 static inline void *current_text_addr(void) 47 { 48 void *pc; 49 50 asm volatile("mov $1f, %0; 1:":"=r" (pc)); 51 52 return pc; 53 } 54 55 #ifdef CONFIG_X86_VSMP 56 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 57 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 58 #else 59 # define ARCH_MIN_TASKALIGN 16 60 # define ARCH_MIN_MMSTRUCT_ALIGN 0 61 #endif 62 63 enum tlb_infos { 64 ENTRIES, 65 NR_INFO 66 }; 67 68 extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 69 extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 70 extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 71 extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 72 extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 73 extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 74 extern u16 __read_mostly tlb_lld_1g[NR_INFO]; 75 76 /* 77 * CPU type and hardware bug flags. Kept separately for each CPU. 78 * Members of this structure are referenced in head.S, so think twice 79 * before touching them. [mj] 80 */ 81 82 struct cpuinfo_x86 { 83 __u8 x86; /* CPU family */ 84 __u8 x86_vendor; /* CPU vendor */ 85 __u8 x86_model; 86 __u8 x86_mask; 87 #ifdef CONFIG_X86_32 88 char wp_works_ok; /* It doesn't on 386's */ 89 90 /* Problems on some 486Dx4's and old 386's: */ 91 char rfu; 92 char pad0; 93 char pad1; 94 #else 95 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 96 int x86_tlbsize; 97 #endif 98 __u8 x86_virt_bits; 99 __u8 x86_phys_bits; 100 /* CPUID returned core id bits: */ 101 __u8 x86_coreid_bits; 102 /* Max extended CPUID function supported: */ 103 __u32 extended_cpuid_level; 104 /* Maximum supported CPUID level, -1=no CPUID: */ 105 int cpuid_level; 106 __u32 x86_capability[NCAPINTS + NBUGINTS]; 107 char x86_vendor_id[16]; 108 char x86_model_id[64]; 109 /* in KB - valid for CPUS which support this call: */ 110 int x86_cache_size; 111 int x86_cache_alignment; /* In bytes */ 112 int x86_power; 113 unsigned long loops_per_jiffy; 114 /* cpuid returned max cores value: */ 115 u16 x86_max_cores; 116 u16 apicid; 117 u16 initial_apicid; 118 u16 x86_clflush_size; 119 /* number of cores as seen by the OS: */ 120 u16 booted_cores; 121 /* Physical processor id: */ 122 u16 phys_proc_id; 123 /* Core id: */ 124 u16 cpu_core_id; 125 /* Compute unit id */ 126 u8 compute_unit_id; 127 /* Index into per_cpu list: */ 128 u16 cpu_index; 129 u32 microcode; 130 } __attribute__((__aligned__(SMP_CACHE_BYTES))); 131 132 #define X86_VENDOR_INTEL 0 133 #define X86_VENDOR_CYRIX 1 134 #define X86_VENDOR_AMD 2 135 #define X86_VENDOR_UMC 3 136 #define X86_VENDOR_CENTAUR 5 137 #define X86_VENDOR_TRANSMETA 7 138 #define X86_VENDOR_NSC 8 139 #define X86_VENDOR_NUM 9 140 141 #define X86_VENDOR_UNKNOWN 0xff 142 143 /* 144 * capabilities of CPUs 145 */ 146 extern struct cpuinfo_x86 boot_cpu_data; 147 extern struct cpuinfo_x86 new_cpu_data; 148 149 extern struct tss_struct doublefault_tss; 150 extern __u32 cpu_caps_cleared[NCAPINTS]; 151 extern __u32 cpu_caps_set[NCAPINTS]; 152 153 #ifdef CONFIG_SMP 154 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 155 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 156 #else 157 #define cpu_info boot_cpu_data 158 #define cpu_data(cpu) boot_cpu_data 159 #endif 160 161 extern const struct seq_operations cpuinfo_op; 162 163 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 164 165 extern void cpu_detect(struct cpuinfo_x86 *c); 166 extern void fpu_detect(struct cpuinfo_x86 *c); 167 168 extern void early_cpu_init(void); 169 extern void identify_boot_cpu(void); 170 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 171 extern void print_cpu_info(struct cpuinfo_x86 *); 172 void print_cpu_msr(struct cpuinfo_x86 *); 173 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); 174 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); 175 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); 176 177 extern void detect_extended_topology(struct cpuinfo_x86 *c); 178 extern void detect_ht(struct cpuinfo_x86 *c); 179 180 #ifdef CONFIG_X86_32 181 extern int have_cpuid_p(void); 182 #else 183 static inline int have_cpuid_p(void) 184 { 185 return 1; 186 } 187 #endif 188 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 189 unsigned int *ecx, unsigned int *edx) 190 { 191 /* ecx is often an input as well as an output. */ 192 asm volatile("cpuid" 193 : "=a" (*eax), 194 "=b" (*ebx), 195 "=c" (*ecx), 196 "=d" (*edx) 197 : "0" (*eax), "2" (*ecx) 198 : "memory"); 199 } 200 201 static inline void load_cr3(pgd_t *pgdir) 202 { 203 write_cr3(__pa(pgdir)); 204 } 205 206 #ifdef CONFIG_X86_32 207 /* This is the TSS defined by the hardware. */ 208 struct x86_hw_tss { 209 unsigned short back_link, __blh; 210 unsigned long sp0; 211 unsigned short ss0, __ss0h; 212 unsigned long sp1; 213 /* ss1 caches MSR_IA32_SYSENTER_CS: */ 214 unsigned short ss1, __ss1h; 215 unsigned long sp2; 216 unsigned short ss2, __ss2h; 217 unsigned long __cr3; 218 unsigned long ip; 219 unsigned long flags; 220 unsigned long ax; 221 unsigned long cx; 222 unsigned long dx; 223 unsigned long bx; 224 unsigned long sp; 225 unsigned long bp; 226 unsigned long si; 227 unsigned long di; 228 unsigned short es, __esh; 229 unsigned short cs, __csh; 230 unsigned short ss, __ssh; 231 unsigned short ds, __dsh; 232 unsigned short fs, __fsh; 233 unsigned short gs, __gsh; 234 unsigned short ldt, __ldth; 235 unsigned short trace; 236 unsigned short io_bitmap_base; 237 238 } __attribute__((packed)); 239 #else 240 struct x86_hw_tss { 241 u32 reserved1; 242 u64 sp0; 243 u64 sp1; 244 u64 sp2; 245 u64 reserved2; 246 u64 ist[7]; 247 u32 reserved3; 248 u32 reserved4; 249 u16 reserved5; 250 u16 io_bitmap_base; 251 252 } __attribute__((packed)) ____cacheline_aligned; 253 #endif 254 255 /* 256 * IO-bitmap sizes: 257 */ 258 #define IO_BITMAP_BITS 65536 259 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) 260 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) 261 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) 262 #define INVALID_IO_BITMAP_OFFSET 0x8000 263 264 struct tss_struct { 265 /* 266 * The hardware state: 267 */ 268 struct x86_hw_tss x86_tss; 269 270 /* 271 * The extra 1 is there because the CPU will access an 272 * additional byte beyond the end of the IO permission 273 * bitmap. The extra byte must be all 1 bits, and must 274 * be within the limit. 275 */ 276 unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; 277 278 /* 279 * .. and then another 0x100 bytes for the emergency kernel stack: 280 */ 281 unsigned long stack[64]; 282 283 } ____cacheline_aligned; 284 285 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss); 286 287 /* 288 * Save the original ist values for checking stack pointers during debugging 289 */ 290 struct orig_ist { 291 unsigned long ist[7]; 292 }; 293 294 #define MXCSR_DEFAULT 0x1f80 295 296 struct i387_fsave_struct { 297 u32 cwd; /* FPU Control Word */ 298 u32 swd; /* FPU Status Word */ 299 u32 twd; /* FPU Tag Word */ 300 u32 fip; /* FPU IP Offset */ 301 u32 fcs; /* FPU IP Selector */ 302 u32 foo; /* FPU Operand Pointer Offset */ 303 u32 fos; /* FPU Operand Pointer Selector */ 304 305 /* 8*10 bytes for each FP-reg = 80 bytes: */ 306 u32 st_space[20]; 307 308 /* Software status information [not touched by FSAVE ]: */ 309 u32 status; 310 }; 311 312 struct i387_fxsave_struct { 313 u16 cwd; /* Control Word */ 314 u16 swd; /* Status Word */ 315 u16 twd; /* Tag Word */ 316 u16 fop; /* Last Instruction Opcode */ 317 union { 318 struct { 319 u64 rip; /* Instruction Pointer */ 320 u64 rdp; /* Data Pointer */ 321 }; 322 struct { 323 u32 fip; /* FPU IP Offset */ 324 u32 fcs; /* FPU IP Selector */ 325 u32 foo; /* FPU Operand Offset */ 326 u32 fos; /* FPU Operand Selector */ 327 }; 328 }; 329 u32 mxcsr; /* MXCSR Register State */ 330 u32 mxcsr_mask; /* MXCSR Mask */ 331 332 /* 8*16 bytes for each FP-reg = 128 bytes: */ 333 u32 st_space[32]; 334 335 /* 16*16 bytes for each XMM-reg = 256 bytes: */ 336 u32 xmm_space[64]; 337 338 u32 padding[12]; 339 340 union { 341 u32 padding1[12]; 342 u32 sw_reserved[12]; 343 }; 344 345 } __attribute__((aligned(16))); 346 347 struct i387_soft_struct { 348 u32 cwd; 349 u32 swd; 350 u32 twd; 351 u32 fip; 352 u32 fcs; 353 u32 foo; 354 u32 fos; 355 /* 8*10 bytes for each FP-reg = 80 bytes: */ 356 u32 st_space[20]; 357 u8 ftop; 358 u8 changed; 359 u8 lookahead; 360 u8 no_update; 361 u8 rm; 362 u8 alimit; 363 struct math_emu_info *info; 364 u32 entry_eip; 365 }; 366 367 struct ymmh_struct { 368 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */ 369 u32 ymmh_space[64]; 370 }; 371 372 /* We don't support LWP yet: */ 373 struct lwp_struct { 374 u8 reserved[128]; 375 }; 376 377 struct bndreg { 378 u64 lower_bound; 379 u64 upper_bound; 380 } __packed; 381 382 struct bndcsr { 383 u64 bndcfgu; 384 u64 bndstatus; 385 } __packed; 386 387 struct xsave_hdr_struct { 388 u64 xstate_bv; 389 u64 xcomp_bv; 390 u64 reserved[6]; 391 } __attribute__((packed)); 392 393 struct xsave_struct { 394 struct i387_fxsave_struct i387; 395 struct xsave_hdr_struct xsave_hdr; 396 struct ymmh_struct ymmh; 397 struct lwp_struct lwp; 398 struct bndreg bndreg[4]; 399 struct bndcsr bndcsr; 400 /* new processor state extensions will go here */ 401 } __attribute__ ((packed, aligned (64))); 402 403 union thread_xstate { 404 struct i387_fsave_struct fsave; 405 struct i387_fxsave_struct fxsave; 406 struct i387_soft_struct soft; 407 struct xsave_struct xsave; 408 }; 409 410 struct fpu { 411 unsigned int last_cpu; 412 unsigned int has_fpu; 413 union thread_xstate *state; 414 }; 415 416 #ifdef CONFIG_X86_64 417 DECLARE_PER_CPU(struct orig_ist, orig_ist); 418 419 union irq_stack_union { 420 char irq_stack[IRQ_STACK_SIZE]; 421 /* 422 * GCC hardcodes the stack canary as %gs:40. Since the 423 * irq_stack is the object at %gs:0, we reserve the bottom 424 * 48 bytes of the irq stack for the canary. 425 */ 426 struct { 427 char gs_base[40]; 428 unsigned long stack_canary; 429 }; 430 }; 431 432 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible; 433 DECLARE_INIT_PER_CPU(irq_stack_union); 434 435 DECLARE_PER_CPU(char *, irq_stack_ptr); 436 DECLARE_PER_CPU(unsigned int, irq_count); 437 extern asmlinkage void ignore_sysret(void); 438 #else /* X86_64 */ 439 #ifdef CONFIG_CC_STACKPROTECTOR 440 /* 441 * Make sure stack canary segment base is cached-aligned: 442 * "For Intel Atom processors, avoid non zero segment base address 443 * that is not aligned to cache line boundary at all cost." 444 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) 445 */ 446 struct stack_canary { 447 char __pad[20]; /* canary at %gs:20 */ 448 unsigned long canary; 449 }; 450 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 451 #endif 452 /* 453 * per-CPU IRQ handling stacks 454 */ 455 struct irq_stack { 456 u32 stack[THREAD_SIZE/sizeof(u32)]; 457 } __aligned(THREAD_SIZE); 458 459 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack); 460 DECLARE_PER_CPU(struct irq_stack *, softirq_stack); 461 #endif /* X86_64 */ 462 463 extern unsigned int xstate_size; 464 extern void free_thread_xstate(struct task_struct *); 465 extern struct kmem_cache *task_xstate_cachep; 466 467 struct perf_event; 468 469 struct thread_struct { 470 /* Cached TLS descriptors: */ 471 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 472 unsigned long sp0; 473 unsigned long sp; 474 #ifdef CONFIG_X86_32 475 unsigned long sysenter_cs; 476 #else 477 unsigned long usersp; /* Copy from PDA */ 478 unsigned short es; 479 unsigned short ds; 480 unsigned short fsindex; 481 unsigned short gsindex; 482 #endif 483 #ifdef CONFIG_X86_32 484 unsigned long ip; 485 #endif 486 #ifdef CONFIG_X86_64 487 unsigned long fs; 488 #endif 489 unsigned long gs; 490 /* Save middle states of ptrace breakpoints */ 491 struct perf_event *ptrace_bps[HBP_NUM]; 492 /* Debug status used for traps, single steps, etc... */ 493 unsigned long debugreg6; 494 /* Keep track of the exact dr7 value set by the user */ 495 unsigned long ptrace_dr7; 496 /* Fault info: */ 497 unsigned long cr2; 498 unsigned long trap_nr; 499 unsigned long error_code; 500 /* floating point and extended processor state */ 501 struct fpu fpu; 502 #ifdef CONFIG_X86_32 503 /* Virtual 86 mode info */ 504 struct vm86_struct __user *vm86_info; 505 unsigned long screen_bitmap; 506 unsigned long v86flags; 507 unsigned long v86mask; 508 unsigned long saved_sp0; 509 unsigned int saved_fs; 510 unsigned int saved_gs; 511 #endif 512 /* IO permissions: */ 513 unsigned long *io_bitmap_ptr; 514 unsigned long iopl; 515 /* Max allowed port in the bitmap, in bytes: */ 516 unsigned io_bitmap_max; 517 /* 518 * fpu_counter contains the number of consecutive context switches 519 * that the FPU is used. If this is over a threshold, the lazy fpu 520 * saving becomes unlazy to save the trap. This is an unsigned char 521 * so that after 256 times the counter wraps and the behavior turns 522 * lazy again; this to deal with bursty apps that only use FPU for 523 * a short time 524 */ 525 unsigned char fpu_counter; 526 }; 527 528 /* 529 * Set IOPL bits in EFLAGS from given mask 530 */ 531 static inline void native_set_iopl_mask(unsigned mask) 532 { 533 #ifdef CONFIG_X86_32 534 unsigned int reg; 535 536 asm volatile ("pushfl;" 537 "popl %0;" 538 "andl %1, %0;" 539 "orl %2, %0;" 540 "pushl %0;" 541 "popfl" 542 : "=&r" (reg) 543 : "i" (~X86_EFLAGS_IOPL), "r" (mask)); 544 #endif 545 } 546 547 static inline void 548 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread) 549 { 550 tss->x86_tss.sp0 = thread->sp0; 551 #ifdef CONFIG_X86_32 552 /* Only happens when SEP is enabled, no need to test "SEP"arately: */ 553 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { 554 tss->x86_tss.ss1 = thread->sysenter_cs; 555 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); 556 } 557 #endif 558 } 559 560 static inline void native_swapgs(void) 561 { 562 #ifdef CONFIG_X86_64 563 asm volatile("swapgs" ::: "memory"); 564 #endif 565 } 566 567 #ifdef CONFIG_PARAVIRT 568 #include <asm/paravirt.h> 569 #else 570 #define __cpuid native_cpuid 571 #define paravirt_enabled() 0 572 573 static inline void load_sp0(struct tss_struct *tss, 574 struct thread_struct *thread) 575 { 576 native_load_sp0(tss, thread); 577 } 578 579 #define set_iopl_mask native_set_iopl_mask 580 #endif /* CONFIG_PARAVIRT */ 581 582 /* 583 * Save the cr4 feature set we're using (ie 584 * Pentium 4MB enable and PPro Global page 585 * enable), so that any CPU's that boot up 586 * after us can get the correct flags. 587 */ 588 extern unsigned long mmu_cr4_features; 589 extern u32 *trampoline_cr4_features; 590 591 static inline void set_in_cr4(unsigned long mask) 592 { 593 unsigned long cr4; 594 595 mmu_cr4_features |= mask; 596 if (trampoline_cr4_features) 597 *trampoline_cr4_features = mmu_cr4_features; 598 cr4 = read_cr4(); 599 cr4 |= mask; 600 write_cr4(cr4); 601 } 602 603 static inline void clear_in_cr4(unsigned long mask) 604 { 605 unsigned long cr4; 606 607 mmu_cr4_features &= ~mask; 608 if (trampoline_cr4_features) 609 *trampoline_cr4_features = mmu_cr4_features; 610 cr4 = read_cr4(); 611 cr4 &= ~mask; 612 write_cr4(cr4); 613 } 614 615 typedef struct { 616 unsigned long seg; 617 } mm_segment_t; 618 619 620 /* Free all resources held by a thread. */ 621 extern void release_thread(struct task_struct *); 622 623 unsigned long get_wchan(struct task_struct *p); 624 625 /* 626 * Generic CPUID function 627 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 628 * resulting in stale register contents being returned. 629 */ 630 static inline void cpuid(unsigned int op, 631 unsigned int *eax, unsigned int *ebx, 632 unsigned int *ecx, unsigned int *edx) 633 { 634 *eax = op; 635 *ecx = 0; 636 __cpuid(eax, ebx, ecx, edx); 637 } 638 639 /* Some CPUID calls want 'count' to be placed in ecx */ 640 static inline void cpuid_count(unsigned int op, int count, 641 unsigned int *eax, unsigned int *ebx, 642 unsigned int *ecx, unsigned int *edx) 643 { 644 *eax = op; 645 *ecx = count; 646 __cpuid(eax, ebx, ecx, edx); 647 } 648 649 /* 650 * CPUID functions returning a single datum 651 */ 652 static inline unsigned int cpuid_eax(unsigned int op) 653 { 654 unsigned int eax, ebx, ecx, edx; 655 656 cpuid(op, &eax, &ebx, &ecx, &edx); 657 658 return eax; 659 } 660 661 static inline unsigned int cpuid_ebx(unsigned int op) 662 { 663 unsigned int eax, ebx, ecx, edx; 664 665 cpuid(op, &eax, &ebx, &ecx, &edx); 666 667 return ebx; 668 } 669 670 static inline unsigned int cpuid_ecx(unsigned int op) 671 { 672 unsigned int eax, ebx, ecx, edx; 673 674 cpuid(op, &eax, &ebx, &ecx, &edx); 675 676 return ecx; 677 } 678 679 static inline unsigned int cpuid_edx(unsigned int op) 680 { 681 unsigned int eax, ebx, ecx, edx; 682 683 cpuid(op, &eax, &ebx, &ecx, &edx); 684 685 return edx; 686 } 687 688 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 689 static inline void rep_nop(void) 690 { 691 asm volatile("rep; nop" ::: "memory"); 692 } 693 694 static inline void cpu_relax(void) 695 { 696 rep_nop(); 697 } 698 699 #define cpu_relax_lowlatency() cpu_relax() 700 701 /* Stop speculative execution and prefetching of modified code. */ 702 static inline void sync_core(void) 703 { 704 int tmp; 705 706 #ifdef CONFIG_M486 707 /* 708 * Do a CPUID if available, otherwise do a jump. The jump 709 * can conveniently enough be the jump around CPUID. 710 */ 711 asm volatile("cmpl %2,%1\n\t" 712 "jl 1f\n\t" 713 "cpuid\n" 714 "1:" 715 : "=a" (tmp) 716 : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1) 717 : "ebx", "ecx", "edx", "memory"); 718 #else 719 /* 720 * CPUID is a barrier to speculative execution. 721 * Prefetched instructions are automatically 722 * invalidated when modified. 723 */ 724 asm volatile("cpuid" 725 : "=a" (tmp) 726 : "0" (1) 727 : "ebx", "ecx", "edx", "memory"); 728 #endif 729 } 730 731 extern void select_idle_routine(const struct cpuinfo_x86 *c); 732 extern void init_amd_e400_c1e_mask(void); 733 734 extern unsigned long boot_option_idle_override; 735 extern bool amd_e400_c1e_detected; 736 737 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 738 IDLE_POLL}; 739 740 extern void enable_sep_cpu(void); 741 extern int sysenter_setup(void); 742 743 extern void early_trap_init(void); 744 void early_trap_pf_init(void); 745 746 /* Defined in head.S */ 747 extern struct desc_ptr early_gdt_descr; 748 749 extern void cpu_set_gdt(int); 750 extern void switch_to_new_gdt(int); 751 extern void load_percpu_segment(int); 752 extern void cpu_init(void); 753 754 static inline unsigned long get_debugctlmsr(void) 755 { 756 unsigned long debugctlmsr = 0; 757 758 #ifndef CONFIG_X86_DEBUGCTLMSR 759 if (boot_cpu_data.x86 < 6) 760 return 0; 761 #endif 762 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 763 764 return debugctlmsr; 765 } 766 767 static inline void update_debugctlmsr(unsigned long debugctlmsr) 768 { 769 #ifndef CONFIG_X86_DEBUGCTLMSR 770 if (boot_cpu_data.x86 < 6) 771 return; 772 #endif 773 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 774 } 775 776 extern void set_task_blockstep(struct task_struct *task, bool on); 777 778 /* 779 * from system description table in BIOS. Mostly for MCA use, but 780 * others may find it useful: 781 */ 782 extern unsigned int machine_id; 783 extern unsigned int machine_submodel_id; 784 extern unsigned int BIOS_revision; 785 786 /* Boot loader type from the setup header: */ 787 extern int bootloader_type; 788 extern int bootloader_version; 789 790 extern char ignore_fpu_irq; 791 792 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 793 #define ARCH_HAS_PREFETCHW 794 #define ARCH_HAS_SPINLOCK_PREFETCH 795 796 #ifdef CONFIG_X86_32 797 # define BASE_PREFETCH ASM_NOP4 798 # define ARCH_HAS_PREFETCH 799 #else 800 # define BASE_PREFETCH "prefetcht0 (%1)" 801 #endif 802 803 /* 804 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 805 * 806 * It's not worth to care about 3dnow prefetches for the K6 807 * because they are microcoded there and very slow. 808 */ 809 static inline void prefetch(const void *x) 810 { 811 alternative_input(BASE_PREFETCH, 812 "prefetchnta (%1)", 813 X86_FEATURE_XMM, 814 "r" (x)); 815 } 816 817 /* 818 * 3dnow prefetch to get an exclusive cache line. 819 * Useful for spinlocks to avoid one state transition in the 820 * cache coherency protocol: 821 */ 822 static inline void prefetchw(const void *x) 823 { 824 alternative_input(BASE_PREFETCH, 825 "prefetchw (%1)", 826 X86_FEATURE_3DNOW, 827 "r" (x)); 828 } 829 830 static inline void spin_lock_prefetch(const void *x) 831 { 832 prefetchw(x); 833 } 834 835 #ifdef CONFIG_X86_32 836 /* 837 * User space process size: 3GB (default). 838 */ 839 #define TASK_SIZE PAGE_OFFSET 840 #define TASK_SIZE_MAX TASK_SIZE 841 #define STACK_TOP TASK_SIZE 842 #define STACK_TOP_MAX STACK_TOP 843 844 #define INIT_THREAD { \ 845 .sp0 = sizeof(init_stack) + (long)&init_stack, \ 846 .vm86_info = NULL, \ 847 .sysenter_cs = __KERNEL_CS, \ 848 .io_bitmap_ptr = NULL, \ 849 } 850 851 /* 852 * Note that the .io_bitmap member must be extra-big. This is because 853 * the CPU will access an additional byte beyond the end of the IO 854 * permission bitmap. The extra byte must be all 1 bits, and must 855 * be within the limit. 856 */ 857 #define INIT_TSS { \ 858 .x86_tss = { \ 859 .sp0 = sizeof(init_stack) + (long)&init_stack, \ 860 .ss0 = __KERNEL_DS, \ 861 .ss1 = __KERNEL_CS, \ 862 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \ 863 }, \ 864 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \ 865 } 866 867 extern unsigned long thread_saved_pc(struct task_struct *tsk); 868 869 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long)) 870 #define KSTK_TOP(info) \ 871 ({ \ 872 unsigned long *__ptr = (unsigned long *)(info); \ 873 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \ 874 }) 875 876 /* 877 * The below -8 is to reserve 8 bytes on top of the ring0 stack. 878 * This is necessary to guarantee that the entire "struct pt_regs" 879 * is accessible even if the CPU haven't stored the SS/ESP registers 880 * on the stack (interrupt gate does not save these registers 881 * when switching to the same priv ring). 882 * Therefore beware: accessing the ss/esp fields of the 883 * "struct pt_regs" is possible, but they may contain the 884 * completely wrong values. 885 */ 886 #define task_pt_regs(task) \ 887 ({ \ 888 struct pt_regs *__regs__; \ 889 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \ 890 __regs__ - 1; \ 891 }) 892 893 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 894 895 #else 896 /* 897 * User space process size. 47bits minus one guard page. 898 */ 899 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE) 900 901 /* This decides where the kernel will search for a free chunk of vm 902 * space during mmap's. 903 */ 904 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ 905 0xc0000000 : 0xFFFFe000) 906 907 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ 908 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 909 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ 910 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 911 912 #define STACK_TOP TASK_SIZE 913 #define STACK_TOP_MAX TASK_SIZE_MAX 914 915 #define INIT_THREAD { \ 916 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ 917 } 918 919 #define INIT_TSS { \ 920 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ 921 } 922 923 /* 924 * Return saved PC of a blocked thread. 925 * What is this good for? it will be always the scheduler or ret_from_fork. 926 */ 927 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8)) 928 929 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) 930 extern unsigned long KSTK_ESP(struct task_struct *task); 931 932 /* 933 * User space RSP while inside the SYSCALL fast path 934 */ 935 DECLARE_PER_CPU(unsigned long, old_rsp); 936 937 #endif /* CONFIG_X86_64 */ 938 939 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 940 unsigned long new_sp); 941 942 /* 943 * This decides where the kernel will search for a free chunk of vm 944 * space during mmap's. 945 */ 946 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) 947 948 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 949 950 /* Get/set a process' ability to use the timestamp counter instruction */ 951 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 952 #define SET_TSC_CTL(val) set_tsc_mode((val)) 953 954 extern int get_tsc_mode(unsigned long adr); 955 extern int set_tsc_mode(unsigned int val); 956 957 extern u16 amd_get_nb_id(int cpu); 958 959 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves) 960 { 961 uint32_t base, eax, signature[3]; 962 963 for (base = 0x40000000; base < 0x40010000; base += 0x100) { 964 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); 965 966 if (!memcmp(sig, signature, 12) && 967 (leaves == 0 || ((eax - base) >= leaves))) 968 return base; 969 } 970 971 return 0; 972 } 973 974 extern unsigned long arch_align_stack(unsigned long sp); 975 extern void free_init_pages(char *what, unsigned long begin, unsigned long end); 976 977 void default_idle(void); 978 #ifdef CONFIG_XEN 979 bool xen_set_default_idle(void); 980 #else 981 #define xen_set_default_idle 0 982 #endif 983 984 void stop_this_cpu(void *dummy); 985 void df_debug(struct pt_regs *regs, long error_code); 986 #endif /* _ASM_X86_PROCESSOR_H */ 987