1 #ifndef _ASM_X86_PROCESSOR_H 2 #define _ASM_X86_PROCESSOR_H 3 4 #include <asm/processor-flags.h> 5 6 /* Forward declaration, a strange C thing */ 7 struct task_struct; 8 struct mm_struct; 9 struct vm86; 10 11 #include <asm/math_emu.h> 12 #include <asm/segment.h> 13 #include <asm/types.h> 14 #include <uapi/asm/sigcontext.h> 15 #include <asm/current.h> 16 #include <asm/cpufeatures.h> 17 #include <asm/page.h> 18 #include <asm/pgtable_types.h> 19 #include <asm/percpu.h> 20 #include <asm/msr.h> 21 #include <asm/desc_defs.h> 22 #include <asm/nops.h> 23 #include <asm/special_insns.h> 24 #include <asm/fpu/types.h> 25 26 #include <linux/personality.h> 27 #include <linux/cache.h> 28 #include <linux/threads.h> 29 #include <linux/math64.h> 30 #include <linux/err.h> 31 #include <linux/irqflags.h> 32 33 /* 34 * We handle most unaligned accesses in hardware. On the other hand 35 * unaligned DMA can be quite expensive on some Nehalem processors. 36 * 37 * Based on this we disable the IP header alignment in network drivers. 38 */ 39 #define NET_IP_ALIGN 0 40 41 #define HBP_NUM 4 42 /* 43 * Default implementation of macro that returns current 44 * instruction pointer ("program counter"). 45 */ 46 static inline void *current_text_addr(void) 47 { 48 void *pc; 49 50 asm volatile("mov $1f, %0; 1:":"=r" (pc)); 51 52 return pc; 53 } 54 55 /* 56 * These alignment constraints are for performance in the vSMP case, 57 * but in the task_struct case we must also meet hardware imposed 58 * alignment requirements of the FPU state: 59 */ 60 #ifdef CONFIG_X86_VSMP 61 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 62 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 63 #else 64 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state) 65 # define ARCH_MIN_MMSTRUCT_ALIGN 0 66 #endif 67 68 enum tlb_infos { 69 ENTRIES, 70 NR_INFO 71 }; 72 73 extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 74 extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 75 extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 76 extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 77 extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 78 extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 79 extern u16 __read_mostly tlb_lld_1g[NR_INFO]; 80 81 /* 82 * CPU type and hardware bug flags. Kept separately for each CPU. 83 * Members of this structure are referenced in head.S, so think twice 84 * before touching them. [mj] 85 */ 86 87 struct cpuinfo_x86 { 88 __u8 x86; /* CPU family */ 89 __u8 x86_vendor; /* CPU vendor */ 90 __u8 x86_model; 91 __u8 x86_mask; 92 #ifdef CONFIG_X86_32 93 char wp_works_ok; /* It doesn't on 386's */ 94 95 /* Problems on some 486Dx4's and old 386's: */ 96 char rfu; 97 char pad0; 98 char pad1; 99 #else 100 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 101 int x86_tlbsize; 102 #endif 103 __u8 x86_virt_bits; 104 __u8 x86_phys_bits; 105 /* CPUID returned core id bits: */ 106 __u8 x86_coreid_bits; 107 /* Max extended CPUID function supported: */ 108 __u32 extended_cpuid_level; 109 /* Maximum supported CPUID level, -1=no CPUID: */ 110 int cpuid_level; 111 __u32 x86_capability[NCAPINTS + NBUGINTS]; 112 char x86_vendor_id[16]; 113 char x86_model_id[64]; 114 /* in KB - valid for CPUS which support this call: */ 115 int x86_cache_size; 116 int x86_cache_alignment; /* In bytes */ 117 /* Cache QoS architectural values: */ 118 int x86_cache_max_rmid; /* max index */ 119 int x86_cache_occ_scale; /* scale to bytes */ 120 int x86_power; 121 unsigned long loops_per_jiffy; 122 /* cpuid returned max cores value: */ 123 u16 x86_max_cores; 124 u16 apicid; 125 u16 initial_apicid; 126 u16 x86_clflush_size; 127 /* number of cores as seen by the OS: */ 128 u16 booted_cores; 129 /* Physical processor id: */ 130 u16 phys_proc_id; 131 /* Logical processor id: */ 132 u16 logical_proc_id; 133 /* Core id: */ 134 u16 cpu_core_id; 135 /* Index into per_cpu list: */ 136 u16 cpu_index; 137 u32 microcode; 138 }; 139 140 struct cpuid_regs { 141 u32 eax, ebx, ecx, edx; 142 }; 143 144 enum cpuid_regs_idx { 145 CPUID_EAX = 0, 146 CPUID_EBX, 147 CPUID_ECX, 148 CPUID_EDX, 149 }; 150 151 #define X86_VENDOR_INTEL 0 152 #define X86_VENDOR_CYRIX 1 153 #define X86_VENDOR_AMD 2 154 #define X86_VENDOR_UMC 3 155 #define X86_VENDOR_CENTAUR 5 156 #define X86_VENDOR_TRANSMETA 7 157 #define X86_VENDOR_NSC 8 158 #define X86_VENDOR_NUM 9 159 160 #define X86_VENDOR_UNKNOWN 0xff 161 162 /* 163 * capabilities of CPUs 164 */ 165 extern struct cpuinfo_x86 boot_cpu_data; 166 extern struct cpuinfo_x86 new_cpu_data; 167 168 extern struct tss_struct doublefault_tss; 169 extern __u32 cpu_caps_cleared[NCAPINTS]; 170 extern __u32 cpu_caps_set[NCAPINTS]; 171 172 #ifdef CONFIG_SMP 173 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 174 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 175 #else 176 #define cpu_info boot_cpu_data 177 #define cpu_data(cpu) boot_cpu_data 178 #endif 179 180 extern const struct seq_operations cpuinfo_op; 181 182 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 183 184 extern void cpu_detect(struct cpuinfo_x86 *c); 185 186 extern void early_cpu_init(void); 187 extern void identify_boot_cpu(void); 188 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 189 extern void print_cpu_info(struct cpuinfo_x86 *); 190 void print_cpu_msr(struct cpuinfo_x86 *); 191 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); 192 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); 193 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); 194 195 extern void detect_extended_topology(struct cpuinfo_x86 *c); 196 extern void detect_ht(struct cpuinfo_x86 *c); 197 198 #ifdef CONFIG_X86_32 199 extern int have_cpuid_p(void); 200 #else 201 static inline int have_cpuid_p(void) 202 { 203 return 1; 204 } 205 #endif 206 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 207 unsigned int *ecx, unsigned int *edx) 208 { 209 /* ecx is often an input as well as an output. */ 210 asm volatile("cpuid" 211 : "=a" (*eax), 212 "=b" (*ebx), 213 "=c" (*ecx), 214 "=d" (*edx) 215 : "0" (*eax), "2" (*ecx) 216 : "memory"); 217 } 218 219 static inline void load_cr3(pgd_t *pgdir) 220 { 221 write_cr3(__pa(pgdir)); 222 } 223 224 #ifdef CONFIG_X86_32 225 /* This is the TSS defined by the hardware. */ 226 struct x86_hw_tss { 227 unsigned short back_link, __blh; 228 unsigned long sp0; 229 unsigned short ss0, __ss0h; 230 unsigned long sp1; 231 232 /* 233 * We don't use ring 1, so ss1 is a convenient scratch space in 234 * the same cacheline as sp0. We use ss1 to cache the value in 235 * MSR_IA32_SYSENTER_CS. When we context switch 236 * MSR_IA32_SYSENTER_CS, we first check if the new value being 237 * written matches ss1, and, if it's not, then we wrmsr the new 238 * value and update ss1. 239 * 240 * The only reason we context switch MSR_IA32_SYSENTER_CS is 241 * that we set it to zero in vm86 tasks to avoid corrupting the 242 * stack if we were to go through the sysenter path from vm86 243 * mode. 244 */ 245 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ 246 247 unsigned short __ss1h; 248 unsigned long sp2; 249 unsigned short ss2, __ss2h; 250 unsigned long __cr3; 251 unsigned long ip; 252 unsigned long flags; 253 unsigned long ax; 254 unsigned long cx; 255 unsigned long dx; 256 unsigned long bx; 257 unsigned long sp; 258 unsigned long bp; 259 unsigned long si; 260 unsigned long di; 261 unsigned short es, __esh; 262 unsigned short cs, __csh; 263 unsigned short ss, __ssh; 264 unsigned short ds, __dsh; 265 unsigned short fs, __fsh; 266 unsigned short gs, __gsh; 267 unsigned short ldt, __ldth; 268 unsigned short trace; 269 unsigned short io_bitmap_base; 270 271 } __attribute__((packed)); 272 #else 273 struct x86_hw_tss { 274 u32 reserved1; 275 u64 sp0; 276 u64 sp1; 277 u64 sp2; 278 u64 reserved2; 279 u64 ist[7]; 280 u32 reserved3; 281 u32 reserved4; 282 u16 reserved5; 283 u16 io_bitmap_base; 284 285 } __attribute__((packed)) ____cacheline_aligned; 286 #endif 287 288 /* 289 * IO-bitmap sizes: 290 */ 291 #define IO_BITMAP_BITS 65536 292 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) 293 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) 294 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) 295 #define INVALID_IO_BITMAP_OFFSET 0x8000 296 297 struct tss_struct { 298 /* 299 * The hardware state: 300 */ 301 struct x86_hw_tss x86_tss; 302 303 /* 304 * The extra 1 is there because the CPU will access an 305 * additional byte beyond the end of the IO permission 306 * bitmap. The extra byte must be all 1 bits, and must 307 * be within the limit. 308 */ 309 unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; 310 311 #ifdef CONFIG_X86_32 312 /* 313 * Space for the temporary SYSENTER stack. 314 */ 315 unsigned long SYSENTER_stack_canary; 316 unsigned long SYSENTER_stack[64]; 317 #endif 318 319 } ____cacheline_aligned; 320 321 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss); 322 323 #ifdef CONFIG_X86_32 324 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack); 325 #endif 326 327 /* 328 * Save the original ist values for checking stack pointers during debugging 329 */ 330 struct orig_ist { 331 unsigned long ist[7]; 332 }; 333 334 #ifdef CONFIG_X86_64 335 DECLARE_PER_CPU(struct orig_ist, orig_ist); 336 337 union irq_stack_union { 338 char irq_stack[IRQ_STACK_SIZE]; 339 /* 340 * GCC hardcodes the stack canary as %gs:40. Since the 341 * irq_stack is the object at %gs:0, we reserve the bottom 342 * 48 bytes of the irq stack for the canary. 343 */ 344 struct { 345 char gs_base[40]; 346 unsigned long stack_canary; 347 }; 348 }; 349 350 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible; 351 DECLARE_INIT_PER_CPU(irq_stack_union); 352 353 DECLARE_PER_CPU(char *, irq_stack_ptr); 354 DECLARE_PER_CPU(unsigned int, irq_count); 355 extern asmlinkage void ignore_sysret(void); 356 #else /* X86_64 */ 357 #ifdef CONFIG_CC_STACKPROTECTOR 358 /* 359 * Make sure stack canary segment base is cached-aligned: 360 * "For Intel Atom processors, avoid non zero segment base address 361 * that is not aligned to cache line boundary at all cost." 362 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) 363 */ 364 struct stack_canary { 365 char __pad[20]; /* canary at %gs:20 */ 366 unsigned long canary; 367 }; 368 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 369 #endif 370 /* 371 * per-CPU IRQ handling stacks 372 */ 373 struct irq_stack { 374 u32 stack[THREAD_SIZE/sizeof(u32)]; 375 } __aligned(THREAD_SIZE); 376 377 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack); 378 DECLARE_PER_CPU(struct irq_stack *, softirq_stack); 379 #endif /* X86_64 */ 380 381 extern unsigned int fpu_kernel_xstate_size; 382 extern unsigned int fpu_user_xstate_size; 383 384 struct perf_event; 385 386 typedef struct { 387 unsigned long seg; 388 } mm_segment_t; 389 390 struct thread_struct { 391 /* Cached TLS descriptors: */ 392 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 393 unsigned long sp0; 394 unsigned long sp; 395 #ifdef CONFIG_X86_32 396 unsigned long sysenter_cs; 397 #else 398 unsigned short es; 399 unsigned short ds; 400 unsigned short fsindex; 401 unsigned short gsindex; 402 #endif 403 404 u32 status; /* thread synchronous flags */ 405 406 #ifdef CONFIG_X86_64 407 unsigned long fsbase; 408 unsigned long gsbase; 409 #else 410 /* 411 * XXX: this could presumably be unsigned short. Alternatively, 412 * 32-bit kernels could be taught to use fsindex instead. 413 */ 414 unsigned long fs; 415 unsigned long gs; 416 #endif 417 418 /* Save middle states of ptrace breakpoints */ 419 struct perf_event *ptrace_bps[HBP_NUM]; 420 /* Debug status used for traps, single steps, etc... */ 421 unsigned long debugreg6; 422 /* Keep track of the exact dr7 value set by the user */ 423 unsigned long ptrace_dr7; 424 /* Fault info: */ 425 unsigned long cr2; 426 unsigned long trap_nr; 427 unsigned long error_code; 428 #ifdef CONFIG_VM86 429 /* Virtual 86 mode info */ 430 struct vm86 *vm86; 431 #endif 432 /* IO permissions: */ 433 unsigned long *io_bitmap_ptr; 434 unsigned long iopl; 435 /* Max allowed port in the bitmap, in bytes: */ 436 unsigned io_bitmap_max; 437 438 mm_segment_t addr_limit; 439 440 unsigned int sig_on_uaccess_err:1; 441 unsigned int uaccess_err:1; /* uaccess failed */ 442 443 /* Floating point and extended processor state */ 444 struct fpu fpu; 445 /* 446 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at 447 * the end. 448 */ 449 }; 450 451 /* 452 * Thread-synchronous status. 453 * 454 * This is different from the flags in that nobody else 455 * ever touches our thread-synchronous status, so we don't 456 * have to worry about atomic accesses. 457 */ 458 #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/ 459 460 /* 461 * Set IOPL bits in EFLAGS from given mask 462 */ 463 static inline void native_set_iopl_mask(unsigned mask) 464 { 465 #ifdef CONFIG_X86_32 466 unsigned int reg; 467 468 asm volatile ("pushfl;" 469 "popl %0;" 470 "andl %1, %0;" 471 "orl %2, %0;" 472 "pushl %0;" 473 "popfl" 474 : "=&r" (reg) 475 : "i" (~X86_EFLAGS_IOPL), "r" (mask)); 476 #endif 477 } 478 479 static inline void 480 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread) 481 { 482 tss->x86_tss.sp0 = thread->sp0; 483 #ifdef CONFIG_X86_32 484 /* Only happens when SEP is enabled, no need to test "SEP"arately: */ 485 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { 486 tss->x86_tss.ss1 = thread->sysenter_cs; 487 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); 488 } 489 #endif 490 } 491 492 static inline void native_swapgs(void) 493 { 494 #ifdef CONFIG_X86_64 495 asm volatile("swapgs" ::: "memory"); 496 #endif 497 } 498 499 static inline unsigned long current_top_of_stack(void) 500 { 501 #ifdef CONFIG_X86_64 502 return this_cpu_read_stable(cpu_tss.x86_tss.sp0); 503 #else 504 /* sp0 on x86_32 is special in and around vm86 mode. */ 505 return this_cpu_read_stable(cpu_current_top_of_stack); 506 #endif 507 } 508 509 #ifdef CONFIG_PARAVIRT 510 #include <asm/paravirt.h> 511 #else 512 #define __cpuid native_cpuid 513 514 static inline void load_sp0(struct tss_struct *tss, 515 struct thread_struct *thread) 516 { 517 native_load_sp0(tss, thread); 518 } 519 520 #define set_iopl_mask native_set_iopl_mask 521 #endif /* CONFIG_PARAVIRT */ 522 523 /* Free all resources held by a thread. */ 524 extern void release_thread(struct task_struct *); 525 526 unsigned long get_wchan(struct task_struct *p); 527 528 /* 529 * Generic CPUID function 530 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 531 * resulting in stale register contents being returned. 532 */ 533 static inline void cpuid(unsigned int op, 534 unsigned int *eax, unsigned int *ebx, 535 unsigned int *ecx, unsigned int *edx) 536 { 537 *eax = op; 538 *ecx = 0; 539 __cpuid(eax, ebx, ecx, edx); 540 } 541 542 /* Some CPUID calls want 'count' to be placed in ecx */ 543 static inline void cpuid_count(unsigned int op, int count, 544 unsigned int *eax, unsigned int *ebx, 545 unsigned int *ecx, unsigned int *edx) 546 { 547 *eax = op; 548 *ecx = count; 549 __cpuid(eax, ebx, ecx, edx); 550 } 551 552 /* 553 * CPUID functions returning a single datum 554 */ 555 static inline unsigned int cpuid_eax(unsigned int op) 556 { 557 unsigned int eax, ebx, ecx, edx; 558 559 cpuid(op, &eax, &ebx, &ecx, &edx); 560 561 return eax; 562 } 563 564 static inline unsigned int cpuid_ebx(unsigned int op) 565 { 566 unsigned int eax, ebx, ecx, edx; 567 568 cpuid(op, &eax, &ebx, &ecx, &edx); 569 570 return ebx; 571 } 572 573 static inline unsigned int cpuid_ecx(unsigned int op) 574 { 575 unsigned int eax, ebx, ecx, edx; 576 577 cpuid(op, &eax, &ebx, &ecx, &edx); 578 579 return ecx; 580 } 581 582 static inline unsigned int cpuid_edx(unsigned int op) 583 { 584 unsigned int eax, ebx, ecx, edx; 585 586 cpuid(op, &eax, &ebx, &ecx, &edx); 587 588 return edx; 589 } 590 591 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 592 static __always_inline void rep_nop(void) 593 { 594 asm volatile("rep; nop" ::: "memory"); 595 } 596 597 static __always_inline void cpu_relax(void) 598 { 599 rep_nop(); 600 } 601 602 #define cpu_relax_lowlatency() cpu_relax() 603 604 /* Stop speculative execution and prefetching of modified code. */ 605 static inline void sync_core(void) 606 { 607 int tmp; 608 609 #ifdef CONFIG_M486 610 /* 611 * Do a CPUID if available, otherwise do a jump. The jump 612 * can conveniently enough be the jump around CPUID. 613 */ 614 asm volatile("cmpl %2,%1\n\t" 615 "jl 1f\n\t" 616 "cpuid\n" 617 "1:" 618 : "=a" (tmp) 619 : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1) 620 : "ebx", "ecx", "edx", "memory"); 621 #else 622 /* 623 * CPUID is a barrier to speculative execution. 624 * Prefetched instructions are automatically 625 * invalidated when modified. 626 */ 627 asm volatile("cpuid" 628 : "=a" (tmp) 629 : "0" (1) 630 : "ebx", "ecx", "edx", "memory"); 631 #endif 632 } 633 634 extern void select_idle_routine(const struct cpuinfo_x86 *c); 635 extern void init_amd_e400_c1e_mask(void); 636 637 extern unsigned long boot_option_idle_override; 638 extern bool amd_e400_c1e_detected; 639 640 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 641 IDLE_POLL}; 642 643 extern void enable_sep_cpu(void); 644 extern int sysenter_setup(void); 645 646 extern void early_trap_init(void); 647 void early_trap_pf_init(void); 648 649 /* Defined in head.S */ 650 extern struct desc_ptr early_gdt_descr; 651 652 extern void cpu_set_gdt(int); 653 extern void switch_to_new_gdt(int); 654 extern void load_percpu_segment(int); 655 extern void cpu_init(void); 656 657 static inline unsigned long get_debugctlmsr(void) 658 { 659 unsigned long debugctlmsr = 0; 660 661 #ifndef CONFIG_X86_DEBUGCTLMSR 662 if (boot_cpu_data.x86 < 6) 663 return 0; 664 #endif 665 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 666 667 return debugctlmsr; 668 } 669 670 static inline void update_debugctlmsr(unsigned long debugctlmsr) 671 { 672 #ifndef CONFIG_X86_DEBUGCTLMSR 673 if (boot_cpu_data.x86 < 6) 674 return; 675 #endif 676 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 677 } 678 679 extern void set_task_blockstep(struct task_struct *task, bool on); 680 681 /* Boot loader type from the setup header: */ 682 extern int bootloader_type; 683 extern int bootloader_version; 684 685 extern char ignore_fpu_irq; 686 687 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 688 #define ARCH_HAS_PREFETCHW 689 #define ARCH_HAS_SPINLOCK_PREFETCH 690 691 #ifdef CONFIG_X86_32 692 # define BASE_PREFETCH "" 693 # define ARCH_HAS_PREFETCH 694 #else 695 # define BASE_PREFETCH "prefetcht0 %P1" 696 #endif 697 698 /* 699 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 700 * 701 * It's not worth to care about 3dnow prefetches for the K6 702 * because they are microcoded there and very slow. 703 */ 704 static inline void prefetch(const void *x) 705 { 706 alternative_input(BASE_PREFETCH, "prefetchnta %P1", 707 X86_FEATURE_XMM, 708 "m" (*(const char *)x)); 709 } 710 711 /* 712 * 3dnow prefetch to get an exclusive cache line. 713 * Useful for spinlocks to avoid one state transition in the 714 * cache coherency protocol: 715 */ 716 static inline void prefetchw(const void *x) 717 { 718 alternative_input(BASE_PREFETCH, "prefetchw %P1", 719 X86_FEATURE_3DNOWPREFETCH, 720 "m" (*(const char *)x)); 721 } 722 723 static inline void spin_lock_prefetch(const void *x) 724 { 725 prefetchw(x); 726 } 727 728 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ 729 TOP_OF_KERNEL_STACK_PADDING) 730 731 #ifdef CONFIG_X86_32 732 /* 733 * User space process size: 3GB (default). 734 */ 735 #define TASK_SIZE PAGE_OFFSET 736 #define TASK_SIZE_MAX TASK_SIZE 737 #define STACK_TOP TASK_SIZE 738 #define STACK_TOP_MAX STACK_TOP 739 740 #define INIT_THREAD { \ 741 .sp0 = TOP_OF_INIT_STACK, \ 742 .sysenter_cs = __KERNEL_CS, \ 743 .io_bitmap_ptr = NULL, \ 744 .addr_limit = KERNEL_DS, \ 745 } 746 747 /* 748 * TOP_OF_KERNEL_STACK_PADDING reserves 8 bytes on top of the ring0 stack. 749 * This is necessary to guarantee that the entire "struct pt_regs" 750 * is accessible even if the CPU haven't stored the SS/ESP registers 751 * on the stack (interrupt gate does not save these registers 752 * when switching to the same priv ring). 753 * Therefore beware: accessing the ss/esp fields of the 754 * "struct pt_regs" is possible, but they may contain the 755 * completely wrong values. 756 */ 757 #define task_pt_regs(task) \ 758 ({ \ 759 unsigned long __ptr = (unsigned long)task_stack_page(task); \ 760 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ 761 ((struct pt_regs *)__ptr) - 1; \ 762 }) 763 764 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 765 766 #else 767 /* 768 * User space process size. 47bits minus one guard page. The guard 769 * page is necessary on Intel CPUs: if a SYSCALL instruction is at 770 * the highest possible canonical userspace address, then that 771 * syscall will enter the kernel with a non-canonical return 772 * address, and SYSRET will explode dangerously. We avoid this 773 * particular problem by preventing anything from being mapped 774 * at the maximum canonical address. 775 */ 776 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE) 777 778 /* This decides where the kernel will search for a free chunk of vm 779 * space during mmap's. 780 */ 781 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ 782 0xc0000000 : 0xFFFFe000) 783 784 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ 785 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 786 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ 787 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 788 789 #define STACK_TOP TASK_SIZE 790 #define STACK_TOP_MAX TASK_SIZE_MAX 791 792 #define INIT_THREAD { \ 793 .sp0 = TOP_OF_INIT_STACK, \ 794 .addr_limit = KERNEL_DS, \ 795 } 796 797 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) 798 extern unsigned long KSTK_ESP(struct task_struct *task); 799 800 #endif /* CONFIG_X86_64 */ 801 802 extern unsigned long thread_saved_pc(struct task_struct *tsk); 803 804 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 805 unsigned long new_sp); 806 807 /* 808 * This decides where the kernel will search for a free chunk of vm 809 * space during mmap's. 810 */ 811 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) 812 813 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 814 815 /* Get/set a process' ability to use the timestamp counter instruction */ 816 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 817 #define SET_TSC_CTL(val) set_tsc_mode((val)) 818 819 extern int get_tsc_mode(unsigned long adr); 820 extern int set_tsc_mode(unsigned int val); 821 822 /* Register/unregister a process' MPX related resource */ 823 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management() 824 #define MPX_DISABLE_MANAGEMENT() mpx_disable_management() 825 826 #ifdef CONFIG_X86_INTEL_MPX 827 extern int mpx_enable_management(void); 828 extern int mpx_disable_management(void); 829 #else 830 static inline int mpx_enable_management(void) 831 { 832 return -EINVAL; 833 } 834 static inline int mpx_disable_management(void) 835 { 836 return -EINVAL; 837 } 838 #endif /* CONFIG_X86_INTEL_MPX */ 839 840 extern u16 amd_get_nb_id(int cpu); 841 extern u32 amd_get_nodes_per_socket(void); 842 843 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves) 844 { 845 uint32_t base, eax, signature[3]; 846 847 for (base = 0x40000000; base < 0x40010000; base += 0x100) { 848 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); 849 850 if (!memcmp(sig, signature, 12) && 851 (leaves == 0 || ((eax - base) >= leaves))) 852 return base; 853 } 854 855 return 0; 856 } 857 858 extern unsigned long arch_align_stack(unsigned long sp); 859 extern void free_init_pages(char *what, unsigned long begin, unsigned long end); 860 861 void default_idle(void); 862 #ifdef CONFIG_XEN 863 bool xen_set_default_idle(void); 864 #else 865 #define xen_set_default_idle 0 866 #endif 867 868 void stop_this_cpu(void *dummy); 869 void df_debug(struct pt_regs *regs, long error_code); 870 #endif /* _ASM_X86_PROCESSOR_H */ 871