1 #ifndef _ASM_X86_PROCESSOR_H 2 #define _ASM_X86_PROCESSOR_H 3 4 #include <asm/processor-flags.h> 5 6 /* Forward declaration, a strange C thing */ 7 struct task_struct; 8 struct mm_struct; 9 10 #include <asm/vm86.h> 11 #include <asm/math_emu.h> 12 #include <asm/segment.h> 13 #include <asm/types.h> 14 #include <asm/sigcontext.h> 15 #include <asm/current.h> 16 #include <asm/cpufeature.h> 17 #include <asm/page.h> 18 #include <asm/pgtable_types.h> 19 #include <asm/percpu.h> 20 #include <asm/msr.h> 21 #include <asm/desc_defs.h> 22 #include <asm/nops.h> 23 #include <asm/special_insns.h> 24 25 #include <linux/personality.h> 26 #include <linux/cpumask.h> 27 #include <linux/cache.h> 28 #include <linux/threads.h> 29 #include <linux/math64.h> 30 #include <linux/init.h> 31 #include <linux/err.h> 32 #include <linux/irqflags.h> 33 34 /* 35 * We handle most unaligned accesses in hardware. On the other hand 36 * unaligned DMA can be quite expensive on some Nehalem processors. 37 * 38 * Based on this we disable the IP header alignment in network drivers. 39 */ 40 #define NET_IP_ALIGN 0 41 42 #define HBP_NUM 4 43 /* 44 * Default implementation of macro that returns current 45 * instruction pointer ("program counter"). 46 */ 47 static inline void *current_text_addr(void) 48 { 49 void *pc; 50 51 asm volatile("mov $1f, %0; 1:":"=r" (pc)); 52 53 return pc; 54 } 55 56 #ifdef CONFIG_X86_VSMP 57 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 58 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 59 #else 60 # define ARCH_MIN_TASKALIGN 16 61 # define ARCH_MIN_MMSTRUCT_ALIGN 0 62 #endif 63 64 enum tlb_infos { 65 ENTRIES, 66 NR_INFO 67 }; 68 69 extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 70 extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 71 extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 72 extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 73 extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 74 extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 75 extern s8 __read_mostly tlb_flushall_shift; 76 77 /* 78 * CPU type and hardware bug flags. Kept separately for each CPU. 79 * Members of this structure are referenced in head.S, so think twice 80 * before touching them. [mj] 81 */ 82 83 struct cpuinfo_x86 { 84 __u8 x86; /* CPU family */ 85 __u8 x86_vendor; /* CPU vendor */ 86 __u8 x86_model; 87 __u8 x86_mask; 88 #ifdef CONFIG_X86_32 89 char wp_works_ok; /* It doesn't on 386's */ 90 91 /* Problems on some 486Dx4's and old 386's: */ 92 char hard_math; 93 char rfu; 94 char pad0; 95 #else 96 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 97 int x86_tlbsize; 98 #endif 99 __u8 x86_virt_bits; 100 __u8 x86_phys_bits; 101 /* CPUID returned core id bits: */ 102 __u8 x86_coreid_bits; 103 /* Max extended CPUID function supported: */ 104 __u32 extended_cpuid_level; 105 /* Maximum supported CPUID level, -1=no CPUID: */ 106 int cpuid_level; 107 __u32 x86_capability[NCAPINTS + NBUGINTS]; 108 char x86_vendor_id[16]; 109 char x86_model_id[64]; 110 /* in KB - valid for CPUS which support this call: */ 111 int x86_cache_size; 112 int x86_cache_alignment; /* In bytes */ 113 int x86_power; 114 unsigned long loops_per_jiffy; 115 /* cpuid returned max cores value: */ 116 u16 x86_max_cores; 117 u16 apicid; 118 u16 initial_apicid; 119 u16 x86_clflush_size; 120 /* number of cores as seen by the OS: */ 121 u16 booted_cores; 122 /* Physical processor id: */ 123 u16 phys_proc_id; 124 /* Core id: */ 125 u16 cpu_core_id; 126 /* Compute unit id */ 127 u8 compute_unit_id; 128 /* Index into per_cpu list: */ 129 u16 cpu_index; 130 u32 microcode; 131 } __attribute__((__aligned__(SMP_CACHE_BYTES))); 132 133 #define X86_VENDOR_INTEL 0 134 #define X86_VENDOR_CYRIX 1 135 #define X86_VENDOR_AMD 2 136 #define X86_VENDOR_UMC 3 137 #define X86_VENDOR_CENTAUR 5 138 #define X86_VENDOR_TRANSMETA 7 139 #define X86_VENDOR_NSC 8 140 #define X86_VENDOR_NUM 9 141 142 #define X86_VENDOR_UNKNOWN 0xff 143 144 /* 145 * capabilities of CPUs 146 */ 147 extern struct cpuinfo_x86 boot_cpu_data; 148 extern struct cpuinfo_x86 new_cpu_data; 149 150 extern struct tss_struct doublefault_tss; 151 extern __u32 cpu_caps_cleared[NCAPINTS]; 152 extern __u32 cpu_caps_set[NCAPINTS]; 153 154 #ifdef CONFIG_SMP 155 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 156 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 157 #else 158 #define cpu_info boot_cpu_data 159 #define cpu_data(cpu) boot_cpu_data 160 #endif 161 162 extern const struct seq_operations cpuinfo_op; 163 164 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 165 166 extern void cpu_detect(struct cpuinfo_x86 *c); 167 168 extern void early_cpu_init(void); 169 extern void identify_boot_cpu(void); 170 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 171 extern void print_cpu_info(struct cpuinfo_x86 *); 172 void print_cpu_msr(struct cpuinfo_x86 *); 173 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); 174 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); 175 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); 176 177 extern void detect_extended_topology(struct cpuinfo_x86 *c); 178 extern void detect_ht(struct cpuinfo_x86 *c); 179 180 #ifdef CONFIG_X86_32 181 extern int have_cpuid_p(void); 182 #else 183 static inline int have_cpuid_p(void) 184 { 185 return 1; 186 } 187 #endif 188 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 189 unsigned int *ecx, unsigned int *edx) 190 { 191 /* ecx is often an input as well as an output. */ 192 asm volatile("cpuid" 193 : "=a" (*eax), 194 "=b" (*ebx), 195 "=c" (*ecx), 196 "=d" (*edx) 197 : "0" (*eax), "2" (*ecx) 198 : "memory"); 199 } 200 201 static inline void load_cr3(pgd_t *pgdir) 202 { 203 write_cr3(__pa(pgdir)); 204 } 205 206 #ifdef CONFIG_X86_32 207 /* This is the TSS defined by the hardware. */ 208 struct x86_hw_tss { 209 unsigned short back_link, __blh; 210 unsigned long sp0; 211 unsigned short ss0, __ss0h; 212 unsigned long sp1; 213 /* ss1 caches MSR_IA32_SYSENTER_CS: */ 214 unsigned short ss1, __ss1h; 215 unsigned long sp2; 216 unsigned short ss2, __ss2h; 217 unsigned long __cr3; 218 unsigned long ip; 219 unsigned long flags; 220 unsigned long ax; 221 unsigned long cx; 222 unsigned long dx; 223 unsigned long bx; 224 unsigned long sp; 225 unsigned long bp; 226 unsigned long si; 227 unsigned long di; 228 unsigned short es, __esh; 229 unsigned short cs, __csh; 230 unsigned short ss, __ssh; 231 unsigned short ds, __dsh; 232 unsigned short fs, __fsh; 233 unsigned short gs, __gsh; 234 unsigned short ldt, __ldth; 235 unsigned short trace; 236 unsigned short io_bitmap_base; 237 238 } __attribute__((packed)); 239 #else 240 struct x86_hw_tss { 241 u32 reserved1; 242 u64 sp0; 243 u64 sp1; 244 u64 sp2; 245 u64 reserved2; 246 u64 ist[7]; 247 u32 reserved3; 248 u32 reserved4; 249 u16 reserved5; 250 u16 io_bitmap_base; 251 252 } __attribute__((packed)) ____cacheline_aligned; 253 #endif 254 255 /* 256 * IO-bitmap sizes: 257 */ 258 #define IO_BITMAP_BITS 65536 259 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) 260 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) 261 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) 262 #define INVALID_IO_BITMAP_OFFSET 0x8000 263 264 struct tss_struct { 265 /* 266 * The hardware state: 267 */ 268 struct x86_hw_tss x86_tss; 269 270 /* 271 * The extra 1 is there because the CPU will access an 272 * additional byte beyond the end of the IO permission 273 * bitmap. The extra byte must be all 1 bits, and must 274 * be within the limit. 275 */ 276 unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; 277 278 /* 279 * .. and then another 0x100 bytes for the emergency kernel stack: 280 */ 281 unsigned long stack[64]; 282 283 } ____cacheline_aligned; 284 285 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss); 286 287 /* 288 * Save the original ist values for checking stack pointers during debugging 289 */ 290 struct orig_ist { 291 unsigned long ist[7]; 292 }; 293 294 #define MXCSR_DEFAULT 0x1f80 295 296 struct i387_fsave_struct { 297 u32 cwd; /* FPU Control Word */ 298 u32 swd; /* FPU Status Word */ 299 u32 twd; /* FPU Tag Word */ 300 u32 fip; /* FPU IP Offset */ 301 u32 fcs; /* FPU IP Selector */ 302 u32 foo; /* FPU Operand Pointer Offset */ 303 u32 fos; /* FPU Operand Pointer Selector */ 304 305 /* 8*10 bytes for each FP-reg = 80 bytes: */ 306 u32 st_space[20]; 307 308 /* Software status information [not touched by FSAVE ]: */ 309 u32 status; 310 }; 311 312 struct i387_fxsave_struct { 313 u16 cwd; /* Control Word */ 314 u16 swd; /* Status Word */ 315 u16 twd; /* Tag Word */ 316 u16 fop; /* Last Instruction Opcode */ 317 union { 318 struct { 319 u64 rip; /* Instruction Pointer */ 320 u64 rdp; /* Data Pointer */ 321 }; 322 struct { 323 u32 fip; /* FPU IP Offset */ 324 u32 fcs; /* FPU IP Selector */ 325 u32 foo; /* FPU Operand Offset */ 326 u32 fos; /* FPU Operand Selector */ 327 }; 328 }; 329 u32 mxcsr; /* MXCSR Register State */ 330 u32 mxcsr_mask; /* MXCSR Mask */ 331 332 /* 8*16 bytes for each FP-reg = 128 bytes: */ 333 u32 st_space[32]; 334 335 /* 16*16 bytes for each XMM-reg = 256 bytes: */ 336 u32 xmm_space[64]; 337 338 u32 padding[12]; 339 340 union { 341 u32 padding1[12]; 342 u32 sw_reserved[12]; 343 }; 344 345 } __attribute__((aligned(16))); 346 347 struct i387_soft_struct { 348 u32 cwd; 349 u32 swd; 350 u32 twd; 351 u32 fip; 352 u32 fcs; 353 u32 foo; 354 u32 fos; 355 /* 8*10 bytes for each FP-reg = 80 bytes: */ 356 u32 st_space[20]; 357 u8 ftop; 358 u8 changed; 359 u8 lookahead; 360 u8 no_update; 361 u8 rm; 362 u8 alimit; 363 struct math_emu_info *info; 364 u32 entry_eip; 365 }; 366 367 struct ymmh_struct { 368 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */ 369 u32 ymmh_space[64]; 370 }; 371 372 struct xsave_hdr_struct { 373 u64 xstate_bv; 374 u64 reserved1[2]; 375 u64 reserved2[5]; 376 } __attribute__((packed)); 377 378 struct xsave_struct { 379 struct i387_fxsave_struct i387; 380 struct xsave_hdr_struct xsave_hdr; 381 struct ymmh_struct ymmh; 382 /* new processor state extensions will go here */ 383 } __attribute__ ((packed, aligned (64))); 384 385 union thread_xstate { 386 struct i387_fsave_struct fsave; 387 struct i387_fxsave_struct fxsave; 388 struct i387_soft_struct soft; 389 struct xsave_struct xsave; 390 }; 391 392 struct fpu { 393 unsigned int last_cpu; 394 unsigned int has_fpu; 395 union thread_xstate *state; 396 }; 397 398 #ifdef CONFIG_X86_64 399 DECLARE_PER_CPU(struct orig_ist, orig_ist); 400 401 union irq_stack_union { 402 char irq_stack[IRQ_STACK_SIZE]; 403 /* 404 * GCC hardcodes the stack canary as %gs:40. Since the 405 * irq_stack is the object at %gs:0, we reserve the bottom 406 * 48 bytes of the irq stack for the canary. 407 */ 408 struct { 409 char gs_base[40]; 410 unsigned long stack_canary; 411 }; 412 }; 413 414 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union); 415 DECLARE_INIT_PER_CPU(irq_stack_union); 416 417 DECLARE_PER_CPU(char *, irq_stack_ptr); 418 DECLARE_PER_CPU(unsigned int, irq_count); 419 extern asmlinkage void ignore_sysret(void); 420 #else /* X86_64 */ 421 #ifdef CONFIG_CC_STACKPROTECTOR 422 /* 423 * Make sure stack canary segment base is cached-aligned: 424 * "For Intel Atom processors, avoid non zero segment base address 425 * that is not aligned to cache line boundary at all cost." 426 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) 427 */ 428 struct stack_canary { 429 char __pad[20]; /* canary at %gs:20 */ 430 unsigned long canary; 431 }; 432 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 433 #endif 434 #endif /* X86_64 */ 435 436 extern unsigned int xstate_size; 437 extern void free_thread_xstate(struct task_struct *); 438 extern struct kmem_cache *task_xstate_cachep; 439 440 struct perf_event; 441 442 struct thread_struct { 443 /* Cached TLS descriptors: */ 444 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 445 unsigned long sp0; 446 unsigned long sp; 447 #ifdef CONFIG_X86_32 448 unsigned long sysenter_cs; 449 #else 450 unsigned long usersp; /* Copy from PDA */ 451 unsigned short es; 452 unsigned short ds; 453 unsigned short fsindex; 454 unsigned short gsindex; 455 #endif 456 #ifdef CONFIG_X86_32 457 unsigned long ip; 458 #endif 459 #ifdef CONFIG_X86_64 460 unsigned long fs; 461 #endif 462 unsigned long gs; 463 /* Save middle states of ptrace breakpoints */ 464 struct perf_event *ptrace_bps[HBP_NUM]; 465 /* Debug status used for traps, single steps, etc... */ 466 unsigned long debugreg6; 467 /* Keep track of the exact dr7 value set by the user */ 468 unsigned long ptrace_dr7; 469 /* Fault info: */ 470 unsigned long cr2; 471 unsigned long trap_nr; 472 unsigned long error_code; 473 /* floating point and extended processor state */ 474 struct fpu fpu; 475 #ifdef CONFIG_X86_32 476 /* Virtual 86 mode info */ 477 struct vm86_struct __user *vm86_info; 478 unsigned long screen_bitmap; 479 unsigned long v86flags; 480 unsigned long v86mask; 481 unsigned long saved_sp0; 482 unsigned int saved_fs; 483 unsigned int saved_gs; 484 #endif 485 /* IO permissions: */ 486 unsigned long *io_bitmap_ptr; 487 unsigned long iopl; 488 /* Max allowed port in the bitmap, in bytes: */ 489 unsigned io_bitmap_max; 490 }; 491 492 /* 493 * Set IOPL bits in EFLAGS from given mask 494 */ 495 static inline void native_set_iopl_mask(unsigned mask) 496 { 497 #ifdef CONFIG_X86_32 498 unsigned int reg; 499 500 asm volatile ("pushfl;" 501 "popl %0;" 502 "andl %1, %0;" 503 "orl %2, %0;" 504 "pushl %0;" 505 "popfl" 506 : "=&r" (reg) 507 : "i" (~X86_EFLAGS_IOPL), "r" (mask)); 508 #endif 509 } 510 511 static inline void 512 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread) 513 { 514 tss->x86_tss.sp0 = thread->sp0; 515 #ifdef CONFIG_X86_32 516 /* Only happens when SEP is enabled, no need to test "SEP"arately: */ 517 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { 518 tss->x86_tss.ss1 = thread->sysenter_cs; 519 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); 520 } 521 #endif 522 } 523 524 static inline void native_swapgs(void) 525 { 526 #ifdef CONFIG_X86_64 527 asm volatile("swapgs" ::: "memory"); 528 #endif 529 } 530 531 #ifdef CONFIG_PARAVIRT 532 #include <asm/paravirt.h> 533 #else 534 #define __cpuid native_cpuid 535 #define paravirt_enabled() 0 536 537 static inline void load_sp0(struct tss_struct *tss, 538 struct thread_struct *thread) 539 { 540 native_load_sp0(tss, thread); 541 } 542 543 #define set_iopl_mask native_set_iopl_mask 544 #endif /* CONFIG_PARAVIRT */ 545 546 /* 547 * Save the cr4 feature set we're using (ie 548 * Pentium 4MB enable and PPro Global page 549 * enable), so that any CPU's that boot up 550 * after us can get the correct flags. 551 */ 552 extern unsigned long mmu_cr4_features; 553 extern u32 *trampoline_cr4_features; 554 555 static inline void set_in_cr4(unsigned long mask) 556 { 557 unsigned long cr4; 558 559 mmu_cr4_features |= mask; 560 if (trampoline_cr4_features) 561 *trampoline_cr4_features = mmu_cr4_features; 562 cr4 = read_cr4(); 563 cr4 |= mask; 564 write_cr4(cr4); 565 } 566 567 static inline void clear_in_cr4(unsigned long mask) 568 { 569 unsigned long cr4; 570 571 mmu_cr4_features &= ~mask; 572 if (trampoline_cr4_features) 573 *trampoline_cr4_features = mmu_cr4_features; 574 cr4 = read_cr4(); 575 cr4 &= ~mask; 576 write_cr4(cr4); 577 } 578 579 typedef struct { 580 unsigned long seg; 581 } mm_segment_t; 582 583 584 /* Free all resources held by a thread. */ 585 extern void release_thread(struct task_struct *); 586 587 unsigned long get_wchan(struct task_struct *p); 588 589 /* 590 * Generic CPUID function 591 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 592 * resulting in stale register contents being returned. 593 */ 594 static inline void cpuid(unsigned int op, 595 unsigned int *eax, unsigned int *ebx, 596 unsigned int *ecx, unsigned int *edx) 597 { 598 *eax = op; 599 *ecx = 0; 600 __cpuid(eax, ebx, ecx, edx); 601 } 602 603 /* Some CPUID calls want 'count' to be placed in ecx */ 604 static inline void cpuid_count(unsigned int op, int count, 605 unsigned int *eax, unsigned int *ebx, 606 unsigned int *ecx, unsigned int *edx) 607 { 608 *eax = op; 609 *ecx = count; 610 __cpuid(eax, ebx, ecx, edx); 611 } 612 613 /* 614 * CPUID functions returning a single datum 615 */ 616 static inline unsigned int cpuid_eax(unsigned int op) 617 { 618 unsigned int eax, ebx, ecx, edx; 619 620 cpuid(op, &eax, &ebx, &ecx, &edx); 621 622 return eax; 623 } 624 625 static inline unsigned int cpuid_ebx(unsigned int op) 626 { 627 unsigned int eax, ebx, ecx, edx; 628 629 cpuid(op, &eax, &ebx, &ecx, &edx); 630 631 return ebx; 632 } 633 634 static inline unsigned int cpuid_ecx(unsigned int op) 635 { 636 unsigned int eax, ebx, ecx, edx; 637 638 cpuid(op, &eax, &ebx, &ecx, &edx); 639 640 return ecx; 641 } 642 643 static inline unsigned int cpuid_edx(unsigned int op) 644 { 645 unsigned int eax, ebx, ecx, edx; 646 647 cpuid(op, &eax, &ebx, &ecx, &edx); 648 649 return edx; 650 } 651 652 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 653 static inline void rep_nop(void) 654 { 655 asm volatile("rep; nop" ::: "memory"); 656 } 657 658 static inline void cpu_relax(void) 659 { 660 rep_nop(); 661 } 662 663 /* Stop speculative execution and prefetching of modified code. */ 664 static inline void sync_core(void) 665 { 666 int tmp; 667 668 #ifdef CONFIG_M486 669 /* 670 * Do a CPUID if available, otherwise do a jump. The jump 671 * can conveniently enough be the jump around CPUID. 672 */ 673 asm volatile("cmpl %2,%1\n\t" 674 "jl 1f\n\t" 675 "cpuid\n" 676 "1:" 677 : "=a" (tmp) 678 : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1) 679 : "ebx", "ecx", "edx", "memory"); 680 #else 681 /* 682 * CPUID is a barrier to speculative execution. 683 * Prefetched instructions are automatically 684 * invalidated when modified. 685 */ 686 asm volatile("cpuid" 687 : "=a" (tmp) 688 : "0" (1) 689 : "ebx", "ecx", "edx", "memory"); 690 #endif 691 } 692 693 static inline void __monitor(const void *eax, unsigned long ecx, 694 unsigned long edx) 695 { 696 /* "monitor %eax, %ecx, %edx;" */ 697 asm volatile(".byte 0x0f, 0x01, 0xc8;" 698 :: "a" (eax), "c" (ecx), "d"(edx)); 699 } 700 701 static inline void __mwait(unsigned long eax, unsigned long ecx) 702 { 703 /* "mwait %eax, %ecx;" */ 704 asm volatile(".byte 0x0f, 0x01, 0xc9;" 705 :: "a" (eax), "c" (ecx)); 706 } 707 708 static inline void __sti_mwait(unsigned long eax, unsigned long ecx) 709 { 710 trace_hardirqs_on(); 711 /* "mwait %eax, %ecx;" */ 712 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;" 713 :: "a" (eax), "c" (ecx)); 714 } 715 716 extern void select_idle_routine(const struct cpuinfo_x86 *c); 717 extern void init_amd_e400_c1e_mask(void); 718 719 extern unsigned long boot_option_idle_override; 720 extern bool amd_e400_c1e_detected; 721 722 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 723 IDLE_POLL}; 724 725 extern void enable_sep_cpu(void); 726 extern int sysenter_setup(void); 727 728 extern void early_trap_init(void); 729 void early_trap_pf_init(void); 730 731 /* Defined in head.S */ 732 extern struct desc_ptr early_gdt_descr; 733 734 extern void cpu_set_gdt(int); 735 extern void switch_to_new_gdt(int); 736 extern void load_percpu_segment(int); 737 extern void cpu_init(void); 738 739 static inline unsigned long get_debugctlmsr(void) 740 { 741 unsigned long debugctlmsr = 0; 742 743 #ifndef CONFIG_X86_DEBUGCTLMSR 744 if (boot_cpu_data.x86 < 6) 745 return 0; 746 #endif 747 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 748 749 return debugctlmsr; 750 } 751 752 static inline void update_debugctlmsr(unsigned long debugctlmsr) 753 { 754 #ifndef CONFIG_X86_DEBUGCTLMSR 755 if (boot_cpu_data.x86 < 6) 756 return; 757 #endif 758 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 759 } 760 761 extern void set_task_blockstep(struct task_struct *task, bool on); 762 763 /* 764 * from system description table in BIOS. Mostly for MCA use, but 765 * others may find it useful: 766 */ 767 extern unsigned int machine_id; 768 extern unsigned int machine_submodel_id; 769 extern unsigned int BIOS_revision; 770 771 /* Boot loader type from the setup header: */ 772 extern int bootloader_type; 773 extern int bootloader_version; 774 775 extern char ignore_fpu_irq; 776 777 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 778 #define ARCH_HAS_PREFETCHW 779 #define ARCH_HAS_SPINLOCK_PREFETCH 780 781 #ifdef CONFIG_X86_32 782 # define BASE_PREFETCH ASM_NOP4 783 # define ARCH_HAS_PREFETCH 784 #else 785 # define BASE_PREFETCH "prefetcht0 (%1)" 786 #endif 787 788 /* 789 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 790 * 791 * It's not worth to care about 3dnow prefetches for the K6 792 * because they are microcoded there and very slow. 793 */ 794 static inline void prefetch(const void *x) 795 { 796 alternative_input(BASE_PREFETCH, 797 "prefetchnta (%1)", 798 X86_FEATURE_XMM, 799 "r" (x)); 800 } 801 802 /* 803 * 3dnow prefetch to get an exclusive cache line. 804 * Useful for spinlocks to avoid one state transition in the 805 * cache coherency protocol: 806 */ 807 static inline void prefetchw(const void *x) 808 { 809 alternative_input(BASE_PREFETCH, 810 "prefetchw (%1)", 811 X86_FEATURE_3DNOW, 812 "r" (x)); 813 } 814 815 static inline void spin_lock_prefetch(const void *x) 816 { 817 prefetchw(x); 818 } 819 820 #ifdef CONFIG_X86_32 821 /* 822 * User space process size: 3GB (default). 823 */ 824 #define TASK_SIZE PAGE_OFFSET 825 #define TASK_SIZE_MAX TASK_SIZE 826 #define STACK_TOP TASK_SIZE 827 #define STACK_TOP_MAX STACK_TOP 828 829 #define INIT_THREAD { \ 830 .sp0 = sizeof(init_stack) + (long)&init_stack, \ 831 .vm86_info = NULL, \ 832 .sysenter_cs = __KERNEL_CS, \ 833 .io_bitmap_ptr = NULL, \ 834 } 835 836 /* 837 * Note that the .io_bitmap member must be extra-big. This is because 838 * the CPU will access an additional byte beyond the end of the IO 839 * permission bitmap. The extra byte must be all 1 bits, and must 840 * be within the limit. 841 */ 842 #define INIT_TSS { \ 843 .x86_tss = { \ 844 .sp0 = sizeof(init_stack) + (long)&init_stack, \ 845 .ss0 = __KERNEL_DS, \ 846 .ss1 = __KERNEL_CS, \ 847 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \ 848 }, \ 849 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \ 850 } 851 852 extern unsigned long thread_saved_pc(struct task_struct *tsk); 853 854 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long)) 855 #define KSTK_TOP(info) \ 856 ({ \ 857 unsigned long *__ptr = (unsigned long *)(info); \ 858 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \ 859 }) 860 861 /* 862 * The below -8 is to reserve 8 bytes on top of the ring0 stack. 863 * This is necessary to guarantee that the entire "struct pt_regs" 864 * is accessible even if the CPU haven't stored the SS/ESP registers 865 * on the stack (interrupt gate does not save these registers 866 * when switching to the same priv ring). 867 * Therefore beware: accessing the ss/esp fields of the 868 * "struct pt_regs" is possible, but they may contain the 869 * completely wrong values. 870 */ 871 #define task_pt_regs(task) \ 872 ({ \ 873 struct pt_regs *__regs__; \ 874 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \ 875 __regs__ - 1; \ 876 }) 877 878 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 879 880 #else 881 /* 882 * User space process size. 47bits minus one guard page. 883 */ 884 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE) 885 886 /* This decides where the kernel will search for a free chunk of vm 887 * space during mmap's. 888 */ 889 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ 890 0xc0000000 : 0xFFFFe000) 891 892 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ 893 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 894 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ 895 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 896 897 #define STACK_TOP TASK_SIZE 898 #define STACK_TOP_MAX TASK_SIZE_MAX 899 900 #define INIT_THREAD { \ 901 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ 902 } 903 904 #define INIT_TSS { \ 905 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ 906 } 907 908 /* 909 * Return saved PC of a blocked thread. 910 * What is this good for? it will be always the scheduler or ret_from_fork. 911 */ 912 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8)) 913 914 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) 915 extern unsigned long KSTK_ESP(struct task_struct *task); 916 917 /* 918 * User space RSP while inside the SYSCALL fast path 919 */ 920 DECLARE_PER_CPU(unsigned long, old_rsp); 921 922 #endif /* CONFIG_X86_64 */ 923 924 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 925 unsigned long new_sp); 926 927 /* 928 * This decides where the kernel will search for a free chunk of vm 929 * space during mmap's. 930 */ 931 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) 932 933 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 934 935 /* Get/set a process' ability to use the timestamp counter instruction */ 936 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 937 #define SET_TSC_CTL(val) set_tsc_mode((val)) 938 939 extern int get_tsc_mode(unsigned long adr); 940 extern int set_tsc_mode(unsigned int val); 941 942 extern u16 amd_get_nb_id(int cpu); 943 944 struct aperfmperf { 945 u64 aperf, mperf; 946 }; 947 948 static inline void get_aperfmperf(struct aperfmperf *am) 949 { 950 WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF)); 951 952 rdmsrl(MSR_IA32_APERF, am->aperf); 953 rdmsrl(MSR_IA32_MPERF, am->mperf); 954 } 955 956 #define APERFMPERF_SHIFT 10 957 958 static inline 959 unsigned long calc_aperfmperf_ratio(struct aperfmperf *old, 960 struct aperfmperf *new) 961 { 962 u64 aperf = new->aperf - old->aperf; 963 u64 mperf = new->mperf - old->mperf; 964 unsigned long ratio = aperf; 965 966 mperf >>= APERFMPERF_SHIFT; 967 if (mperf) 968 ratio = div64_u64(aperf, mperf); 969 970 return ratio; 971 } 972 973 extern unsigned long arch_align_stack(unsigned long sp); 974 extern void free_init_pages(char *what, unsigned long begin, unsigned long end); 975 976 void default_idle(void); 977 #ifdef CONFIG_XEN 978 bool xen_set_default_idle(void); 979 #else 980 #define xen_set_default_idle 0 981 #endif 982 983 void stop_this_cpu(void *dummy); 984 985 #endif /* _ASM_X86_PROCESSOR_H */ 986