1 #ifndef _ASM_X86_PROCESSOR_FLAGS_H 2 #define _ASM_X86_PROCESSOR_FLAGS_H 3 4 #include <uapi/asm/processor-flags.h> 5 #include <linux/mem_encrypt.h> 6 7 #ifdef CONFIG_VM86 8 #define X86_VM_MASK X86_EFLAGS_VM 9 #else 10 #define X86_VM_MASK 0 /* No VM86 support */ 11 #endif 12 13 /* 14 * CR3's layout varies depending on several things. 15 * 16 * If CR4.PCIDE is set (64-bit only), then CR3[11:0] is the address space ID. 17 * If PAE is enabled, then CR3[11:5] is part of the PDPT address 18 * (i.e. it's 32-byte aligned, not page-aligned) and CR3[4:0] is ignored. 19 * Otherwise (non-PAE, non-PCID), CR3[3] is PWT, CR3[4] is PCD, and 20 * CR3[2:0] and CR3[11:5] are ignored. 21 * 22 * In all cases, Linux puts zeros in the low ignored bits and in PWT and PCD. 23 * 24 * CR3[63] is always read as zero. If CR4.PCIDE is set, then CR3[63] may be 25 * written as 1 to prevent the write to CR3 from flushing the TLB. 26 * 27 * On systems with SME, one bit (in a variable position!) is stolen to indicate 28 * that the top-level paging structure is encrypted. 29 * 30 * All of the remaining bits indicate the physical address of the top-level 31 * paging structure. 32 * 33 * CR3_ADDR_MASK is the mask used by read_cr3_pa(). 34 */ 35 #ifdef CONFIG_X86_64 36 /* Mask off the address space ID and SME encryption bits. */ 37 #define CR3_ADDR_MASK __sme_clr(0x7FFFFFFFFFFFF000ull) 38 #define CR3_PCID_MASK 0xFFFull 39 #else 40 /* 41 * CR3_ADDR_MASK needs at least bits 31:5 set on PAE systems, and we save 42 * a tiny bit of code size by setting all the bits. 43 */ 44 #define CR3_ADDR_MASK 0xFFFFFFFFull 45 #define CR3_PCID_MASK 0ull 46 #endif 47 48 #endif /* _ASM_X86_PROCESSOR_FLAGS_H */ 49