1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_PGTABLE_DEFS_H 3 #define _ASM_X86_PGTABLE_DEFS_H 4 5 #include <linux/const.h> 6 #include <linux/mem_encrypt.h> 7 8 #include <asm/page_types.h> 9 10 #define FIRST_USER_ADDRESS 0UL 11 12 #define _PAGE_BIT_PRESENT 0 /* is present */ 13 #define _PAGE_BIT_RW 1 /* writeable */ 14 #define _PAGE_BIT_USER 2 /* userspace addressable */ 15 #define _PAGE_BIT_PWT 3 /* page write through */ 16 #define _PAGE_BIT_PCD 4 /* page cache disabled */ 17 #define _PAGE_BIT_ACCESSED 5 /* was accessed (raised by CPU) */ 18 #define _PAGE_BIT_DIRTY 6 /* was written to (raised by CPU) */ 19 #define _PAGE_BIT_PSE 7 /* 4 MB (or 2MB) page */ 20 #define _PAGE_BIT_PAT 7 /* on 4KB pages */ 21 #define _PAGE_BIT_GLOBAL 8 /* Global TLB entry PPro+ */ 22 #define _PAGE_BIT_SOFTW1 9 /* available for programmer */ 23 #define _PAGE_BIT_SOFTW2 10 /* " */ 24 #define _PAGE_BIT_SOFTW3 11 /* " */ 25 #define _PAGE_BIT_PAT_LARGE 12 /* On 2MB or 1GB pages */ 26 #define _PAGE_BIT_SOFTW4 58 /* available for programmer */ 27 #define _PAGE_BIT_PKEY_BIT0 59 /* Protection Keys, bit 1/4 */ 28 #define _PAGE_BIT_PKEY_BIT1 60 /* Protection Keys, bit 2/4 */ 29 #define _PAGE_BIT_PKEY_BIT2 61 /* Protection Keys, bit 3/4 */ 30 #define _PAGE_BIT_PKEY_BIT3 62 /* Protection Keys, bit 4/4 */ 31 #define _PAGE_BIT_NX 63 /* No execute: only valid after cpuid check */ 32 33 #define _PAGE_BIT_SPECIAL _PAGE_BIT_SOFTW1 34 #define _PAGE_BIT_CPA_TEST _PAGE_BIT_SOFTW1 35 #define _PAGE_BIT_SOFT_DIRTY _PAGE_BIT_SOFTW3 /* software dirty tracking */ 36 #define _PAGE_BIT_DEVMAP _PAGE_BIT_SOFTW4 37 38 /* If _PAGE_BIT_PRESENT is clear, we use these: */ 39 /* - if the user mapped it with PROT_NONE; pte_present gives true */ 40 #define _PAGE_BIT_PROTNONE _PAGE_BIT_GLOBAL 41 42 #define _PAGE_PRESENT (_AT(pteval_t, 1) << _PAGE_BIT_PRESENT) 43 #define _PAGE_RW (_AT(pteval_t, 1) << _PAGE_BIT_RW) 44 #define _PAGE_USER (_AT(pteval_t, 1) << _PAGE_BIT_USER) 45 #define _PAGE_PWT (_AT(pteval_t, 1) << _PAGE_BIT_PWT) 46 #define _PAGE_PCD (_AT(pteval_t, 1) << _PAGE_BIT_PCD) 47 #define _PAGE_ACCESSED (_AT(pteval_t, 1) << _PAGE_BIT_ACCESSED) 48 #define _PAGE_DIRTY (_AT(pteval_t, 1) << _PAGE_BIT_DIRTY) 49 #define _PAGE_PSE (_AT(pteval_t, 1) << _PAGE_BIT_PSE) 50 #define _PAGE_GLOBAL (_AT(pteval_t, 1) << _PAGE_BIT_GLOBAL) 51 #define _PAGE_SOFTW1 (_AT(pteval_t, 1) << _PAGE_BIT_SOFTW1) 52 #define _PAGE_SOFTW2 (_AT(pteval_t, 1) << _PAGE_BIT_SOFTW2) 53 #define _PAGE_SOFTW3 (_AT(pteval_t, 1) << _PAGE_BIT_SOFTW3) 54 #define _PAGE_PAT (_AT(pteval_t, 1) << _PAGE_BIT_PAT) 55 #define _PAGE_PAT_LARGE (_AT(pteval_t, 1) << _PAGE_BIT_PAT_LARGE) 56 #define _PAGE_SPECIAL (_AT(pteval_t, 1) << _PAGE_BIT_SPECIAL) 57 #define _PAGE_CPA_TEST (_AT(pteval_t, 1) << _PAGE_BIT_CPA_TEST) 58 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 59 #define _PAGE_PKEY_BIT0 (_AT(pteval_t, 1) << _PAGE_BIT_PKEY_BIT0) 60 #define _PAGE_PKEY_BIT1 (_AT(pteval_t, 1) << _PAGE_BIT_PKEY_BIT1) 61 #define _PAGE_PKEY_BIT2 (_AT(pteval_t, 1) << _PAGE_BIT_PKEY_BIT2) 62 #define _PAGE_PKEY_BIT3 (_AT(pteval_t, 1) << _PAGE_BIT_PKEY_BIT3) 63 #else 64 #define _PAGE_PKEY_BIT0 (_AT(pteval_t, 0)) 65 #define _PAGE_PKEY_BIT1 (_AT(pteval_t, 0)) 66 #define _PAGE_PKEY_BIT2 (_AT(pteval_t, 0)) 67 #define _PAGE_PKEY_BIT3 (_AT(pteval_t, 0)) 68 #endif 69 70 #define _PAGE_PKEY_MASK (_PAGE_PKEY_BIT0 | \ 71 _PAGE_PKEY_BIT1 | \ 72 _PAGE_PKEY_BIT2 | \ 73 _PAGE_PKEY_BIT3) 74 75 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) 76 #define _PAGE_KNL_ERRATUM_MASK (_PAGE_DIRTY | _PAGE_ACCESSED) 77 #else 78 #define _PAGE_KNL_ERRATUM_MASK 0 79 #endif 80 81 #ifdef CONFIG_MEM_SOFT_DIRTY 82 #define _PAGE_SOFT_DIRTY (_AT(pteval_t, 1) << _PAGE_BIT_SOFT_DIRTY) 83 #else 84 #define _PAGE_SOFT_DIRTY (_AT(pteval_t, 0)) 85 #endif 86 87 /* 88 * Tracking soft dirty bit when a page goes to a swap is tricky. 89 * We need a bit which can be stored in pte _and_ not conflict 90 * with swap entry format. On x86 bits 1-4 are *not* involved 91 * into swap entry computation, but bit 7 is used for thp migration, 92 * so we borrow bit 1 for soft dirty tracking. 93 * 94 * Please note that this bit must be treated as swap dirty page 95 * mark if and only if the PTE/PMD has present bit clear! 96 */ 97 #ifdef CONFIG_MEM_SOFT_DIRTY 98 #define _PAGE_SWP_SOFT_DIRTY _PAGE_RW 99 #else 100 #define _PAGE_SWP_SOFT_DIRTY (_AT(pteval_t, 0)) 101 #endif 102 103 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) 104 #define _PAGE_NX (_AT(pteval_t, 1) << _PAGE_BIT_NX) 105 #define _PAGE_DEVMAP (_AT(u64, 1) << _PAGE_BIT_DEVMAP) 106 #else 107 #define _PAGE_NX (_AT(pteval_t, 0)) 108 #define _PAGE_DEVMAP (_AT(pteval_t, 0)) 109 #endif 110 111 #define _PAGE_PROTNONE (_AT(pteval_t, 1) << _PAGE_BIT_PROTNONE) 112 113 /* 114 * Set of bits not changed in pte_modify. The pte's 115 * protection key is treated like _PAGE_RW, for 116 * instance, and is *not* included in this mask since 117 * pte_modify() does modify it. 118 */ 119 #define _PAGE_CHG_MASK (PTE_PFN_MASK | _PAGE_PCD | _PAGE_PWT | \ 120 _PAGE_SPECIAL | _PAGE_ACCESSED | _PAGE_DIRTY | \ 121 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 122 #define _HPAGE_CHG_MASK (_PAGE_CHG_MASK | _PAGE_PSE) 123 124 /* 125 * The cache modes defined here are used to translate between pure SW usage 126 * and the HW defined cache mode bits and/or PAT entries. 127 * 128 * The resulting bits for PWT, PCD and PAT should be chosen in a way 129 * to have the WB mode at index 0 (all bits clear). This is the default 130 * right now and likely would break too much if changed. 131 */ 132 #ifndef __ASSEMBLY__ 133 enum page_cache_mode { 134 _PAGE_CACHE_MODE_WB = 0, 135 _PAGE_CACHE_MODE_WC = 1, 136 _PAGE_CACHE_MODE_UC_MINUS = 2, 137 _PAGE_CACHE_MODE_UC = 3, 138 _PAGE_CACHE_MODE_WT = 4, 139 _PAGE_CACHE_MODE_WP = 5, 140 141 _PAGE_CACHE_MODE_NUM = 8 142 }; 143 #endif 144 145 #define _PAGE_ENC (_AT(pteval_t, sme_me_mask)) 146 147 #define _PAGE_CACHE_MASK (_PAGE_PWT | _PAGE_PCD | _PAGE_PAT) 148 149 #define _PAGE_NOCACHE (cachemode2protval(_PAGE_CACHE_MODE_UC)) 150 #define _PAGE_CACHE_WP (cachemode2protval(_PAGE_CACHE_MODE_WP)) 151 152 #define __PP _PAGE_PRESENT 153 #define __RW _PAGE_RW 154 #define _USR _PAGE_USER 155 #define ___A _PAGE_ACCESSED 156 #define ___D _PAGE_DIRTY 157 #define ___G _PAGE_GLOBAL 158 #define __NX _PAGE_NX 159 160 #define _ENC _PAGE_ENC 161 #define __WP _PAGE_CACHE_WP 162 #define __NC _PAGE_NOCACHE 163 #define _PSE _PAGE_PSE 164 165 #define pgprot_val(x) ((x).pgprot) 166 #define __pgprot(x) ((pgprot_t) { (x) } ) 167 #define __pg(x) __pgprot(x) 168 169 #define _PAGE_PAT_LARGE (_AT(pteval_t, 1) << _PAGE_BIT_PAT_LARGE) 170 171 #define PAGE_NONE __pg( 0| 0| 0|___A| 0| 0| 0|___G) 172 #define PAGE_SHARED __pg(__PP|__RW|_USR|___A|__NX| 0| 0| 0) 173 #define PAGE_SHARED_EXEC __pg(__PP|__RW|_USR|___A| 0| 0| 0| 0) 174 #define PAGE_COPY_NOEXEC __pg(__PP| 0|_USR|___A|__NX| 0| 0| 0) 175 #define PAGE_COPY_EXEC __pg(__PP| 0|_USR|___A| 0| 0| 0| 0) 176 #define PAGE_COPY __pg(__PP| 0|_USR|___A|__NX| 0| 0| 0) 177 #define PAGE_READONLY __pg(__PP| 0|_USR|___A|__NX| 0| 0| 0) 178 #define PAGE_READONLY_EXEC __pg(__PP| 0|_USR|___A| 0| 0| 0| 0) 179 180 #define __PAGE_KERNEL (__PP|__RW| 0|___A|__NX|___D| 0|___G) 181 #define __PAGE_KERNEL_EXEC (__PP|__RW| 0|___A| 0|___D| 0|___G) 182 #define _KERNPG_TABLE_NOENC (__PP|__RW| 0|___A| 0|___D| 0| 0) 183 #define _KERNPG_TABLE (__PP|__RW| 0|___A| 0|___D| 0| 0| _ENC) 184 #define _PAGE_TABLE_NOENC (__PP|__RW|_USR|___A| 0|___D| 0| 0) 185 #define _PAGE_TABLE (__PP|__RW|_USR|___A| 0|___D| 0| 0| _ENC) 186 #define __PAGE_KERNEL_RO (__PP| 0| 0|___A|__NX|___D| 0|___G) 187 #define __PAGE_KERNEL_RX (__PP| 0| 0|___A| 0|___D| 0|___G) 188 #define __PAGE_KERNEL_NOCACHE (__PP|__RW| 0|___A|__NX|___D| 0|___G| __NC) 189 #define __PAGE_KERNEL_VVAR (__PP| 0|_USR|___A|__NX|___D| 0|___G) 190 #define __PAGE_KERNEL_LARGE (__PP|__RW| 0|___A|__NX|___D|_PSE|___G) 191 #define __PAGE_KERNEL_LARGE_EXEC (__PP|__RW| 0|___A| 0|___D|_PSE|___G) 192 #define __PAGE_KERNEL_WP (__PP|__RW| 0|___A|__NX|___D| 0|___G| __WP) 193 194 195 #define __PAGE_KERNEL_IO __PAGE_KERNEL 196 #define __PAGE_KERNEL_IO_NOCACHE __PAGE_KERNEL_NOCACHE 197 198 199 #ifndef __ASSEMBLY__ 200 201 #define __PAGE_KERNEL_ENC (__PAGE_KERNEL | _ENC) 202 #define __PAGE_KERNEL_ENC_WP (__PAGE_KERNEL_WP | _ENC) 203 #define __PAGE_KERNEL_NOENC (__PAGE_KERNEL | 0) 204 #define __PAGE_KERNEL_NOENC_WP (__PAGE_KERNEL_WP | 0) 205 206 #define __pgprot_mask(x) __pgprot((x) & __default_kernel_pte_mask) 207 208 #define PAGE_KERNEL __pgprot_mask(__PAGE_KERNEL | _ENC) 209 #define PAGE_KERNEL_NOENC __pgprot_mask(__PAGE_KERNEL | 0) 210 #define PAGE_KERNEL_RO __pgprot_mask(__PAGE_KERNEL_RO | _ENC) 211 #define PAGE_KERNEL_EXEC __pgprot_mask(__PAGE_KERNEL_EXEC | _ENC) 212 #define PAGE_KERNEL_EXEC_NOENC __pgprot_mask(__PAGE_KERNEL_EXEC | 0) 213 #define PAGE_KERNEL_RX __pgprot_mask(__PAGE_KERNEL_RX | _ENC) 214 #define PAGE_KERNEL_NOCACHE __pgprot_mask(__PAGE_KERNEL_NOCACHE | _ENC) 215 #define PAGE_KERNEL_LARGE __pgprot_mask(__PAGE_KERNEL_LARGE | _ENC) 216 #define PAGE_KERNEL_LARGE_EXEC __pgprot_mask(__PAGE_KERNEL_LARGE_EXEC | _ENC) 217 #define PAGE_KERNEL_VVAR __pgprot_mask(__PAGE_KERNEL_VVAR | _ENC) 218 219 #define PAGE_KERNEL_IO __pgprot_mask(__PAGE_KERNEL_IO) 220 #define PAGE_KERNEL_IO_NOCACHE __pgprot_mask(__PAGE_KERNEL_IO_NOCACHE) 221 222 #endif /* __ASSEMBLY__ */ 223 224 /* xwr */ 225 #define __P000 PAGE_NONE 226 #define __P001 PAGE_READONLY 227 #define __P010 PAGE_COPY 228 #define __P011 PAGE_COPY 229 #define __P100 PAGE_READONLY_EXEC 230 #define __P101 PAGE_READONLY_EXEC 231 #define __P110 PAGE_COPY_EXEC 232 #define __P111 PAGE_COPY_EXEC 233 234 #define __S000 PAGE_NONE 235 #define __S001 PAGE_READONLY 236 #define __S010 PAGE_SHARED 237 #define __S011 PAGE_SHARED 238 #define __S100 PAGE_READONLY_EXEC 239 #define __S101 PAGE_READONLY_EXEC 240 #define __S110 PAGE_SHARED_EXEC 241 #define __S111 PAGE_SHARED_EXEC 242 243 /* 244 * early identity mapping pte attrib macros. 245 */ 246 #ifdef CONFIG_X86_64 247 #define __PAGE_KERNEL_IDENT_LARGE_EXEC __PAGE_KERNEL_LARGE_EXEC 248 #else 249 #define PTE_IDENT_ATTR 0x003 /* PRESENT+RW */ 250 #define PDE_IDENT_ATTR 0x063 /* PRESENT+RW+DIRTY+ACCESSED */ 251 #define PGD_IDENT_ATTR 0x001 /* PRESENT (no other attributes) */ 252 #endif 253 254 #ifdef CONFIG_X86_32 255 # include <asm/pgtable_32_types.h> 256 #else 257 # include <asm/pgtable_64_types.h> 258 #endif 259 260 #ifndef __ASSEMBLY__ 261 262 #include <linux/types.h> 263 264 /* Extracts the PFN from a (pte|pmd|pud|pgd)val_t of a 4KB page */ 265 #define PTE_PFN_MASK ((pteval_t)PHYSICAL_PAGE_MASK) 266 267 /* 268 * Extracts the flags from a (pte|pmd|pud|pgd)val_t 269 * This includes the protection key value. 270 */ 271 #define PTE_FLAGS_MASK (~PTE_PFN_MASK) 272 273 typedef struct pgprot { pgprotval_t pgprot; } pgprot_t; 274 275 typedef struct { pgdval_t pgd; } pgd_t; 276 277 #ifdef CONFIG_X86_PAE 278 279 /* 280 * PHYSICAL_PAGE_MASK might be non-constant when SME is compiled in, so we can't 281 * use it here. 282 */ 283 284 #define PGD_PAE_PAGE_MASK ((signed long)PAGE_MASK) 285 #define PGD_PAE_PHYS_MASK (((1ULL << __PHYSICAL_MASK_SHIFT)-1) & PGD_PAE_PAGE_MASK) 286 287 /* 288 * PAE allows Base Address, P, PWT, PCD and AVL bits to be set in PGD entries. 289 * All other bits are Reserved MBZ 290 */ 291 #define PGD_ALLOWED_BITS (PGD_PAE_PHYS_MASK | _PAGE_PRESENT | \ 292 _PAGE_PWT | _PAGE_PCD | \ 293 _PAGE_SOFTW1 | _PAGE_SOFTW2 | _PAGE_SOFTW3) 294 295 #else 296 /* No need to mask any bits for !PAE */ 297 #define PGD_ALLOWED_BITS (~0ULL) 298 #endif 299 300 static inline pgd_t native_make_pgd(pgdval_t val) 301 { 302 return (pgd_t) { val & PGD_ALLOWED_BITS }; 303 } 304 305 static inline pgdval_t native_pgd_val(pgd_t pgd) 306 { 307 return pgd.pgd & PGD_ALLOWED_BITS; 308 } 309 310 static inline pgdval_t pgd_flags(pgd_t pgd) 311 { 312 return native_pgd_val(pgd) & PTE_FLAGS_MASK; 313 } 314 315 #if CONFIG_PGTABLE_LEVELS > 4 316 typedef struct { p4dval_t p4d; } p4d_t; 317 318 static inline p4d_t native_make_p4d(pudval_t val) 319 { 320 return (p4d_t) { val }; 321 } 322 323 static inline p4dval_t native_p4d_val(p4d_t p4d) 324 { 325 return p4d.p4d; 326 } 327 #else 328 #include <asm-generic/pgtable-nop4d.h> 329 330 static inline p4d_t native_make_p4d(pudval_t val) 331 { 332 return (p4d_t) { .pgd = native_make_pgd((pgdval_t)val) }; 333 } 334 335 static inline p4dval_t native_p4d_val(p4d_t p4d) 336 { 337 return native_pgd_val(p4d.pgd); 338 } 339 #endif 340 341 #if CONFIG_PGTABLE_LEVELS > 3 342 typedef struct { pudval_t pud; } pud_t; 343 344 static inline pud_t native_make_pud(pmdval_t val) 345 { 346 return (pud_t) { val }; 347 } 348 349 static inline pudval_t native_pud_val(pud_t pud) 350 { 351 return pud.pud; 352 } 353 #else 354 #include <asm-generic/pgtable-nopud.h> 355 356 static inline pud_t native_make_pud(pudval_t val) 357 { 358 return (pud_t) { .p4d.pgd = native_make_pgd(val) }; 359 } 360 361 static inline pudval_t native_pud_val(pud_t pud) 362 { 363 return native_pgd_val(pud.p4d.pgd); 364 } 365 #endif 366 367 #if CONFIG_PGTABLE_LEVELS > 2 368 typedef struct { pmdval_t pmd; } pmd_t; 369 370 static inline pmd_t native_make_pmd(pmdval_t val) 371 { 372 return (pmd_t) { val }; 373 } 374 375 static inline pmdval_t native_pmd_val(pmd_t pmd) 376 { 377 return pmd.pmd; 378 } 379 #else 380 #include <asm-generic/pgtable-nopmd.h> 381 382 static inline pmd_t native_make_pmd(pmdval_t val) 383 { 384 return (pmd_t) { .pud.p4d.pgd = native_make_pgd(val) }; 385 } 386 387 static inline pmdval_t native_pmd_val(pmd_t pmd) 388 { 389 return native_pgd_val(pmd.pud.p4d.pgd); 390 } 391 #endif 392 393 static inline p4dval_t p4d_pfn_mask(p4d_t p4d) 394 { 395 /* No 512 GiB huge pages yet */ 396 return PTE_PFN_MASK; 397 } 398 399 static inline p4dval_t p4d_flags_mask(p4d_t p4d) 400 { 401 return ~p4d_pfn_mask(p4d); 402 } 403 404 static inline p4dval_t p4d_flags(p4d_t p4d) 405 { 406 return native_p4d_val(p4d) & p4d_flags_mask(p4d); 407 } 408 409 static inline pudval_t pud_pfn_mask(pud_t pud) 410 { 411 if (native_pud_val(pud) & _PAGE_PSE) 412 return PHYSICAL_PUD_PAGE_MASK; 413 else 414 return PTE_PFN_MASK; 415 } 416 417 static inline pudval_t pud_flags_mask(pud_t pud) 418 { 419 return ~pud_pfn_mask(pud); 420 } 421 422 static inline pudval_t pud_flags(pud_t pud) 423 { 424 return native_pud_val(pud) & pud_flags_mask(pud); 425 } 426 427 static inline pmdval_t pmd_pfn_mask(pmd_t pmd) 428 { 429 if (native_pmd_val(pmd) & _PAGE_PSE) 430 return PHYSICAL_PMD_PAGE_MASK; 431 else 432 return PTE_PFN_MASK; 433 } 434 435 static inline pmdval_t pmd_flags_mask(pmd_t pmd) 436 { 437 return ~pmd_pfn_mask(pmd); 438 } 439 440 static inline pmdval_t pmd_flags(pmd_t pmd) 441 { 442 return native_pmd_val(pmd) & pmd_flags_mask(pmd); 443 } 444 445 static inline pte_t native_make_pte(pteval_t val) 446 { 447 return (pte_t) { .pte = val }; 448 } 449 450 static inline pteval_t native_pte_val(pte_t pte) 451 { 452 return pte.pte; 453 } 454 455 static inline pteval_t pte_flags(pte_t pte) 456 { 457 return native_pte_val(pte) & PTE_FLAGS_MASK; 458 } 459 460 extern uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM]; 461 extern uint8_t __pte2cachemode_tbl[8]; 462 463 #define __pte2cm_idx(cb) \ 464 ((((cb) >> (_PAGE_BIT_PAT - 2)) & 4) | \ 465 (((cb) >> (_PAGE_BIT_PCD - 1)) & 2) | \ 466 (((cb) >> _PAGE_BIT_PWT) & 1)) 467 #define __cm_idx2pte(i) \ 468 ((((i) & 4) << (_PAGE_BIT_PAT - 2)) | \ 469 (((i) & 2) << (_PAGE_BIT_PCD - 1)) | \ 470 (((i) & 1) << _PAGE_BIT_PWT)) 471 472 static inline unsigned long cachemode2protval(enum page_cache_mode pcm) 473 { 474 if (likely(pcm == 0)) 475 return 0; 476 return __cachemode2pte_tbl[pcm]; 477 } 478 static inline pgprot_t cachemode2pgprot(enum page_cache_mode pcm) 479 { 480 return __pgprot(cachemode2protval(pcm)); 481 } 482 static inline enum page_cache_mode pgprot2cachemode(pgprot_t pgprot) 483 { 484 unsigned long masked; 485 486 masked = pgprot_val(pgprot) & _PAGE_CACHE_MASK; 487 if (likely(masked == 0)) 488 return 0; 489 return __pte2cachemode_tbl[__pte2cm_idx(masked)]; 490 } 491 static inline pgprot_t pgprot_4k_2_large(pgprot_t pgprot) 492 { 493 pgprotval_t val = pgprot_val(pgprot); 494 pgprot_t new; 495 496 pgprot_val(new) = (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) | 497 ((val & _PAGE_PAT) << (_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT)); 498 return new; 499 } 500 static inline pgprot_t pgprot_large_2_4k(pgprot_t pgprot) 501 { 502 pgprotval_t val = pgprot_val(pgprot); 503 pgprot_t new; 504 505 pgprot_val(new) = (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) | 506 ((val & _PAGE_PAT_LARGE) >> 507 (_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT)); 508 return new; 509 } 510 511 512 typedef struct page *pgtable_t; 513 514 extern pteval_t __supported_pte_mask; 515 extern pteval_t __default_kernel_pte_mask; 516 extern void set_nx(void); 517 extern int nx_enabled; 518 519 #define pgprot_writecombine pgprot_writecombine 520 extern pgprot_t pgprot_writecombine(pgprot_t prot); 521 522 #define pgprot_writethrough pgprot_writethrough 523 extern pgprot_t pgprot_writethrough(pgprot_t prot); 524 525 /* Indicate that x86 has its own track and untrack pfn vma functions */ 526 #define __HAVE_PFNMAP_TRACKING 527 528 #define __HAVE_PHYS_MEM_ACCESS_PROT 529 struct file; 530 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 531 unsigned long size, pgprot_t vma_prot); 532 533 /* Install a pte for a particular vaddr in kernel space. */ 534 void set_pte_vaddr(unsigned long vaddr, pte_t pte); 535 536 #ifdef CONFIG_X86_32 537 extern void native_pagetable_init(void); 538 #else 539 #define native_pagetable_init paging_init 540 #endif 541 542 struct seq_file; 543 extern void arch_report_meminfo(struct seq_file *m); 544 545 enum pg_level { 546 PG_LEVEL_NONE, 547 PG_LEVEL_4K, 548 PG_LEVEL_2M, 549 PG_LEVEL_1G, 550 PG_LEVEL_512G, 551 PG_LEVEL_NUM 552 }; 553 554 #ifdef CONFIG_PROC_FS 555 extern void update_page_count(int level, unsigned long pages); 556 #else 557 static inline void update_page_count(int level, unsigned long pages) { } 558 #endif 559 560 /* 561 * Helper function that returns the kernel pagetable entry controlling 562 * the virtual address 'address'. NULL means no pagetable entry present. 563 * NOTE: the return type is pte_t but if the pmd is PSE then we return it 564 * as a pte too. 565 */ 566 extern pte_t *lookup_address(unsigned long address, unsigned int *level); 567 extern pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long address, 568 unsigned int *level); 569 570 struct mm_struct; 571 extern pte_t *lookup_address_in_mm(struct mm_struct *mm, unsigned long address, 572 unsigned int *level); 573 extern pmd_t *lookup_pmd_address(unsigned long address); 574 extern phys_addr_t slow_virt_to_phys(void *__address); 575 extern int __init kernel_map_pages_in_pgd(pgd_t *pgd, u64 pfn, 576 unsigned long address, 577 unsigned numpages, 578 unsigned long page_flags); 579 extern int __init kernel_unmap_pages_in_pgd(pgd_t *pgd, unsigned long address, 580 unsigned long numpages); 581 #endif /* !__ASSEMBLY__ */ 582 583 #endif /* _ASM_X86_PGTABLE_DEFS_H */ 584