1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_PGTABLE_3LEVEL_H 3 #define _ASM_X86_PGTABLE_3LEVEL_H 4 5 /* 6 * Intel Physical Address Extension (PAE) Mode - three-level page 7 * tables on PPro+ CPUs. 8 * 9 * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com> 10 */ 11 12 #define pte_ERROR(e) \ 13 pr_err("%s:%d: bad pte %p(%08lx%08lx)\n", \ 14 __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low) 15 #define pmd_ERROR(e) \ 16 pr_err("%s:%d: bad pmd %p(%016Lx)\n", \ 17 __FILE__, __LINE__, &(e), pmd_val(e)) 18 #define pgd_ERROR(e) \ 19 pr_err("%s:%d: bad pgd %p(%016Lx)\n", \ 20 __FILE__, __LINE__, &(e), pgd_val(e)) 21 22 /* Rules for using set_pte: the pte being assigned *must* be 23 * either not present or in a state where the hardware will 24 * not attempt to update the pte. In places where this is 25 * not possible, use pte_get_and_clear to obtain the old pte 26 * value and then use set_pte to update it. -ben 27 */ 28 static inline void native_set_pte(pte_t *ptep, pte_t pte) 29 { 30 ptep->pte_high = pte.pte_high; 31 smp_wmb(); 32 ptep->pte_low = pte.pte_low; 33 } 34 35 #define pmd_read_atomic pmd_read_atomic 36 /* 37 * pte_offset_map_lock on 32bit PAE kernels was reading the pmd_t with 38 * a "*pmdp" dereference done by gcc. Problem is, in certain places 39 * where pte_offset_map_lock is called, concurrent page faults are 40 * allowed, if the mmap_sem is hold for reading. An example is mincore 41 * vs page faults vs MADV_DONTNEED. On the page fault side 42 * pmd_populate rightfully does a set_64bit, but if we're reading the 43 * pmd_t with a "*pmdp" on the mincore side, a SMP race can happen 44 * because gcc will not read the 64bit of the pmd atomically. To fix 45 * this all places running pmd_offset_map_lock() while holding the 46 * mmap_sem in read mode, shall read the pmdp pointer using this 47 * function to know if the pmd is null nor not, and in turn to know if 48 * they can run pmd_offset_map_lock or pmd_trans_huge or other pmd 49 * operations. 50 * 51 * Without THP if the mmap_sem is hold for reading, the pmd can only 52 * transition from null to not null while pmd_read_atomic runs. So 53 * we can always return atomic pmd values with this function. 54 * 55 * With THP if the mmap_sem is hold for reading, the pmd can become 56 * trans_huge or none or point to a pte (and in turn become "stable") 57 * at any time under pmd_read_atomic. We could read it really 58 * atomically here with a atomic64_read for the THP enabled case (and 59 * it would be a whole lot simpler), but to avoid using cmpxchg8b we 60 * only return an atomic pmdval if the low part of the pmdval is later 61 * found stable (i.e. pointing to a pte). And we're returning a none 62 * pmdval if the low part of the pmd is none. In some cases the high 63 * and low part of the pmdval returned may not be consistent if THP is 64 * enabled (the low part may point to previously mapped hugepage, 65 * while the high part may point to a more recently mapped hugepage), 66 * but pmd_none_or_trans_huge_or_clear_bad() only needs the low part 67 * of the pmd to be read atomically to decide if the pmd is unstable 68 * or not, with the only exception of when the low part of the pmd is 69 * zero in which case we return a none pmd. 70 */ 71 static inline pmd_t pmd_read_atomic(pmd_t *pmdp) 72 { 73 pmdval_t ret; 74 u32 *tmp = (u32 *)pmdp; 75 76 ret = (pmdval_t) (*tmp); 77 if (ret) { 78 /* 79 * If the low part is null, we must not read the high part 80 * or we can end up with a partial pmd. 81 */ 82 smp_rmb(); 83 ret |= ((pmdval_t)*(tmp + 1)) << 32; 84 } 85 86 return (pmd_t) { ret }; 87 } 88 89 static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte) 90 { 91 set_64bit((unsigned long long *)(ptep), native_pte_val(pte)); 92 } 93 94 static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd) 95 { 96 set_64bit((unsigned long long *)(pmdp), native_pmd_val(pmd)); 97 } 98 99 static inline void native_set_pud(pud_t *pudp, pud_t pud) 100 { 101 #ifdef CONFIG_PAGE_TABLE_ISOLATION 102 pud.p4d.pgd = pti_set_user_pgtbl(&pudp->p4d.pgd, pud.p4d.pgd); 103 #endif 104 set_64bit((unsigned long long *)(pudp), native_pud_val(pud)); 105 } 106 107 /* 108 * For PTEs and PDEs, we must clear the P-bit first when clearing a page table 109 * entry, so clear the bottom half first and enforce ordering with a compiler 110 * barrier. 111 */ 112 static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr, 113 pte_t *ptep) 114 { 115 ptep->pte_low = 0; 116 smp_wmb(); 117 ptep->pte_high = 0; 118 } 119 120 static inline void native_pmd_clear(pmd_t *pmd) 121 { 122 u32 *tmp = (u32 *)pmd; 123 *tmp = 0; 124 smp_wmb(); 125 *(tmp + 1) = 0; 126 } 127 128 static inline void native_pud_clear(pud_t *pudp) 129 { 130 } 131 132 static inline void pud_clear(pud_t *pudp) 133 { 134 set_pud(pudp, __pud(0)); 135 136 /* 137 * According to Intel App note "TLBs, Paging-Structure Caches, 138 * and Their Invalidation", April 2007, document 317080-001, 139 * section 8.1: in PAE mode we explicitly have to flush the 140 * TLB via cr3 if the top-level pgd is changed... 141 * 142 * Currently all places where pud_clear() is called either have 143 * flush_tlb_mm() followed or don't need TLB flush (x86_64 code or 144 * pud_clear_bad()), so we don't need TLB flush here. 145 */ 146 } 147 148 #ifdef CONFIG_SMP 149 static inline pte_t native_ptep_get_and_clear(pte_t *ptep) 150 { 151 pte_t res; 152 153 /* xchg acts as a barrier before the setting of the high bits */ 154 res.pte_low = xchg(&ptep->pte_low, 0); 155 res.pte_high = ptep->pte_high; 156 ptep->pte_high = 0; 157 158 return res; 159 } 160 #else 161 #define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp) 162 #endif 163 164 union split_pmd { 165 struct { 166 u32 pmd_low; 167 u32 pmd_high; 168 }; 169 pmd_t pmd; 170 }; 171 172 #ifdef CONFIG_SMP 173 static inline pmd_t native_pmdp_get_and_clear(pmd_t *pmdp) 174 { 175 union split_pmd res, *orig = (union split_pmd *)pmdp; 176 177 /* xchg acts as a barrier before setting of the high bits */ 178 res.pmd_low = xchg(&orig->pmd_low, 0); 179 res.pmd_high = orig->pmd_high; 180 orig->pmd_high = 0; 181 182 return res.pmd; 183 } 184 #else 185 #define native_pmdp_get_and_clear(xp) native_local_pmdp_get_and_clear(xp) 186 #endif 187 188 #ifndef pmdp_establish 189 #define pmdp_establish pmdp_establish 190 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 191 unsigned long address, pmd_t *pmdp, pmd_t pmd) 192 { 193 pmd_t old; 194 195 /* 196 * If pmd has present bit cleared we can get away without expensive 197 * cmpxchg64: we can update pmdp half-by-half without racing with 198 * anybody. 199 */ 200 if (!(pmd_val(pmd) & _PAGE_PRESENT)) { 201 union split_pmd old, new, *ptr; 202 203 ptr = (union split_pmd *)pmdp; 204 205 new.pmd = pmd; 206 207 /* xchg acts as a barrier before setting of the high bits */ 208 old.pmd_low = xchg(&ptr->pmd_low, new.pmd_low); 209 old.pmd_high = ptr->pmd_high; 210 ptr->pmd_high = new.pmd_high; 211 return old.pmd; 212 } 213 214 do { 215 old = *pmdp; 216 } while (cmpxchg64(&pmdp->pmd, old.pmd, pmd.pmd) != old.pmd); 217 218 return old; 219 } 220 #endif 221 222 #ifdef CONFIG_SMP 223 union split_pud { 224 struct { 225 u32 pud_low; 226 u32 pud_high; 227 }; 228 pud_t pud; 229 }; 230 231 static inline pud_t native_pudp_get_and_clear(pud_t *pudp) 232 { 233 union split_pud res, *orig = (union split_pud *)pudp; 234 235 #ifdef CONFIG_PAGE_TABLE_ISOLATION 236 pti_set_user_pgtbl(&pudp->p4d.pgd, __pgd(0)); 237 #endif 238 239 /* xchg acts as a barrier before setting of the high bits */ 240 res.pud_low = xchg(&orig->pud_low, 0); 241 res.pud_high = orig->pud_high; 242 orig->pud_high = 0; 243 244 return res.pud; 245 } 246 #else 247 #define native_pudp_get_and_clear(xp) native_local_pudp_get_and_clear(xp) 248 #endif 249 250 /* Encode and de-code a swap entry */ 251 #define SWP_TYPE_BITS 5 252 253 #define SWP_OFFSET_FIRST_BIT (_PAGE_BIT_PROTNONE + 1) 254 255 /* We always extract/encode the offset by shifting it all the way up, and then down again */ 256 #define SWP_OFFSET_SHIFT (SWP_OFFSET_FIRST_BIT + SWP_TYPE_BITS) 257 258 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > 5) 259 #define __swp_type(x) (((x).val) & 0x1f) 260 #define __swp_offset(x) ((x).val >> 5) 261 #define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) << 5}) 262 263 /* 264 * Normally, __swp_entry() converts from arch-independent swp_entry_t to 265 * arch-dependent swp_entry_t, and __swp_entry_to_pte() just stores the result 266 * to pte. But here we have 32bit swp_entry_t and 64bit pte, and need to use the 267 * whole 64 bits. Thus, we shift the "real" arch-dependent conversion to 268 * __swp_entry_to_pte() through the following helper macro based on 64bit 269 * __swp_entry(). 270 */ 271 #define __swp_pteval_entry(type, offset) ((pteval_t) { \ 272 (~(pteval_t)(offset) << SWP_OFFSET_SHIFT >> SWP_TYPE_BITS) \ 273 | ((pteval_t)(type) << (64 - SWP_TYPE_BITS)) }) 274 275 #define __swp_entry_to_pte(x) ((pte_t){ .pte = \ 276 __swp_pteval_entry(__swp_type(x), __swp_offset(x)) }) 277 /* 278 * Analogically, __pte_to_swp_entry() doesn't just extract the arch-dependent 279 * swp_entry_t, but also has to convert it from 64bit to the 32bit 280 * intermediate representation, using the following macros based on 64bit 281 * __swp_type() and __swp_offset(). 282 */ 283 #define __pteval_swp_type(x) ((unsigned long)((x).pte >> (64 - SWP_TYPE_BITS))) 284 #define __pteval_swp_offset(x) ((unsigned long)(~((x).pte) << SWP_TYPE_BITS >> SWP_OFFSET_SHIFT)) 285 286 #define __pte_to_swp_entry(pte) (__swp_entry(__pteval_swp_type(pte), \ 287 __pteval_swp_offset(pte))) 288 289 #define gup_get_pte gup_get_pte 290 /* 291 * WARNING: only to be used in the get_user_pages_fast() implementation. 292 * 293 * With get_user_pages_fast(), we walk down the pagetables without taking 294 * any locks. For this we would like to load the pointers atomically, 295 * but that is not possible (without expensive cmpxchg8b) on PAE. What 296 * we do have is the guarantee that a PTE will only either go from not 297 * present to present, or present to not present or both -- it will not 298 * switch to a completely different present page without a TLB flush in 299 * between; something that we are blocking by holding interrupts off. 300 * 301 * Setting ptes from not present to present goes: 302 * 303 * ptep->pte_high = h; 304 * smp_wmb(); 305 * ptep->pte_low = l; 306 * 307 * And present to not present goes: 308 * 309 * ptep->pte_low = 0; 310 * smp_wmb(); 311 * ptep->pte_high = 0; 312 * 313 * We must ensure here that the load of pte_low sees 'l' iff pte_high 314 * sees 'h'. We load pte_high *after* loading pte_low, which ensures we 315 * don't see an older value of pte_high. *Then* we recheck pte_low, 316 * which ensures that we haven't picked up a changed pte high. We might 317 * have gotten rubbish values from pte_low and pte_high, but we are 318 * guaranteed that pte_low will not have the present bit set *unless* 319 * it is 'l'. Because get_user_pages_fast() only operates on present ptes 320 * we're safe. 321 */ 322 static inline pte_t gup_get_pte(pte_t *ptep) 323 { 324 pte_t pte; 325 326 do { 327 pte.pte_low = ptep->pte_low; 328 smp_rmb(); 329 pte.pte_high = ptep->pte_high; 330 smp_rmb(); 331 } while (unlikely(pte.pte_low != ptep->pte_low)); 332 333 return pte; 334 } 335 336 #include <asm/pgtable-invert.h> 337 338 #endif /* _ASM_X86_PGTABLE_3LEVEL_H */ 339