1 /* 2 * Netburst Perfomance Events (P4, old Xeon) 3 */ 4 5 #ifndef PERF_EVENT_P4_H 6 #define PERF_EVENT_P4_H 7 8 #include <linux/cpu.h> 9 #include <linux/bitops.h> 10 11 /* 12 * NetBurst has perfomance MSRs shared between 13 * threads if HT is turned on, ie for both logical 14 * processors (mem: in turn in Atom with HT support 15 * perf-MSRs are not shared and every thread has its 16 * own perf-MSRs set) 17 */ 18 #define ARCH_P4_TOTAL_ESCR (46) 19 #define ARCH_P4_RESERVED_ESCR (2) /* IQ_ESCR(0,1) not always present */ 20 #define ARCH_P4_MAX_ESCR (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR) 21 #define ARCH_P4_MAX_CCCR (18) 22 23 #define P4_ESCR_EVENT_MASK 0x7e000000U 24 #define P4_ESCR_EVENT_SHIFT 25 25 #define P4_ESCR_EVENTMASK_MASK 0x01fffe00U 26 #define P4_ESCR_EVENTMASK_SHIFT 9 27 #define P4_ESCR_TAG_MASK 0x000001e0U 28 #define P4_ESCR_TAG_SHIFT 5 29 #define P4_ESCR_TAG_ENABLE 0x00000010U 30 #define P4_ESCR_T0_OS 0x00000008U 31 #define P4_ESCR_T0_USR 0x00000004U 32 #define P4_ESCR_T1_OS 0x00000002U 33 #define P4_ESCR_T1_USR 0x00000001U 34 35 #define P4_ESCR_EVENT(v) ((v) << P4_ESCR_EVENT_SHIFT) 36 #define P4_ESCR_EMASK(v) ((v) << P4_ESCR_EVENTMASK_SHIFT) 37 #define P4_ESCR_TAG(v) ((v) << P4_ESCR_TAG_SHIFT) 38 39 #define P4_CCCR_OVF 0x80000000U 40 #define P4_CCCR_CASCADE 0x40000000U 41 #define P4_CCCR_OVF_PMI_T0 0x04000000U 42 #define P4_CCCR_OVF_PMI_T1 0x08000000U 43 #define P4_CCCR_FORCE_OVF 0x02000000U 44 #define P4_CCCR_EDGE 0x01000000U 45 #define P4_CCCR_THRESHOLD_MASK 0x00f00000U 46 #define P4_CCCR_THRESHOLD_SHIFT 20 47 #define P4_CCCR_COMPLEMENT 0x00080000U 48 #define P4_CCCR_COMPARE 0x00040000U 49 #define P4_CCCR_ESCR_SELECT_MASK 0x0000e000U 50 #define P4_CCCR_ESCR_SELECT_SHIFT 13 51 #define P4_CCCR_ENABLE 0x00001000U 52 #define P4_CCCR_THREAD_SINGLE 0x00010000U 53 #define P4_CCCR_THREAD_BOTH 0x00020000U 54 #define P4_CCCR_THREAD_ANY 0x00030000U 55 #define P4_CCCR_RESERVED 0x00000fffU 56 57 #define P4_CCCR_THRESHOLD(v) ((v) << P4_CCCR_THRESHOLD_SHIFT) 58 #define P4_CCCR_ESEL(v) ((v) << P4_CCCR_ESCR_SELECT_SHIFT) 59 60 #define P4_GEN_ESCR_EMASK(class, name, bit) \ 61 class##__##name = ((1 << bit) << P4_ESCR_EVENTMASK_SHIFT) 62 #define P4_ESCR_EMASK_BIT(class, name) class##__##name 63 64 /* 65 * config field is 64bit width and consists of 66 * HT << 63 | ESCR << 32 | CCCR 67 * where HT is HyperThreading bit (since ESCR 68 * has it reserved we may use it for own purpose) 69 * 70 * note that this is NOT the addresses of respective 71 * ESCR and CCCR but rather an only packed value should 72 * be unpacked and written to a proper addresses 73 * 74 * the base idea is to pack as much info as possible 75 */ 76 #define p4_config_pack_escr(v) (((u64)(v)) << 32) 77 #define p4_config_pack_cccr(v) (((u64)(v)) & 0xffffffffULL) 78 #define p4_config_unpack_escr(v) (((u64)(v)) >> 32) 79 #define p4_config_unpack_cccr(v) (((u64)(v)) & 0xffffffffULL) 80 81 #define p4_config_unpack_emask(v) \ 82 ({ \ 83 u32 t = p4_config_unpack_escr((v)); \ 84 t = t & P4_ESCR_EVENTMASK_MASK; \ 85 t = t >> P4_ESCR_EVENTMASK_SHIFT; \ 86 t; \ 87 }) 88 89 #define p4_config_unpack_event(v) \ 90 ({ \ 91 u32 t = p4_config_unpack_escr((v)); \ 92 t = t & P4_ESCR_EVENT_MASK; \ 93 t = t >> P4_ESCR_EVENT_SHIFT; \ 94 t; \ 95 }) 96 97 #define P4_CONFIG_HT_SHIFT 63 98 #define P4_CONFIG_HT (1ULL << P4_CONFIG_HT_SHIFT) 99 100 /* 101 * The bits we allow to pass for RAW events 102 */ 103 #define P4_CONFIG_MASK_ESCR \ 104 P4_ESCR_EVENT_MASK | \ 105 P4_ESCR_EVENTMASK_MASK | \ 106 P4_ESCR_TAG_MASK | \ 107 P4_ESCR_TAG_ENABLE 108 109 #define P4_CONFIG_MASK_CCCR \ 110 P4_CCCR_EDGE | \ 111 P4_CCCR_THRESHOLD_MASK | \ 112 P4_CCCR_COMPLEMENT | \ 113 P4_CCCR_COMPARE | \ 114 P4_CCCR_THREAD_ANY | \ 115 P4_CCCR_RESERVED 116 117 /* some dangerous bits are reserved for kernel internals */ 118 #define P4_CONFIG_MASK \ 119 (p4_config_pack_escr(P4_CONFIG_MASK_ESCR)) | \ 120 (p4_config_pack_cccr(P4_CONFIG_MASK_CCCR)) 121 122 static inline bool p4_is_event_cascaded(u64 config) 123 { 124 u32 cccr = p4_config_unpack_cccr(config); 125 return !!(cccr & P4_CCCR_CASCADE); 126 } 127 128 static inline int p4_ht_config_thread(u64 config) 129 { 130 return !!(config & P4_CONFIG_HT); 131 } 132 133 static inline u64 p4_set_ht_bit(u64 config) 134 { 135 return config | P4_CONFIG_HT; 136 } 137 138 static inline u64 p4_clear_ht_bit(u64 config) 139 { 140 return config & ~P4_CONFIG_HT; 141 } 142 143 static inline int p4_ht_active(void) 144 { 145 #ifdef CONFIG_SMP 146 return smp_num_siblings > 1; 147 #endif 148 return 0; 149 } 150 151 static inline int p4_ht_thread(int cpu) 152 { 153 #ifdef CONFIG_SMP 154 if (smp_num_siblings == 2) 155 return cpu != cpumask_first(__get_cpu_var(cpu_sibling_map)); 156 #endif 157 return 0; 158 } 159 160 static inline int p4_should_swap_ts(u64 config, int cpu) 161 { 162 return p4_ht_config_thread(config) ^ p4_ht_thread(cpu); 163 } 164 165 static inline u32 p4_default_cccr_conf(int cpu) 166 { 167 /* 168 * Note that P4_CCCR_THREAD_ANY is "required" on 169 * non-HT machines (on HT machines we count TS events 170 * regardless the state of second logical processor 171 */ 172 u32 cccr = P4_CCCR_THREAD_ANY; 173 174 if (!p4_ht_thread(cpu)) 175 cccr |= P4_CCCR_OVF_PMI_T0; 176 else 177 cccr |= P4_CCCR_OVF_PMI_T1; 178 179 return cccr; 180 } 181 182 static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr) 183 { 184 u32 escr = 0; 185 186 if (!p4_ht_thread(cpu)) { 187 if (!exclude_os) 188 escr |= P4_ESCR_T0_OS; 189 if (!exclude_usr) 190 escr |= P4_ESCR_T0_USR; 191 } else { 192 if (!exclude_os) 193 escr |= P4_ESCR_T1_OS; 194 if (!exclude_usr) 195 escr |= P4_ESCR_T1_USR; 196 } 197 198 return escr; 199 } 200 201 /* 202 * This are the events which should be used in "Event Select" 203 * field of ESCR register, they are like unique keys which allow 204 * the kernel to determinate which CCCR and COUNTER should be 205 * used to track an event 206 */ 207 enum P4_EVENTS { 208 P4_EVENT_TC_DELIVER_MODE, 209 P4_EVENT_BPU_FETCH_REQUEST, 210 P4_EVENT_ITLB_REFERENCE, 211 P4_EVENT_MEMORY_CANCEL, 212 P4_EVENT_MEMORY_COMPLETE, 213 P4_EVENT_LOAD_PORT_REPLAY, 214 P4_EVENT_STORE_PORT_REPLAY, 215 P4_EVENT_MOB_LOAD_REPLAY, 216 P4_EVENT_PAGE_WALK_TYPE, 217 P4_EVENT_BSQ_CACHE_REFERENCE, 218 P4_EVENT_IOQ_ALLOCATION, 219 P4_EVENT_IOQ_ACTIVE_ENTRIES, 220 P4_EVENT_FSB_DATA_ACTIVITY, 221 P4_EVENT_BSQ_ALLOCATION, 222 P4_EVENT_BSQ_ACTIVE_ENTRIES, 223 P4_EVENT_SSE_INPUT_ASSIST, 224 P4_EVENT_PACKED_SP_UOP, 225 P4_EVENT_PACKED_DP_UOP, 226 P4_EVENT_SCALAR_SP_UOP, 227 P4_EVENT_SCALAR_DP_UOP, 228 P4_EVENT_64BIT_MMX_UOP, 229 P4_EVENT_128BIT_MMX_UOP, 230 P4_EVENT_X87_FP_UOP, 231 P4_EVENT_TC_MISC, 232 P4_EVENT_GLOBAL_POWER_EVENTS, 233 P4_EVENT_TC_MS_XFER, 234 P4_EVENT_UOP_QUEUE_WRITES, 235 P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, 236 P4_EVENT_RETIRED_BRANCH_TYPE, 237 P4_EVENT_RESOURCE_STALL, 238 P4_EVENT_WC_BUFFER, 239 P4_EVENT_B2B_CYCLES, 240 P4_EVENT_BNR, 241 P4_EVENT_SNOOP, 242 P4_EVENT_RESPONSE, 243 P4_EVENT_FRONT_END_EVENT, 244 P4_EVENT_EXECUTION_EVENT, 245 P4_EVENT_REPLAY_EVENT, 246 P4_EVENT_INSTR_RETIRED, 247 P4_EVENT_UOPS_RETIRED, 248 P4_EVENT_UOP_TYPE, 249 P4_EVENT_BRANCH_RETIRED, 250 P4_EVENT_MISPRED_BRANCH_RETIRED, 251 P4_EVENT_X87_ASSIST, 252 P4_EVENT_MACHINE_CLEAR, 253 P4_EVENT_INSTR_COMPLETED, 254 }; 255 256 #define P4_OPCODE(event) event##_OPCODE 257 #define P4_OPCODE_ESEL(opcode) ((opcode & 0x00ff) >> 0) 258 #define P4_OPCODE_EVNT(opcode) ((opcode & 0xff00) >> 8) 259 #define P4_OPCODE_PACK(event, sel) (((event) << 8) | sel) 260 261 /* 262 * Comments below the event represent ESCR restriction 263 * for this event and counter index per ESCR 264 * 265 * MSR_P4_IQ_ESCR0 and MSR_P4_IQ_ESCR1 are available only on early 266 * processor builds (family 0FH, models 01H-02H). These MSRs 267 * are not available on later versions, so that we don't use 268 * them completely 269 * 270 * Also note that CCCR1 do not have P4_CCCR_ENABLE bit properly 271 * working so that we should not use this CCCR and respective 272 * counter as result 273 */ 274 enum P4_EVENT_OPCODES { 275 P4_OPCODE(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), 276 /* 277 * MSR_P4_TC_ESCR0: 4, 5 278 * MSR_P4_TC_ESCR1: 6, 7 279 */ 280 281 P4_OPCODE(P4_EVENT_BPU_FETCH_REQUEST) = P4_OPCODE_PACK(0x03, 0x00), 282 /* 283 * MSR_P4_BPU_ESCR0: 0, 1 284 * MSR_P4_BPU_ESCR1: 2, 3 285 */ 286 287 P4_OPCODE(P4_EVENT_ITLB_REFERENCE) = P4_OPCODE_PACK(0x18, 0x03), 288 /* 289 * MSR_P4_ITLB_ESCR0: 0, 1 290 * MSR_P4_ITLB_ESCR1: 2, 3 291 */ 292 293 P4_OPCODE(P4_EVENT_MEMORY_CANCEL) = P4_OPCODE_PACK(0x02, 0x05), 294 /* 295 * MSR_P4_DAC_ESCR0: 8, 9 296 * MSR_P4_DAC_ESCR1: 10, 11 297 */ 298 299 P4_OPCODE(P4_EVENT_MEMORY_COMPLETE) = P4_OPCODE_PACK(0x08, 0x02), 300 /* 301 * MSR_P4_SAAT_ESCR0: 8, 9 302 * MSR_P4_SAAT_ESCR1: 10, 11 303 */ 304 305 P4_OPCODE(P4_EVENT_LOAD_PORT_REPLAY) = P4_OPCODE_PACK(0x04, 0x02), 306 /* 307 * MSR_P4_SAAT_ESCR0: 8, 9 308 * MSR_P4_SAAT_ESCR1: 10, 11 309 */ 310 311 P4_OPCODE(P4_EVENT_STORE_PORT_REPLAY) = P4_OPCODE_PACK(0x05, 0x02), 312 /* 313 * MSR_P4_SAAT_ESCR0: 8, 9 314 * MSR_P4_SAAT_ESCR1: 10, 11 315 */ 316 317 P4_OPCODE(P4_EVENT_MOB_LOAD_REPLAY) = P4_OPCODE_PACK(0x03, 0x02), 318 /* 319 * MSR_P4_MOB_ESCR0: 0, 1 320 * MSR_P4_MOB_ESCR1: 2, 3 321 */ 322 323 P4_OPCODE(P4_EVENT_PAGE_WALK_TYPE) = P4_OPCODE_PACK(0x01, 0x04), 324 /* 325 * MSR_P4_PMH_ESCR0: 0, 1 326 * MSR_P4_PMH_ESCR1: 2, 3 327 */ 328 329 P4_OPCODE(P4_EVENT_BSQ_CACHE_REFERENCE) = P4_OPCODE_PACK(0x0c, 0x07), 330 /* 331 * MSR_P4_BSU_ESCR0: 0, 1 332 * MSR_P4_BSU_ESCR1: 2, 3 333 */ 334 335 P4_OPCODE(P4_EVENT_IOQ_ALLOCATION) = P4_OPCODE_PACK(0x03, 0x06), 336 /* 337 * MSR_P4_FSB_ESCR0: 0, 1 338 * MSR_P4_FSB_ESCR1: 2, 3 339 */ 340 341 P4_OPCODE(P4_EVENT_IOQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x1a, 0x06), 342 /* 343 * MSR_P4_FSB_ESCR1: 2, 3 344 */ 345 346 P4_OPCODE(P4_EVENT_FSB_DATA_ACTIVITY) = P4_OPCODE_PACK(0x17, 0x06), 347 /* 348 * MSR_P4_FSB_ESCR0: 0, 1 349 * MSR_P4_FSB_ESCR1: 2, 3 350 */ 351 352 P4_OPCODE(P4_EVENT_BSQ_ALLOCATION) = P4_OPCODE_PACK(0x05, 0x07), 353 /* 354 * MSR_P4_BSU_ESCR0: 0, 1 355 */ 356 357 P4_OPCODE(P4_EVENT_BSQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x06, 0x07), 358 /* 359 * NOTE: no ESCR name in docs, it's guessed 360 * MSR_P4_BSU_ESCR1: 2, 3 361 */ 362 363 P4_OPCODE(P4_EVENT_SSE_INPUT_ASSIST) = P4_OPCODE_PACK(0x34, 0x01), 364 /* 365 * MSR_P4_FIRM_ESCR0: 8, 9 366 * MSR_P4_FIRM_ESCR1: 10, 11 367 */ 368 369 P4_OPCODE(P4_EVENT_PACKED_SP_UOP) = P4_OPCODE_PACK(0x08, 0x01), 370 /* 371 * MSR_P4_FIRM_ESCR0: 8, 9 372 * MSR_P4_FIRM_ESCR1: 10, 11 373 */ 374 375 P4_OPCODE(P4_EVENT_PACKED_DP_UOP) = P4_OPCODE_PACK(0x0c, 0x01), 376 /* 377 * MSR_P4_FIRM_ESCR0: 8, 9 378 * MSR_P4_FIRM_ESCR1: 10, 11 379 */ 380 381 P4_OPCODE(P4_EVENT_SCALAR_SP_UOP) = P4_OPCODE_PACK(0x0a, 0x01), 382 /* 383 * MSR_P4_FIRM_ESCR0: 8, 9 384 * MSR_P4_FIRM_ESCR1: 10, 11 385 */ 386 387 P4_OPCODE(P4_EVENT_SCALAR_DP_UOP) = P4_OPCODE_PACK(0x0e, 0x01), 388 /* 389 * MSR_P4_FIRM_ESCR0: 8, 9 390 * MSR_P4_FIRM_ESCR1: 10, 11 391 */ 392 393 P4_OPCODE(P4_EVENT_64BIT_MMX_UOP) = P4_OPCODE_PACK(0x02, 0x01), 394 /* 395 * MSR_P4_FIRM_ESCR0: 8, 9 396 * MSR_P4_FIRM_ESCR1: 10, 11 397 */ 398 399 P4_OPCODE(P4_EVENT_128BIT_MMX_UOP) = P4_OPCODE_PACK(0x1a, 0x01), 400 /* 401 * MSR_P4_FIRM_ESCR0: 8, 9 402 * MSR_P4_FIRM_ESCR1: 10, 11 403 */ 404 405 P4_OPCODE(P4_EVENT_X87_FP_UOP) = P4_OPCODE_PACK(0x04, 0x01), 406 /* 407 * MSR_P4_FIRM_ESCR0: 8, 9 408 * MSR_P4_FIRM_ESCR1: 10, 11 409 */ 410 411 P4_OPCODE(P4_EVENT_TC_MISC) = P4_OPCODE_PACK(0x06, 0x01), 412 /* 413 * MSR_P4_TC_ESCR0: 4, 5 414 * MSR_P4_TC_ESCR1: 6, 7 415 */ 416 417 P4_OPCODE(P4_EVENT_GLOBAL_POWER_EVENTS) = P4_OPCODE_PACK(0x13, 0x06), 418 /* 419 * MSR_P4_FSB_ESCR0: 0, 1 420 * MSR_P4_FSB_ESCR1: 2, 3 421 */ 422 423 P4_OPCODE(P4_EVENT_TC_MS_XFER) = P4_OPCODE_PACK(0x05, 0x00), 424 /* 425 * MSR_P4_MS_ESCR0: 4, 5 426 * MSR_P4_MS_ESCR1: 6, 7 427 */ 428 429 P4_OPCODE(P4_EVENT_UOP_QUEUE_WRITES) = P4_OPCODE_PACK(0x09, 0x00), 430 /* 431 * MSR_P4_MS_ESCR0: 4, 5 432 * MSR_P4_MS_ESCR1: 6, 7 433 */ 434 435 P4_OPCODE(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x05, 0x02), 436 /* 437 * MSR_P4_TBPU_ESCR0: 4, 5 438 * MSR_P4_TBPU_ESCR1: 6, 7 439 */ 440 441 P4_OPCODE(P4_EVENT_RETIRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x04, 0x02), 442 /* 443 * MSR_P4_TBPU_ESCR0: 4, 5 444 * MSR_P4_TBPU_ESCR1: 6, 7 445 */ 446 447 P4_OPCODE(P4_EVENT_RESOURCE_STALL) = P4_OPCODE_PACK(0x01, 0x01), 448 /* 449 * MSR_P4_ALF_ESCR0: 12, 13, 16 450 * MSR_P4_ALF_ESCR1: 14, 15, 17 451 */ 452 453 P4_OPCODE(P4_EVENT_WC_BUFFER) = P4_OPCODE_PACK(0x05, 0x05), 454 /* 455 * MSR_P4_DAC_ESCR0: 8, 9 456 * MSR_P4_DAC_ESCR1: 10, 11 457 */ 458 459 P4_OPCODE(P4_EVENT_B2B_CYCLES) = P4_OPCODE_PACK(0x16, 0x03), 460 /* 461 * MSR_P4_FSB_ESCR0: 0, 1 462 * MSR_P4_FSB_ESCR1: 2, 3 463 */ 464 465 P4_OPCODE(P4_EVENT_BNR) = P4_OPCODE_PACK(0x08, 0x03), 466 /* 467 * MSR_P4_FSB_ESCR0: 0, 1 468 * MSR_P4_FSB_ESCR1: 2, 3 469 */ 470 471 P4_OPCODE(P4_EVENT_SNOOP) = P4_OPCODE_PACK(0x06, 0x03), 472 /* 473 * MSR_P4_FSB_ESCR0: 0, 1 474 * MSR_P4_FSB_ESCR1: 2, 3 475 */ 476 477 P4_OPCODE(P4_EVENT_RESPONSE) = P4_OPCODE_PACK(0x04, 0x03), 478 /* 479 * MSR_P4_FSB_ESCR0: 0, 1 480 * MSR_P4_FSB_ESCR1: 2, 3 481 */ 482 483 P4_OPCODE(P4_EVENT_FRONT_END_EVENT) = P4_OPCODE_PACK(0x08, 0x05), 484 /* 485 * MSR_P4_CRU_ESCR2: 12, 13, 16 486 * MSR_P4_CRU_ESCR3: 14, 15, 17 487 */ 488 489 P4_OPCODE(P4_EVENT_EXECUTION_EVENT) = P4_OPCODE_PACK(0x0c, 0x05), 490 /* 491 * MSR_P4_CRU_ESCR2: 12, 13, 16 492 * MSR_P4_CRU_ESCR3: 14, 15, 17 493 */ 494 495 P4_OPCODE(P4_EVENT_REPLAY_EVENT) = P4_OPCODE_PACK(0x09, 0x05), 496 /* 497 * MSR_P4_CRU_ESCR2: 12, 13, 16 498 * MSR_P4_CRU_ESCR3: 14, 15, 17 499 */ 500 501 P4_OPCODE(P4_EVENT_INSTR_RETIRED) = P4_OPCODE_PACK(0x02, 0x04), 502 /* 503 * MSR_P4_CRU_ESCR0: 12, 13, 16 504 * MSR_P4_CRU_ESCR1: 14, 15, 17 505 */ 506 507 P4_OPCODE(P4_EVENT_UOPS_RETIRED) = P4_OPCODE_PACK(0x01, 0x04), 508 /* 509 * MSR_P4_CRU_ESCR0: 12, 13, 16 510 * MSR_P4_CRU_ESCR1: 14, 15, 17 511 */ 512 513 P4_OPCODE(P4_EVENT_UOP_TYPE) = P4_OPCODE_PACK(0x02, 0x02), 514 /* 515 * MSR_P4_RAT_ESCR0: 12, 13, 16 516 * MSR_P4_RAT_ESCR1: 14, 15, 17 517 */ 518 519 P4_OPCODE(P4_EVENT_BRANCH_RETIRED) = P4_OPCODE_PACK(0x06, 0x05), 520 /* 521 * MSR_P4_CRU_ESCR2: 12, 13, 16 522 * MSR_P4_CRU_ESCR3: 14, 15, 17 523 */ 524 525 P4_OPCODE(P4_EVENT_MISPRED_BRANCH_RETIRED) = P4_OPCODE_PACK(0x03, 0x04), 526 /* 527 * MSR_P4_CRU_ESCR0: 12, 13, 16 528 * MSR_P4_CRU_ESCR1: 14, 15, 17 529 */ 530 531 P4_OPCODE(P4_EVENT_X87_ASSIST) = P4_OPCODE_PACK(0x03, 0x05), 532 /* 533 * MSR_P4_CRU_ESCR2: 12, 13, 16 534 * MSR_P4_CRU_ESCR3: 14, 15, 17 535 */ 536 537 P4_OPCODE(P4_EVENT_MACHINE_CLEAR) = P4_OPCODE_PACK(0x02, 0x05), 538 /* 539 * MSR_P4_CRU_ESCR2: 12, 13, 16 540 * MSR_P4_CRU_ESCR3: 14, 15, 17 541 */ 542 543 P4_OPCODE(P4_EVENT_INSTR_COMPLETED) = P4_OPCODE_PACK(0x07, 0x04), 544 /* 545 * MSR_P4_CRU_ESCR0: 12, 13, 16 546 * MSR_P4_CRU_ESCR1: 14, 15, 17 547 */ 548 }; 549 550 /* 551 * a caller should use P4_ESCR_EMASK_NAME helper to 552 * pick the EventMask needed, for example 553 * 554 * P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, DD) 555 */ 556 enum P4_ESCR_EMASKS { 557 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DD, 0), 558 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DB, 1), 559 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DI, 2), 560 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BD, 3), 561 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BB, 4), 562 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BI, 5), 563 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, ID, 6), 564 565 P4_GEN_ESCR_EMASK(P4_EVENT_BPU_FETCH_REQUEST, TCMISS, 0), 566 567 P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT, 0), 568 P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, MISS, 1), 569 P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT_UK, 2), 570 571 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, ST_RB_FULL, 2), 572 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, 64K_CONF, 3), 573 574 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, LSC, 0), 575 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, SSC, 1), 576 577 P4_GEN_ESCR_EMASK(P4_EVENT_LOAD_PORT_REPLAY, SPLIT_LD, 1), 578 579 P4_GEN_ESCR_EMASK(P4_EVENT_STORE_PORT_REPLAY, SPLIT_ST, 1), 580 581 P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STA, 1), 582 P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STD, 3), 583 P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, PARTIAL_DATA, 4), 584 P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, UNALGN_ADDR, 5), 585 586 P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, DTMISS, 0), 587 P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, ITMISS, 1), 588 589 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS, 0), 590 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE, 1), 591 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM, 2), 592 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS, 3), 593 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE, 4), 594 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM, 5), 595 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS, 8), 596 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS, 9), 597 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS, 10), 598 599 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, DEFAULT, 0), 600 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_READ, 5), 601 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_WRITE, 6), 602 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_UC, 7), 603 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WC, 8), 604 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WT, 9), 605 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WP, 10), 606 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WB, 11), 607 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OWN, 13), 608 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OTHER, 14), 609 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, PREFETCH, 15), 610 611 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, DEFAULT, 0), 612 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_READ, 5), 613 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_WRITE, 6), 614 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_UC, 7), 615 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WC, 8), 616 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WT, 9), 617 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WP, 10), 618 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WB, 11), 619 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OWN, 13), 620 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OTHER, 14), 621 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, PREFETCH, 15), 622 623 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_DRV, 0), 624 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OWN, 1), 625 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OTHER, 2), 626 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_DRV, 3), 627 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OWN, 4), 628 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OTHER, 5), 629 630 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE0, 0), 631 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE1, 1), 632 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN0, 2), 633 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN1, 3), 634 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_IO_TYPE, 5), 635 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LOCK_TYPE, 6), 636 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_CACHE_TYPE, 7), 637 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_SPLIT_TYPE, 8), 638 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_DEM_TYPE, 9), 639 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_ORD_TYPE, 10), 640 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE0, 11), 641 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE1, 12), 642 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE2, 13), 643 644 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE0, 0), 645 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE1, 1), 646 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN0, 2), 647 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN1, 3), 648 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_IO_TYPE, 5), 649 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LOCK_TYPE, 6), 650 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_CACHE_TYPE, 7), 651 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_SPLIT_TYPE, 8), 652 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_DEM_TYPE, 9), 653 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_ORD_TYPE, 10), 654 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE0, 11), 655 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE1, 12), 656 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE2, 13), 657 658 P4_GEN_ESCR_EMASK(P4_EVENT_SSE_INPUT_ASSIST, ALL, 15), 659 660 P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_SP_UOP, ALL, 15), 661 662 P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_DP_UOP, ALL, 15), 663 664 P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_SP_UOP, ALL, 15), 665 666 P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_DP_UOP, ALL, 15), 667 668 P4_GEN_ESCR_EMASK(P4_EVENT_64BIT_MMX_UOP, ALL, 15), 669 670 P4_GEN_ESCR_EMASK(P4_EVENT_128BIT_MMX_UOP, ALL, 15), 671 672 P4_GEN_ESCR_EMASK(P4_EVENT_X87_FP_UOP, ALL, 15), 673 674 P4_GEN_ESCR_EMASK(P4_EVENT_TC_MISC, FLUSH, 4), 675 676 P4_GEN_ESCR_EMASK(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING, 0), 677 678 P4_GEN_ESCR_EMASK(P4_EVENT_TC_MS_XFER, CISC, 0), 679 680 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_BUILD, 0), 681 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_DELIVER, 1), 682 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_ROM, 2), 683 684 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CONDITIONAL, 1), 685 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CALL, 2), 686 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, RETURN, 3), 687 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, INDIRECT, 4), 688 689 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CONDITIONAL, 1), 690 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CALL, 2), 691 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, RETURN, 3), 692 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, INDIRECT, 4), 693 694 P4_GEN_ESCR_EMASK(P4_EVENT_RESOURCE_STALL, SBFULL, 5), 695 696 P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_EVICTS, 0), 697 P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_FULL_EVICTS, 1), 698 699 P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, NBOGUS, 0), 700 P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, BOGUS, 1), 701 702 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS0, 0), 703 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS1, 1), 704 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS2, 2), 705 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS3, 3), 706 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS0, 4), 707 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS1, 5), 708 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS2, 6), 709 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS3, 7), 710 711 P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, NBOGUS, 0), 712 P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, BOGUS, 1), 713 714 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSNTAG, 0), 715 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSTAG, 1), 716 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSNTAG, 2), 717 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSTAG, 3), 718 719 P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, NBOGUS, 0), 720 P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, BOGUS, 1), 721 722 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGLOADS, 1), 723 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGSTORES, 2), 724 725 P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNP, 0), 726 P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNM, 1), 727 P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTP, 2), 728 P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTM, 3), 729 730 P4_GEN_ESCR_EMASK(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS, 0), 731 732 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSU, 0), 733 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSO, 1), 734 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAO, 2), 735 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAU, 3), 736 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, PREA, 4), 737 738 P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, CLEAR, 0), 739 P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, MOCLEAR, 1), 740 P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, SMCLEAR, 2), 741 742 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, NBOGUS, 0), 743 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, BOGUS, 1), 744 }; 745 746 /* 747 * Note we have UOP and PEBS bits reserved for now 748 * just in case if we will need them once 749 */ 750 #define P4_PEBS_CONFIG_ENABLE (1 << 7) 751 #define P4_PEBS_CONFIG_UOP_TAG (1 << 8) 752 #define P4_PEBS_CONFIG_METRIC_MASK 0x3f 753 #define P4_PEBS_CONFIG_MASK 0xff 754 755 /* 756 * mem: Only counters MSR_IQ_COUNTER4 (16) and 757 * MSR_IQ_COUNTER5 (17) are allowed for PEBS sampling 758 */ 759 #define P4_PEBS_ENABLE 0x02000000U 760 #define P4_PEBS_ENABLE_UOP_TAG 0x01000000U 761 762 #define p4_config_unpack_metric(v) (((u64)(v)) & P4_PEBS_CONFIG_METRIC_MASK) 763 #define p4_config_unpack_pebs(v) (((u64)(v)) & P4_PEBS_CONFIG_MASK) 764 765 #define p4_config_pebs_has(v, mask) (p4_config_unpack_pebs(v) & (mask)) 766 767 enum P4_PEBS_METRIC { 768 P4_PEBS_METRIC__none, 769 770 P4_PEBS_METRIC__1stl_cache_load_miss_retired, 771 P4_PEBS_METRIC__2ndl_cache_load_miss_retired, 772 P4_PEBS_METRIC__dtlb_load_miss_retired, 773 P4_PEBS_METRIC__dtlb_store_miss_retired, 774 P4_PEBS_METRIC__dtlb_all_miss_retired, 775 P4_PEBS_METRIC__tagged_mispred_branch, 776 P4_PEBS_METRIC__mob_load_replay_retired, 777 P4_PEBS_METRIC__split_load_retired, 778 P4_PEBS_METRIC__split_store_retired, 779 780 P4_PEBS_METRIC__max 781 }; 782 783 /* 784 * Notes on internal configuration of ESCR+CCCR tuples 785 * 786 * Since P4 has quite the different architecture of 787 * performance registers in compare with "architectural" 788 * once and we have on 64 bits to keep configuration 789 * of performance event, the following trick is used. 790 * 791 * 1) Since both ESCR and CCCR registers have only low 792 * 32 bits valuable, we pack them into a single 64 bit 793 * configuration. Low 32 bits of such config correspond 794 * to low 32 bits of CCCR register and high 32 bits 795 * correspond to low 32 bits of ESCR register. 796 * 797 * 2) The meaning of every bit of such config field can 798 * be found in Intel SDM but it should be noted that 799 * we "borrow" some reserved bits for own usage and 800 * clean them or set to a proper value when we do 801 * a real write to hardware registers. 802 * 803 * 3) The format of bits of config is the following 804 * and should be either 0 or set to some predefined 805 * values: 806 * 807 * Low 32 bits 808 * ----------- 809 * 0-6: P4_PEBS_METRIC enum 810 * 7-11: reserved 811 * 12: reserved (Enable) 812 * 13-15: reserved (ESCR select) 813 * 16-17: Active Thread 814 * 18: Compare 815 * 19: Complement 816 * 20-23: Threshold 817 * 24: Edge 818 * 25: reserved (FORCE_OVF) 819 * 26: reserved (OVF_PMI_T0) 820 * 27: reserved (OVF_PMI_T1) 821 * 28-29: reserved 822 * 30: reserved (Cascade) 823 * 31: reserved (OVF) 824 * 825 * High 32 bits 826 * ------------ 827 * 0: reserved (T1_USR) 828 * 1: reserved (T1_OS) 829 * 2: reserved (T0_USR) 830 * 3: reserved (T0_OS) 831 * 4: Tag Enable 832 * 5-8: Tag Value 833 * 9-24: Event Mask (may use P4_ESCR_EMASK_BIT helper) 834 * 25-30: enum P4_EVENTS 835 * 31: reserved (HT thread) 836 */ 837 838 #endif /* PERF_EVENT_P4_H */ 839 840