1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_PERF_EVENT_H 3 #define _ASM_X86_PERF_EVENT_H 4 5 #include <linux/static_call.h> 6 7 /* 8 * Performance event hw details: 9 */ 10 11 #define INTEL_PMC_MAX_GENERIC 32 12 #define INTEL_PMC_MAX_FIXED 16 13 #define INTEL_PMC_IDX_FIXED 32 14 15 #define X86_PMC_IDX_MAX 64 16 17 #define MSR_ARCH_PERFMON_PERFCTR0 0xc1 18 #define MSR_ARCH_PERFMON_PERFCTR1 0xc2 19 20 #define MSR_ARCH_PERFMON_EVENTSEL0 0x186 21 #define MSR_ARCH_PERFMON_EVENTSEL1 0x187 22 23 #define ARCH_PERFMON_EVENTSEL_EVENT 0x000000FFULL 24 #define ARCH_PERFMON_EVENTSEL_UMASK 0x0000FF00ULL 25 #define ARCH_PERFMON_EVENTSEL_USR (1ULL << 16) 26 #define ARCH_PERFMON_EVENTSEL_OS (1ULL << 17) 27 #define ARCH_PERFMON_EVENTSEL_EDGE (1ULL << 18) 28 #define ARCH_PERFMON_EVENTSEL_PIN_CONTROL (1ULL << 19) 29 #define ARCH_PERFMON_EVENTSEL_INT (1ULL << 20) 30 #define ARCH_PERFMON_EVENTSEL_ANY (1ULL << 21) 31 #define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22) 32 #define ARCH_PERFMON_EVENTSEL_INV (1ULL << 23) 33 #define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL 34 35 #define HSW_IN_TX (1ULL << 32) 36 #define HSW_IN_TX_CHECKPOINTED (1ULL << 33) 37 #define ICL_EVENTSEL_ADAPTIVE (1ULL << 34) 38 #define ICL_FIXED_0_ADAPTIVE (1ULL << 32) 39 40 #define AMD64_EVENTSEL_INT_CORE_ENABLE (1ULL << 36) 41 #define AMD64_EVENTSEL_GUESTONLY (1ULL << 40) 42 #define AMD64_EVENTSEL_HOSTONLY (1ULL << 41) 43 44 #define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT 37 45 #define AMD64_EVENTSEL_INT_CORE_SEL_MASK \ 46 (0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT) 47 48 #define AMD64_EVENTSEL_EVENT \ 49 (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32)) 50 #define INTEL_ARCH_EVENT_MASK \ 51 (ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT) 52 53 #define AMD64_L3_SLICE_SHIFT 48 54 #define AMD64_L3_SLICE_MASK \ 55 (0xFULL << AMD64_L3_SLICE_SHIFT) 56 #define AMD64_L3_SLICEID_MASK \ 57 (0x7ULL << AMD64_L3_SLICE_SHIFT) 58 59 #define AMD64_L3_THREAD_SHIFT 56 60 #define AMD64_L3_THREAD_MASK \ 61 (0xFFULL << AMD64_L3_THREAD_SHIFT) 62 #define AMD64_L3_F19H_THREAD_MASK \ 63 (0x3ULL << AMD64_L3_THREAD_SHIFT) 64 65 #define AMD64_L3_EN_ALL_CORES BIT_ULL(47) 66 #define AMD64_L3_EN_ALL_SLICES BIT_ULL(46) 67 68 #define AMD64_L3_COREID_SHIFT 42 69 #define AMD64_L3_COREID_MASK \ 70 (0x7ULL << AMD64_L3_COREID_SHIFT) 71 72 #define X86_RAW_EVENT_MASK \ 73 (ARCH_PERFMON_EVENTSEL_EVENT | \ 74 ARCH_PERFMON_EVENTSEL_UMASK | \ 75 ARCH_PERFMON_EVENTSEL_EDGE | \ 76 ARCH_PERFMON_EVENTSEL_INV | \ 77 ARCH_PERFMON_EVENTSEL_CMASK) 78 #define X86_ALL_EVENT_FLAGS \ 79 (ARCH_PERFMON_EVENTSEL_EDGE | \ 80 ARCH_PERFMON_EVENTSEL_INV | \ 81 ARCH_PERFMON_EVENTSEL_CMASK | \ 82 ARCH_PERFMON_EVENTSEL_ANY | \ 83 ARCH_PERFMON_EVENTSEL_PIN_CONTROL | \ 84 HSW_IN_TX | \ 85 HSW_IN_TX_CHECKPOINTED) 86 #define AMD64_RAW_EVENT_MASK \ 87 (X86_RAW_EVENT_MASK | \ 88 AMD64_EVENTSEL_EVENT) 89 #define AMD64_RAW_EVENT_MASK_NB \ 90 (AMD64_EVENTSEL_EVENT | \ 91 ARCH_PERFMON_EVENTSEL_UMASK) 92 93 #define AMD64_PERFMON_V2_EVENTSEL_EVENT_NB \ 94 (AMD64_EVENTSEL_EVENT | \ 95 GENMASK_ULL(37, 36)) 96 97 #define AMD64_PERFMON_V2_EVENTSEL_UMASK_NB \ 98 (ARCH_PERFMON_EVENTSEL_UMASK | \ 99 GENMASK_ULL(27, 24)) 100 101 #define AMD64_PERFMON_V2_RAW_EVENT_MASK_NB \ 102 (AMD64_PERFMON_V2_EVENTSEL_EVENT_NB | \ 103 AMD64_PERFMON_V2_EVENTSEL_UMASK_NB) 104 105 #define AMD64_NUM_COUNTERS 4 106 #define AMD64_NUM_COUNTERS_CORE 6 107 #define AMD64_NUM_COUNTERS_NB 4 108 109 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c 110 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8) 111 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0 112 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \ 113 (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX)) 114 115 #define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6 116 #define ARCH_PERFMON_EVENTS_COUNT 7 117 118 #define PEBS_DATACFG_MEMINFO BIT_ULL(0) 119 #define PEBS_DATACFG_GP BIT_ULL(1) 120 #define PEBS_DATACFG_XMMS BIT_ULL(2) 121 #define PEBS_DATACFG_LBRS BIT_ULL(3) 122 #define PEBS_DATACFG_LBR_SHIFT 24 123 124 /* Steal the highest bit of pebs_data_cfg for SW usage */ 125 #define PEBS_UPDATE_DS_SW BIT_ULL(63) 126 127 /* 128 * Intel "Architectural Performance Monitoring" CPUID 129 * detection/enumeration details: 130 */ 131 union cpuid10_eax { 132 struct { 133 unsigned int version_id:8; 134 unsigned int num_counters:8; 135 unsigned int bit_width:8; 136 unsigned int mask_length:8; 137 } split; 138 unsigned int full; 139 }; 140 141 union cpuid10_ebx { 142 struct { 143 unsigned int no_unhalted_core_cycles:1; 144 unsigned int no_instructions_retired:1; 145 unsigned int no_unhalted_reference_cycles:1; 146 unsigned int no_llc_reference:1; 147 unsigned int no_llc_misses:1; 148 unsigned int no_branch_instruction_retired:1; 149 unsigned int no_branch_misses_retired:1; 150 } split; 151 unsigned int full; 152 }; 153 154 union cpuid10_edx { 155 struct { 156 unsigned int num_counters_fixed:5; 157 unsigned int bit_width_fixed:8; 158 unsigned int reserved1:2; 159 unsigned int anythread_deprecated:1; 160 unsigned int reserved2:16; 161 } split; 162 unsigned int full; 163 }; 164 165 /* 166 * Intel "Architectural Performance Monitoring extension" CPUID 167 * detection/enumeration details: 168 */ 169 #define ARCH_PERFMON_EXT_LEAF 0x00000023 170 #define ARCH_PERFMON_NUM_COUNTER_LEAF_BIT 0x1 171 #define ARCH_PERFMON_NUM_COUNTER_LEAF 0x1 172 173 /* 174 * Intel Architectural LBR CPUID detection/enumeration details: 175 */ 176 union cpuid28_eax { 177 struct { 178 /* Supported LBR depth values */ 179 unsigned int lbr_depth_mask:8; 180 unsigned int reserved:22; 181 /* Deep C-state Reset */ 182 unsigned int lbr_deep_c_reset:1; 183 /* IP values contain LIP */ 184 unsigned int lbr_lip:1; 185 } split; 186 unsigned int full; 187 }; 188 189 union cpuid28_ebx { 190 struct { 191 /* CPL Filtering Supported */ 192 unsigned int lbr_cpl:1; 193 /* Branch Filtering Supported */ 194 unsigned int lbr_filter:1; 195 /* Call-stack Mode Supported */ 196 unsigned int lbr_call_stack:1; 197 } split; 198 unsigned int full; 199 }; 200 201 union cpuid28_ecx { 202 struct { 203 /* Mispredict Bit Supported */ 204 unsigned int lbr_mispred:1; 205 /* Timed LBRs Supported */ 206 unsigned int lbr_timed_lbr:1; 207 /* Branch Type Field Supported */ 208 unsigned int lbr_br_type:1; 209 } split; 210 unsigned int full; 211 }; 212 213 /* 214 * AMD "Extended Performance Monitoring and Debug" CPUID 215 * detection/enumeration details: 216 */ 217 union cpuid_0x80000022_ebx { 218 struct { 219 /* Number of Core Performance Counters */ 220 unsigned int num_core_pmc:4; 221 /* Number of available LBR Stack Entries */ 222 unsigned int lbr_v2_stack_sz:6; 223 /* Number of Data Fabric Counters */ 224 unsigned int num_df_pmc:6; 225 } split; 226 unsigned int full; 227 }; 228 229 struct x86_pmu_capability { 230 int version; 231 int num_counters_gp; 232 int num_counters_fixed; 233 int bit_width_gp; 234 int bit_width_fixed; 235 unsigned int events_mask; 236 int events_mask_len; 237 unsigned int pebs_ept :1; 238 }; 239 240 /* 241 * Fixed-purpose performance events: 242 */ 243 244 /* RDPMC offset for Fixed PMCs */ 245 #define INTEL_PMC_FIXED_RDPMC_BASE (1 << 30) 246 #define INTEL_PMC_FIXED_RDPMC_METRICS (1 << 29) 247 248 /* 249 * All the fixed-mode PMCs are configured via this single MSR: 250 */ 251 #define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d 252 253 /* 254 * There is no event-code assigned to the fixed-mode PMCs. 255 * 256 * For a fixed-mode PMC, which has an equivalent event on a general-purpose 257 * PMC, the event-code of the equivalent event is used for the fixed-mode PMC, 258 * e.g., Instr_Retired.Any and CPU_CLK_Unhalted.Core. 259 * 260 * For a fixed-mode PMC, which doesn't have an equivalent event, a 261 * pseudo-encoding is used, e.g., CPU_CLK_Unhalted.Ref and TOPDOWN.SLOTS. 262 * The pseudo event-code for a fixed-mode PMC must be 0x00. 263 * The pseudo umask-code is 0xX. The X equals the index of the fixed 264 * counter + 1, e.g., the fixed counter 2 has the pseudo-encoding 0x0300. 265 * 266 * The counts are available in separate MSRs: 267 */ 268 269 /* Instr_Retired.Any: */ 270 #define MSR_ARCH_PERFMON_FIXED_CTR0 0x309 271 #define INTEL_PMC_IDX_FIXED_INSTRUCTIONS (INTEL_PMC_IDX_FIXED + 0) 272 273 /* CPU_CLK_Unhalted.Core: */ 274 #define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a 275 #define INTEL_PMC_IDX_FIXED_CPU_CYCLES (INTEL_PMC_IDX_FIXED + 1) 276 277 /* CPU_CLK_Unhalted.Ref: event=0x00,umask=0x3 (pseudo-encoding) */ 278 #define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b 279 #define INTEL_PMC_IDX_FIXED_REF_CYCLES (INTEL_PMC_IDX_FIXED + 2) 280 #define INTEL_PMC_MSK_FIXED_REF_CYCLES (1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES) 281 282 /* TOPDOWN.SLOTS: event=0x00,umask=0x4 (pseudo-encoding) */ 283 #define MSR_ARCH_PERFMON_FIXED_CTR3 0x30c 284 #define INTEL_PMC_IDX_FIXED_SLOTS (INTEL_PMC_IDX_FIXED + 3) 285 #define INTEL_PMC_MSK_FIXED_SLOTS (1ULL << INTEL_PMC_IDX_FIXED_SLOTS) 286 287 static inline bool use_fixed_pseudo_encoding(u64 code) 288 { 289 return !(code & 0xff); 290 } 291 292 /* 293 * We model BTS tracing as another fixed-mode PMC. 294 * 295 * We choose the value 47 for the fixed index of BTS, since lower 296 * values are used by actual fixed events and higher values are used 297 * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr. 298 */ 299 #define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 15) 300 301 /* 302 * The PERF_METRICS MSR is modeled as several magic fixed-mode PMCs, one for 303 * each TopDown metric event. 304 * 305 * Internally the TopDown metric events are mapped to the FxCtr 3 (SLOTS). 306 */ 307 #define INTEL_PMC_IDX_METRIC_BASE (INTEL_PMC_IDX_FIXED + 16) 308 #define INTEL_PMC_IDX_TD_RETIRING (INTEL_PMC_IDX_METRIC_BASE + 0) 309 #define INTEL_PMC_IDX_TD_BAD_SPEC (INTEL_PMC_IDX_METRIC_BASE + 1) 310 #define INTEL_PMC_IDX_TD_FE_BOUND (INTEL_PMC_IDX_METRIC_BASE + 2) 311 #define INTEL_PMC_IDX_TD_BE_BOUND (INTEL_PMC_IDX_METRIC_BASE + 3) 312 #define INTEL_PMC_IDX_TD_HEAVY_OPS (INTEL_PMC_IDX_METRIC_BASE + 4) 313 #define INTEL_PMC_IDX_TD_BR_MISPREDICT (INTEL_PMC_IDX_METRIC_BASE + 5) 314 #define INTEL_PMC_IDX_TD_FETCH_LAT (INTEL_PMC_IDX_METRIC_BASE + 6) 315 #define INTEL_PMC_IDX_TD_MEM_BOUND (INTEL_PMC_IDX_METRIC_BASE + 7) 316 #define INTEL_PMC_IDX_METRIC_END INTEL_PMC_IDX_TD_MEM_BOUND 317 #define INTEL_PMC_MSK_TOPDOWN ((0xffull << INTEL_PMC_IDX_METRIC_BASE) | \ 318 INTEL_PMC_MSK_FIXED_SLOTS) 319 320 /* 321 * There is no event-code assigned to the TopDown events. 322 * 323 * For the slots event, use the pseudo code of the fixed counter 3. 324 * 325 * For the metric events, the pseudo event-code is 0x00. 326 * The pseudo umask-code starts from the middle of the pseudo event 327 * space, 0x80. 328 */ 329 #define INTEL_TD_SLOTS 0x0400 /* TOPDOWN.SLOTS */ 330 /* Level 1 metrics */ 331 #define INTEL_TD_METRIC_RETIRING 0x8000 /* Retiring metric */ 332 #define INTEL_TD_METRIC_BAD_SPEC 0x8100 /* Bad speculation metric */ 333 #define INTEL_TD_METRIC_FE_BOUND 0x8200 /* FE bound metric */ 334 #define INTEL_TD_METRIC_BE_BOUND 0x8300 /* BE bound metric */ 335 /* Level 2 metrics */ 336 #define INTEL_TD_METRIC_HEAVY_OPS 0x8400 /* Heavy Operations metric */ 337 #define INTEL_TD_METRIC_BR_MISPREDICT 0x8500 /* Branch Mispredict metric */ 338 #define INTEL_TD_METRIC_FETCH_LAT 0x8600 /* Fetch Latency metric */ 339 #define INTEL_TD_METRIC_MEM_BOUND 0x8700 /* Memory bound metric */ 340 341 #define INTEL_TD_METRIC_MAX INTEL_TD_METRIC_MEM_BOUND 342 #define INTEL_TD_METRIC_NUM 8 343 344 static inline bool is_metric_idx(int idx) 345 { 346 return (unsigned)(idx - INTEL_PMC_IDX_METRIC_BASE) < INTEL_TD_METRIC_NUM; 347 } 348 349 static inline bool is_topdown_idx(int idx) 350 { 351 return is_metric_idx(idx) || idx == INTEL_PMC_IDX_FIXED_SLOTS; 352 } 353 354 #define INTEL_PMC_OTHER_TOPDOWN_BITS(bit) \ 355 (~(0x1ull << bit) & INTEL_PMC_MSK_TOPDOWN) 356 357 #define GLOBAL_STATUS_COND_CHG BIT_ULL(63) 358 #define GLOBAL_STATUS_BUFFER_OVF_BIT 62 359 #define GLOBAL_STATUS_BUFFER_OVF BIT_ULL(GLOBAL_STATUS_BUFFER_OVF_BIT) 360 #define GLOBAL_STATUS_UNC_OVF BIT_ULL(61) 361 #define GLOBAL_STATUS_ASIF BIT_ULL(60) 362 #define GLOBAL_STATUS_COUNTERS_FROZEN BIT_ULL(59) 363 #define GLOBAL_STATUS_LBRS_FROZEN_BIT 58 364 #define GLOBAL_STATUS_LBRS_FROZEN BIT_ULL(GLOBAL_STATUS_LBRS_FROZEN_BIT) 365 #define GLOBAL_STATUS_TRACE_TOPAPMI_BIT 55 366 #define GLOBAL_STATUS_TRACE_TOPAPMI BIT_ULL(GLOBAL_STATUS_TRACE_TOPAPMI_BIT) 367 #define GLOBAL_STATUS_PERF_METRICS_OVF_BIT 48 368 369 #define GLOBAL_CTRL_EN_PERF_METRICS 48 370 /* 371 * We model guest LBR event tracing as another fixed-mode PMC like BTS. 372 * 373 * We choose bit 58 because it's used to indicate LBR stack frozen state 374 * for architectural perfmon v4, also we unconditionally mask that bit in 375 * the handle_pmi_common(), so it'll never be set in the overflow handling. 376 * 377 * With this fake counter assigned, the guest LBR event user (such as KVM), 378 * can program the LBR registers on its own, and we don't actually do anything 379 * with then in the host context. 380 */ 381 #define INTEL_PMC_IDX_FIXED_VLBR (GLOBAL_STATUS_LBRS_FROZEN_BIT) 382 383 /* 384 * Pseudo-encoding the guest LBR event as event=0x00,umask=0x1b, 385 * since it would claim bit 58 which is effectively Fixed26. 386 */ 387 #define INTEL_FIXED_VLBR_EVENT 0x1b00 388 389 /* 390 * Adaptive PEBS v4 391 */ 392 393 struct pebs_basic { 394 u64 format_size; 395 u64 ip; 396 u64 applicable_counters; 397 u64 tsc; 398 }; 399 400 struct pebs_meminfo { 401 u64 address; 402 u64 aux; 403 u64 latency; 404 u64 tsx_tuning; 405 }; 406 407 struct pebs_gprs { 408 u64 flags, ip, ax, cx, dx, bx, sp, bp, si, di; 409 u64 r8, r9, r10, r11, r12, r13, r14, r15; 410 }; 411 412 struct pebs_xmm { 413 u64 xmm[16*2]; /* two entries for each register */ 414 }; 415 416 /* 417 * AMD Extended Performance Monitoring and Debug cpuid feature detection 418 */ 419 #define EXT_PERFMON_DEBUG_FEATURES 0x80000022 420 421 /* 422 * IBS cpuid feature detection 423 */ 424 425 #define IBS_CPUID_FEATURES 0x8000001b 426 427 /* 428 * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but 429 * bit 0 is used to indicate the existence of IBS. 430 */ 431 #define IBS_CAPS_AVAIL (1U<<0) 432 #define IBS_CAPS_FETCHSAM (1U<<1) 433 #define IBS_CAPS_OPSAM (1U<<2) 434 #define IBS_CAPS_RDWROPCNT (1U<<3) 435 #define IBS_CAPS_OPCNT (1U<<4) 436 #define IBS_CAPS_BRNTRGT (1U<<5) 437 #define IBS_CAPS_OPCNTEXT (1U<<6) 438 #define IBS_CAPS_RIPINVALIDCHK (1U<<7) 439 #define IBS_CAPS_OPBRNFUSE (1U<<8) 440 #define IBS_CAPS_FETCHCTLEXTD (1U<<9) 441 #define IBS_CAPS_OPDATA4 (1U<<10) 442 #define IBS_CAPS_ZEN4 (1U<<11) 443 444 #define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \ 445 | IBS_CAPS_FETCHSAM \ 446 | IBS_CAPS_OPSAM) 447 448 /* 449 * IBS APIC setup 450 */ 451 #define IBSCTL 0x1cc 452 #define IBSCTL_LVT_OFFSET_VALID (1ULL<<8) 453 #define IBSCTL_LVT_OFFSET_MASK 0x0F 454 455 /* IBS fetch bits/masks */ 456 #define IBS_FETCH_L3MISSONLY (1ULL<<59) 457 #define IBS_FETCH_RAND_EN (1ULL<<57) 458 #define IBS_FETCH_VAL (1ULL<<49) 459 #define IBS_FETCH_ENABLE (1ULL<<48) 460 #define IBS_FETCH_CNT 0xFFFF0000ULL 461 #define IBS_FETCH_MAX_CNT 0x0000FFFFULL 462 463 /* 464 * IBS op bits/masks 465 * The lower 7 bits of the current count are random bits 466 * preloaded by hardware and ignored in software 467 */ 468 #define IBS_OP_CUR_CNT (0xFFF80ULL<<32) 469 #define IBS_OP_CUR_CNT_RAND (0x0007FULL<<32) 470 #define IBS_OP_CNT_CTL (1ULL<<19) 471 #define IBS_OP_VAL (1ULL<<18) 472 #define IBS_OP_ENABLE (1ULL<<17) 473 #define IBS_OP_L3MISSONLY (1ULL<<16) 474 #define IBS_OP_MAX_CNT 0x0000FFFFULL 475 #define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */ 476 #define IBS_OP_MAX_CNT_EXT_MASK (0x7FULL<<20) /* separate upper 7 bits */ 477 #define IBS_RIP_INVALID (1ULL<<38) 478 479 #ifdef CONFIG_X86_LOCAL_APIC 480 extern u32 get_ibs_caps(void); 481 #else 482 static inline u32 get_ibs_caps(void) { return 0; } 483 #endif 484 485 #ifdef CONFIG_PERF_EVENTS 486 extern void perf_events_lapic_init(void); 487 488 /* 489 * Abuse bits {3,5} of the cpu eflags register. These flags are otherwise 490 * unused and ABI specified to be 0, so nobody should care what we do with 491 * them. 492 * 493 * EXACT - the IP points to the exact instruction that triggered the 494 * event (HW bugs exempt). 495 * VM - original X86_VM_MASK; see set_linear_ip(). 496 */ 497 #define PERF_EFLAGS_EXACT (1UL << 3) 498 #define PERF_EFLAGS_VM (1UL << 5) 499 500 struct pt_regs; 501 struct x86_perf_regs { 502 struct pt_regs regs; 503 u64 *xmm_regs; 504 }; 505 506 extern unsigned long perf_instruction_pointer(struct pt_regs *regs); 507 extern unsigned long perf_misc_flags(struct pt_regs *regs); 508 #define perf_misc_flags(regs) perf_misc_flags(regs) 509 510 #include <asm/stacktrace.h> 511 512 /* 513 * We abuse bit 3 from flags to pass exact information, see perf_misc_flags 514 * and the comment with PERF_EFLAGS_EXACT. 515 */ 516 #define perf_arch_fetch_caller_regs(regs, __ip) { \ 517 (regs)->ip = (__ip); \ 518 (regs)->sp = (unsigned long)__builtin_frame_address(0); \ 519 (regs)->cs = __KERNEL_CS; \ 520 regs->flags = 0; \ 521 } 522 523 struct perf_guest_switch_msr { 524 unsigned msr; 525 u64 host, guest; 526 }; 527 528 struct x86_pmu_lbr { 529 unsigned int nr; 530 unsigned int from; 531 unsigned int to; 532 unsigned int info; 533 }; 534 535 extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap); 536 extern u64 perf_get_hw_event_config(int hw_event); 537 extern void perf_check_microcode(void); 538 extern void perf_clear_dirty_counters(void); 539 extern int x86_perf_rdpmc_index(struct perf_event *event); 540 #else 541 static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) 542 { 543 memset(cap, 0, sizeof(*cap)); 544 } 545 546 static inline u64 perf_get_hw_event_config(int hw_event) 547 { 548 return 0; 549 } 550 551 static inline void perf_events_lapic_init(void) { } 552 static inline void perf_check_microcode(void) { } 553 #endif 554 555 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL) 556 extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data); 557 extern void x86_perf_get_lbr(struct x86_pmu_lbr *lbr); 558 #else 559 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data); 560 static inline void x86_perf_get_lbr(struct x86_pmu_lbr *lbr) 561 { 562 memset(lbr, 0, sizeof(*lbr)); 563 } 564 #endif 565 566 #ifdef CONFIG_CPU_SUP_INTEL 567 extern void intel_pt_handle_vmx(int on); 568 #else 569 static inline void intel_pt_handle_vmx(int on) 570 { 571 572 } 573 #endif 574 575 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) 576 extern void amd_pmu_enable_virt(void); 577 extern void amd_pmu_disable_virt(void); 578 579 #if defined(CONFIG_PERF_EVENTS_AMD_BRS) 580 581 #define PERF_NEEDS_LOPWR_CB 1 582 583 /* 584 * architectural low power callback impacts 585 * drivers/acpi/processor_idle.c 586 * drivers/acpi/acpi_pad.c 587 */ 588 extern void perf_amd_brs_lopwr_cb(bool lopwr_in); 589 590 DECLARE_STATIC_CALL(perf_lopwr_cb, perf_amd_brs_lopwr_cb); 591 592 static __always_inline void perf_lopwr_cb(bool lopwr_in) 593 { 594 static_call_mod(perf_lopwr_cb)(lopwr_in); 595 } 596 597 #endif /* PERF_NEEDS_LOPWR_CB */ 598 599 #else 600 static inline void amd_pmu_enable_virt(void) { } 601 static inline void amd_pmu_disable_virt(void) { } 602 #endif 603 604 #define arch_perf_out_copy_user copy_from_user_nmi 605 606 #endif /* _ASM_X86_PERF_EVENT_H */ 607