xref: /openbmc/linux/arch/x86/include/asm/paravirt.h (revision e3d786a3) 
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_PARAVIRT_H
3 #define _ASM_X86_PARAVIRT_H
4 /* Various instructions on x86 need to be replaced for
5  * para-virtualization: those hooks are defined here. */
6 
7 #ifdef CONFIG_PARAVIRT
8 #include <asm/pgtable_types.h>
9 #include <asm/asm.h>
10 #include <asm/nospec-branch.h>
11 
12 #include <asm/paravirt_types.h>
13 
14 #ifndef __ASSEMBLY__
15 #include <linux/bug.h>
16 #include <linux/types.h>
17 #include <linux/cpumask.h>
18 #include <asm/frame.h>
19 
20 static inline unsigned long long paravirt_sched_clock(void)
21 {
22 	return PVOP_CALL0(unsigned long long, time.sched_clock);
23 }
24 
25 struct static_key;
26 extern struct static_key paravirt_steal_enabled;
27 extern struct static_key paravirt_steal_rq_enabled;
28 
29 static inline u64 paravirt_steal_clock(int cpu)
30 {
31 	return PVOP_CALL1(u64, time.steal_clock, cpu);
32 }
33 
34 /* The paravirtualized I/O functions */
35 static inline void slow_down_io(void)
36 {
37 	pv_ops.cpu.io_delay();
38 #ifdef REALLY_SLOW_IO
39 	pv_ops.cpu.io_delay();
40 	pv_ops.cpu.io_delay();
41 	pv_ops.cpu.io_delay();
42 #endif
43 }
44 
45 static inline void __flush_tlb(void)
46 {
47 	PVOP_VCALL0(mmu.flush_tlb_user);
48 }
49 
50 static inline void __flush_tlb_global(void)
51 {
52 	PVOP_VCALL0(mmu.flush_tlb_kernel);
53 }
54 
55 static inline void __flush_tlb_one_user(unsigned long addr)
56 {
57 	PVOP_VCALL1(mmu.flush_tlb_one_user, addr);
58 }
59 
60 static inline void flush_tlb_others(const struct cpumask *cpumask,
61 				    const struct flush_tlb_info *info)
62 {
63 	PVOP_VCALL2(mmu.flush_tlb_others, cpumask, info);
64 }
65 
66 static inline void paravirt_tlb_remove_table(struct mmu_gather *tlb, void *table)
67 {
68 	PVOP_VCALL2(mmu.tlb_remove_table, tlb, table);
69 }
70 
71 static inline void paravirt_arch_exit_mmap(struct mm_struct *mm)
72 {
73 	PVOP_VCALL1(mmu.exit_mmap, mm);
74 }
75 
76 #ifdef CONFIG_PARAVIRT_XXL
77 static inline void load_sp0(unsigned long sp0)
78 {
79 	PVOP_VCALL1(cpu.load_sp0, sp0);
80 }
81 
82 /* The paravirtualized CPUID instruction. */
83 static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
84 			   unsigned int *ecx, unsigned int *edx)
85 {
86 	PVOP_VCALL4(cpu.cpuid, eax, ebx, ecx, edx);
87 }
88 
89 /*
90  * These special macros can be used to get or set a debugging register
91  */
92 static inline unsigned long paravirt_get_debugreg(int reg)
93 {
94 	return PVOP_CALL1(unsigned long, cpu.get_debugreg, reg);
95 }
96 #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg)
97 static inline void set_debugreg(unsigned long val, int reg)
98 {
99 	PVOP_VCALL2(cpu.set_debugreg, reg, val);
100 }
101 
102 static inline unsigned long read_cr0(void)
103 {
104 	return PVOP_CALL0(unsigned long, cpu.read_cr0);
105 }
106 
107 static inline void write_cr0(unsigned long x)
108 {
109 	PVOP_VCALL1(cpu.write_cr0, x);
110 }
111 
112 static inline unsigned long read_cr2(void)
113 {
114 	return PVOP_CALL0(unsigned long, mmu.read_cr2);
115 }
116 
117 static inline void write_cr2(unsigned long x)
118 {
119 	PVOP_VCALL1(mmu.write_cr2, x);
120 }
121 
122 static inline unsigned long __read_cr3(void)
123 {
124 	return PVOP_CALL0(unsigned long, mmu.read_cr3);
125 }
126 
127 static inline void write_cr3(unsigned long x)
128 {
129 	PVOP_VCALL1(mmu.write_cr3, x);
130 }
131 
132 static inline void __write_cr4(unsigned long x)
133 {
134 	PVOP_VCALL1(cpu.write_cr4, x);
135 }
136 
137 #ifdef CONFIG_X86_64
138 static inline unsigned long read_cr8(void)
139 {
140 	return PVOP_CALL0(unsigned long, cpu.read_cr8);
141 }
142 
143 static inline void write_cr8(unsigned long x)
144 {
145 	PVOP_VCALL1(cpu.write_cr8, x);
146 }
147 #endif
148 
149 static inline void arch_safe_halt(void)
150 {
151 	PVOP_VCALL0(irq.safe_halt);
152 }
153 
154 static inline void halt(void)
155 {
156 	PVOP_VCALL0(irq.halt);
157 }
158 
159 static inline void wbinvd(void)
160 {
161 	PVOP_VCALL0(cpu.wbinvd);
162 }
163 
164 #define get_kernel_rpl()  (pv_info.kernel_rpl)
165 
166 static inline u64 paravirt_read_msr(unsigned msr)
167 {
168 	return PVOP_CALL1(u64, cpu.read_msr, msr);
169 }
170 
171 static inline void paravirt_write_msr(unsigned msr,
172 				      unsigned low, unsigned high)
173 {
174 	PVOP_VCALL3(cpu.write_msr, msr, low, high);
175 }
176 
177 static inline u64 paravirt_read_msr_safe(unsigned msr, int *err)
178 {
179 	return PVOP_CALL2(u64, cpu.read_msr_safe, msr, err);
180 }
181 
182 static inline int paravirt_write_msr_safe(unsigned msr,
183 					  unsigned low, unsigned high)
184 {
185 	return PVOP_CALL3(int, cpu.write_msr_safe, msr, low, high);
186 }
187 
188 #define rdmsr(msr, val1, val2)			\
189 do {						\
190 	u64 _l = paravirt_read_msr(msr);	\
191 	val1 = (u32)_l;				\
192 	val2 = _l >> 32;			\
193 } while (0)
194 
195 #define wrmsr(msr, val1, val2)			\
196 do {						\
197 	paravirt_write_msr(msr, val1, val2);	\
198 } while (0)
199 
200 #define rdmsrl(msr, val)			\
201 do {						\
202 	val = paravirt_read_msr(msr);		\
203 } while (0)
204 
205 static inline void wrmsrl(unsigned msr, u64 val)
206 {
207 	wrmsr(msr, (u32)val, (u32)(val>>32));
208 }
209 
210 #define wrmsr_safe(msr, a, b)	paravirt_write_msr_safe(msr, a, b)
211 
212 /* rdmsr with exception handling */
213 #define rdmsr_safe(msr, a, b)				\
214 ({							\
215 	int _err;					\
216 	u64 _l = paravirt_read_msr_safe(msr, &_err);	\
217 	(*a) = (u32)_l;					\
218 	(*b) = _l >> 32;				\
219 	_err;						\
220 })
221 
222 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
223 {
224 	int err;
225 
226 	*p = paravirt_read_msr_safe(msr, &err);
227 	return err;
228 }
229 
230 static inline unsigned long long paravirt_read_pmc(int counter)
231 {
232 	return PVOP_CALL1(u64, cpu.read_pmc, counter);
233 }
234 
235 #define rdpmc(counter, low, high)		\
236 do {						\
237 	u64 _l = paravirt_read_pmc(counter);	\
238 	low = (u32)_l;				\
239 	high = _l >> 32;			\
240 } while (0)
241 
242 #define rdpmcl(counter, val) ((val) = paravirt_read_pmc(counter))
243 
244 static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
245 {
246 	PVOP_VCALL2(cpu.alloc_ldt, ldt, entries);
247 }
248 
249 static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
250 {
251 	PVOP_VCALL2(cpu.free_ldt, ldt, entries);
252 }
253 
254 static inline void load_TR_desc(void)
255 {
256 	PVOP_VCALL0(cpu.load_tr_desc);
257 }
258 static inline void load_gdt(const struct desc_ptr *dtr)
259 {
260 	PVOP_VCALL1(cpu.load_gdt, dtr);
261 }
262 static inline void load_idt(const struct desc_ptr *dtr)
263 {
264 	PVOP_VCALL1(cpu.load_idt, dtr);
265 }
266 static inline void set_ldt(const void *addr, unsigned entries)
267 {
268 	PVOP_VCALL2(cpu.set_ldt, addr, entries);
269 }
270 static inline unsigned long paravirt_store_tr(void)
271 {
272 	return PVOP_CALL0(unsigned long, cpu.store_tr);
273 }
274 
275 #define store_tr(tr)	((tr) = paravirt_store_tr())
276 static inline void load_TLS(struct thread_struct *t, unsigned cpu)
277 {
278 	PVOP_VCALL2(cpu.load_tls, t, cpu);
279 }
280 
281 #ifdef CONFIG_X86_64
282 static inline void load_gs_index(unsigned int gs)
283 {
284 	PVOP_VCALL1(cpu.load_gs_index, gs);
285 }
286 #endif
287 
288 static inline void write_ldt_entry(struct desc_struct *dt, int entry,
289 				   const void *desc)
290 {
291 	PVOP_VCALL3(cpu.write_ldt_entry, dt, entry, desc);
292 }
293 
294 static inline void write_gdt_entry(struct desc_struct *dt, int entry,
295 				   void *desc, int type)
296 {
297 	PVOP_VCALL4(cpu.write_gdt_entry, dt, entry, desc, type);
298 }
299 
300 static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g)
301 {
302 	PVOP_VCALL3(cpu.write_idt_entry, dt, entry, g);
303 }
304 static inline void set_iopl_mask(unsigned mask)
305 {
306 	PVOP_VCALL1(cpu.set_iopl_mask, mask);
307 }
308 
309 static inline void paravirt_activate_mm(struct mm_struct *prev,
310 					struct mm_struct *next)
311 {
312 	PVOP_VCALL2(mmu.activate_mm, prev, next);
313 }
314 
315 static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm,
316 					  struct mm_struct *mm)
317 {
318 	PVOP_VCALL2(mmu.dup_mmap, oldmm, mm);
319 }
320 
321 static inline int paravirt_pgd_alloc(struct mm_struct *mm)
322 {
323 	return PVOP_CALL1(int, mmu.pgd_alloc, mm);
324 }
325 
326 static inline void paravirt_pgd_free(struct mm_struct *mm, pgd_t *pgd)
327 {
328 	PVOP_VCALL2(mmu.pgd_free, mm, pgd);
329 }
330 
331 static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned long pfn)
332 {
333 	PVOP_VCALL2(mmu.alloc_pte, mm, pfn);
334 }
335 static inline void paravirt_release_pte(unsigned long pfn)
336 {
337 	PVOP_VCALL1(mmu.release_pte, pfn);
338 }
339 
340 static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned long pfn)
341 {
342 	PVOP_VCALL2(mmu.alloc_pmd, mm, pfn);
343 }
344 
345 static inline void paravirt_release_pmd(unsigned long pfn)
346 {
347 	PVOP_VCALL1(mmu.release_pmd, pfn);
348 }
349 
350 static inline void paravirt_alloc_pud(struct mm_struct *mm, unsigned long pfn)
351 {
352 	PVOP_VCALL2(mmu.alloc_pud, mm, pfn);
353 }
354 static inline void paravirt_release_pud(unsigned long pfn)
355 {
356 	PVOP_VCALL1(mmu.release_pud, pfn);
357 }
358 
359 static inline void paravirt_alloc_p4d(struct mm_struct *mm, unsigned long pfn)
360 {
361 	PVOP_VCALL2(mmu.alloc_p4d, mm, pfn);
362 }
363 
364 static inline void paravirt_release_p4d(unsigned long pfn)
365 {
366 	PVOP_VCALL1(mmu.release_p4d, pfn);
367 }
368 
369 static inline pte_t __pte(pteval_t val)
370 {
371 	pteval_t ret;
372 
373 	if (sizeof(pteval_t) > sizeof(long))
374 		ret = PVOP_CALLEE2(pteval_t, mmu.make_pte, val, (u64)val >> 32);
375 	else
376 		ret = PVOP_CALLEE1(pteval_t, mmu.make_pte, val);
377 
378 	return (pte_t) { .pte = ret };
379 }
380 
381 static inline pteval_t pte_val(pte_t pte)
382 {
383 	pteval_t ret;
384 
385 	if (sizeof(pteval_t) > sizeof(long))
386 		ret = PVOP_CALLEE2(pteval_t, mmu.pte_val,
387 				   pte.pte, (u64)pte.pte >> 32);
388 	else
389 		ret = PVOP_CALLEE1(pteval_t, mmu.pte_val, pte.pte);
390 
391 	return ret;
392 }
393 
394 static inline pgd_t __pgd(pgdval_t val)
395 {
396 	pgdval_t ret;
397 
398 	if (sizeof(pgdval_t) > sizeof(long))
399 		ret = PVOP_CALLEE2(pgdval_t, mmu.make_pgd, val, (u64)val >> 32);
400 	else
401 		ret = PVOP_CALLEE1(pgdval_t, mmu.make_pgd, val);
402 
403 	return (pgd_t) { ret };
404 }
405 
406 static inline pgdval_t pgd_val(pgd_t pgd)
407 {
408 	pgdval_t ret;
409 
410 	if (sizeof(pgdval_t) > sizeof(long))
411 		ret =  PVOP_CALLEE2(pgdval_t, mmu.pgd_val,
412 				    pgd.pgd, (u64)pgd.pgd >> 32);
413 	else
414 		ret =  PVOP_CALLEE1(pgdval_t, mmu.pgd_val, pgd.pgd);
415 
416 	return ret;
417 }
418 
419 #define  __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
420 static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, unsigned long addr,
421 					   pte_t *ptep)
422 {
423 	pteval_t ret;
424 
425 	ret = PVOP_CALL3(pteval_t, mmu.ptep_modify_prot_start, mm, addr, ptep);
426 
427 	return (pte_t) { .pte = ret };
428 }
429 
430 static inline void ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr,
431 					   pte_t *ptep, pte_t pte)
432 {
433 	if (sizeof(pteval_t) > sizeof(long))
434 		/* 5 arg words */
435 		pv_ops.mmu.ptep_modify_prot_commit(mm, addr, ptep, pte);
436 	else
437 		PVOP_VCALL4(mmu.ptep_modify_prot_commit,
438 			    mm, addr, ptep, pte.pte);
439 }
440 
441 static inline void set_pte(pte_t *ptep, pte_t pte)
442 {
443 	if (sizeof(pteval_t) > sizeof(long))
444 		PVOP_VCALL3(mmu.set_pte, ptep, pte.pte, (u64)pte.pte >> 32);
445 	else
446 		PVOP_VCALL2(mmu.set_pte, ptep, pte.pte);
447 }
448 
449 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
450 			      pte_t *ptep, pte_t pte)
451 {
452 	if (sizeof(pteval_t) > sizeof(long))
453 		/* 5 arg words */
454 		pv_ops.mmu.set_pte_at(mm, addr, ptep, pte);
455 	else
456 		PVOP_VCALL4(mmu.set_pte_at, mm, addr, ptep, pte.pte);
457 }
458 
459 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
460 {
461 	pmdval_t val = native_pmd_val(pmd);
462 
463 	if (sizeof(pmdval_t) > sizeof(long))
464 		PVOP_VCALL3(mmu.set_pmd, pmdp, val, (u64)val >> 32);
465 	else
466 		PVOP_VCALL2(mmu.set_pmd, pmdp, val);
467 }
468 
469 #if CONFIG_PGTABLE_LEVELS >= 3
470 static inline pmd_t __pmd(pmdval_t val)
471 {
472 	pmdval_t ret;
473 
474 	if (sizeof(pmdval_t) > sizeof(long))
475 		ret = PVOP_CALLEE2(pmdval_t, mmu.make_pmd, val, (u64)val >> 32);
476 	else
477 		ret = PVOP_CALLEE1(pmdval_t, mmu.make_pmd, val);
478 
479 	return (pmd_t) { ret };
480 }
481 
482 static inline pmdval_t pmd_val(pmd_t pmd)
483 {
484 	pmdval_t ret;
485 
486 	if (sizeof(pmdval_t) > sizeof(long))
487 		ret =  PVOP_CALLEE2(pmdval_t, mmu.pmd_val,
488 				    pmd.pmd, (u64)pmd.pmd >> 32);
489 	else
490 		ret =  PVOP_CALLEE1(pmdval_t, mmu.pmd_val, pmd.pmd);
491 
492 	return ret;
493 }
494 
495 static inline void set_pud(pud_t *pudp, pud_t pud)
496 {
497 	pudval_t val = native_pud_val(pud);
498 
499 	if (sizeof(pudval_t) > sizeof(long))
500 		PVOP_VCALL3(mmu.set_pud, pudp, val, (u64)val >> 32);
501 	else
502 		PVOP_VCALL2(mmu.set_pud, pudp, val);
503 }
504 #if CONFIG_PGTABLE_LEVELS >= 4
505 static inline pud_t __pud(pudval_t val)
506 {
507 	pudval_t ret;
508 
509 	ret = PVOP_CALLEE1(pudval_t, mmu.make_pud, val);
510 
511 	return (pud_t) { ret };
512 }
513 
514 static inline pudval_t pud_val(pud_t pud)
515 {
516 	return PVOP_CALLEE1(pudval_t, mmu.pud_val, pud.pud);
517 }
518 
519 static inline void pud_clear(pud_t *pudp)
520 {
521 	set_pud(pudp, __pud(0));
522 }
523 
524 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d)
525 {
526 	p4dval_t val = native_p4d_val(p4d);
527 
528 	PVOP_VCALL2(mmu.set_p4d, p4dp, val);
529 }
530 
531 #if CONFIG_PGTABLE_LEVELS >= 5
532 
533 static inline p4d_t __p4d(p4dval_t val)
534 {
535 	p4dval_t ret = PVOP_CALLEE1(p4dval_t, mmu.make_p4d, val);
536 
537 	return (p4d_t) { ret };
538 }
539 
540 static inline p4dval_t p4d_val(p4d_t p4d)
541 {
542 	return PVOP_CALLEE1(p4dval_t, mmu.p4d_val, p4d.p4d);
543 }
544 
545 static inline void __set_pgd(pgd_t *pgdp, pgd_t pgd)
546 {
547 	PVOP_VCALL2(mmu.set_pgd, pgdp, native_pgd_val(pgd));
548 }
549 
550 #define set_pgd(pgdp, pgdval) do {					\
551 	if (pgtable_l5_enabled())						\
552 		__set_pgd(pgdp, pgdval);				\
553 	else								\
554 		set_p4d((p4d_t *)(pgdp), (p4d_t) { (pgdval).pgd });	\
555 } while (0)
556 
557 #define pgd_clear(pgdp) do {						\
558 	if (pgtable_l5_enabled())						\
559 		set_pgd(pgdp, __pgd(0));				\
560 } while (0)
561 
562 #endif  /* CONFIG_PGTABLE_LEVELS == 5 */
563 
564 static inline void p4d_clear(p4d_t *p4dp)
565 {
566 	set_p4d(p4dp, __p4d(0));
567 }
568 
569 #endif	/* CONFIG_PGTABLE_LEVELS == 4 */
570 
571 #endif	/* CONFIG_PGTABLE_LEVELS >= 3 */
572 
573 #ifdef CONFIG_X86_PAE
574 /* Special-case pte-setting operations for PAE, which can't update a
575    64-bit pte atomically */
576 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
577 {
578 	PVOP_VCALL3(mmu.set_pte_atomic, ptep, pte.pte, pte.pte >> 32);
579 }
580 
581 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
582 			     pte_t *ptep)
583 {
584 	PVOP_VCALL3(mmu.pte_clear, mm, addr, ptep);
585 }
586 
587 static inline void pmd_clear(pmd_t *pmdp)
588 {
589 	PVOP_VCALL1(mmu.pmd_clear, pmdp);
590 }
591 #else  /* !CONFIG_X86_PAE */
592 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
593 {
594 	set_pte(ptep, pte);
595 }
596 
597 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
598 			     pte_t *ptep)
599 {
600 	set_pte_at(mm, addr, ptep, __pte(0));
601 }
602 
603 static inline void pmd_clear(pmd_t *pmdp)
604 {
605 	set_pmd(pmdp, __pmd(0));
606 }
607 #endif	/* CONFIG_X86_PAE */
608 
609 #define  __HAVE_ARCH_START_CONTEXT_SWITCH
610 static inline void arch_start_context_switch(struct task_struct *prev)
611 {
612 	PVOP_VCALL1(cpu.start_context_switch, prev);
613 }
614 
615 static inline void arch_end_context_switch(struct task_struct *next)
616 {
617 	PVOP_VCALL1(cpu.end_context_switch, next);
618 }
619 
620 #define  __HAVE_ARCH_ENTER_LAZY_MMU_MODE
621 static inline void arch_enter_lazy_mmu_mode(void)
622 {
623 	PVOP_VCALL0(mmu.lazy_mode.enter);
624 }
625 
626 static inline void arch_leave_lazy_mmu_mode(void)
627 {
628 	PVOP_VCALL0(mmu.lazy_mode.leave);
629 }
630 
631 static inline void arch_flush_lazy_mmu_mode(void)
632 {
633 	PVOP_VCALL0(mmu.lazy_mode.flush);
634 }
635 
636 static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx,
637 				phys_addr_t phys, pgprot_t flags)
638 {
639 	pv_ops.mmu.set_fixmap(idx, phys, flags);
640 }
641 #endif
642 
643 #if defined(CONFIG_SMP) && defined(CONFIG_PARAVIRT_SPINLOCKS)
644 
645 static __always_inline void pv_queued_spin_lock_slowpath(struct qspinlock *lock,
646 							u32 val)
647 {
648 	PVOP_VCALL2(lock.queued_spin_lock_slowpath, lock, val);
649 }
650 
651 static __always_inline void pv_queued_spin_unlock(struct qspinlock *lock)
652 {
653 	PVOP_VCALLEE1(lock.queued_spin_unlock, lock);
654 }
655 
656 static __always_inline void pv_wait(u8 *ptr, u8 val)
657 {
658 	PVOP_VCALL2(lock.wait, ptr, val);
659 }
660 
661 static __always_inline void pv_kick(int cpu)
662 {
663 	PVOP_VCALL1(lock.kick, cpu);
664 }
665 
666 static __always_inline bool pv_vcpu_is_preempted(long cpu)
667 {
668 	return PVOP_CALLEE1(bool, lock.vcpu_is_preempted, cpu);
669 }
670 
671 void __raw_callee_save___native_queued_spin_unlock(struct qspinlock *lock);
672 bool __raw_callee_save___native_vcpu_is_preempted(long cpu);
673 
674 #endif /* SMP && PARAVIRT_SPINLOCKS */
675 
676 #ifdef CONFIG_X86_32
677 #define PV_SAVE_REGS "pushl %ecx; pushl %edx;"
678 #define PV_RESTORE_REGS "popl %edx; popl %ecx;"
679 
680 /* save and restore all caller-save registers, except return value */
681 #define PV_SAVE_ALL_CALLER_REGS		"pushl %ecx;"
682 #define PV_RESTORE_ALL_CALLER_REGS	"popl  %ecx;"
683 
684 #define PV_FLAGS_ARG "0"
685 #define PV_EXTRA_CLOBBERS
686 #define PV_VEXTRA_CLOBBERS
687 #else
688 /* save and restore all caller-save registers, except return value */
689 #define PV_SAVE_ALL_CALLER_REGS						\
690 	"push %rcx;"							\
691 	"push %rdx;"							\
692 	"push %rsi;"							\
693 	"push %rdi;"							\
694 	"push %r8;"							\
695 	"push %r9;"							\
696 	"push %r10;"							\
697 	"push %r11;"
698 #define PV_RESTORE_ALL_CALLER_REGS					\
699 	"pop %r11;"							\
700 	"pop %r10;"							\
701 	"pop %r9;"							\
702 	"pop %r8;"							\
703 	"pop %rdi;"							\
704 	"pop %rsi;"							\
705 	"pop %rdx;"							\
706 	"pop %rcx;"
707 
708 /* We save some registers, but all of them, that's too much. We clobber all
709  * caller saved registers but the argument parameter */
710 #define PV_SAVE_REGS "pushq %%rdi;"
711 #define PV_RESTORE_REGS "popq %%rdi;"
712 #define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx", "rsi"
713 #define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx", "rsi"
714 #define PV_FLAGS_ARG "D"
715 #endif
716 
717 /*
718  * Generate a thunk around a function which saves all caller-save
719  * registers except for the return value.  This allows C functions to
720  * be called from assembler code where fewer than normal registers are
721  * available.  It may also help code generation around calls from C
722  * code if the common case doesn't use many registers.
723  *
724  * When a callee is wrapped in a thunk, the caller can assume that all
725  * arg regs and all scratch registers are preserved across the
726  * call. The return value in rax/eax will not be saved, even for void
727  * functions.
728  */
729 #define PV_THUNK_NAME(func) "__raw_callee_save_" #func
730 #define PV_CALLEE_SAVE_REGS_THUNK(func)					\
731 	extern typeof(func) __raw_callee_save_##func;			\
732 									\
733 	asm(".pushsection .text;"					\
734 	    ".globl " PV_THUNK_NAME(func) ";"				\
735 	    ".type " PV_THUNK_NAME(func) ", @function;"			\
736 	    PV_THUNK_NAME(func) ":"					\
737 	    FRAME_BEGIN							\
738 	    PV_SAVE_ALL_CALLER_REGS					\
739 	    "call " #func ";"						\
740 	    PV_RESTORE_ALL_CALLER_REGS					\
741 	    FRAME_END							\
742 	    "ret;"							\
743 	    ".popsection")
744 
745 /* Get a reference to a callee-save function */
746 #define PV_CALLEE_SAVE(func)						\
747 	((struct paravirt_callee_save) { __raw_callee_save_##func })
748 
749 /* Promise that "func" already uses the right calling convention */
750 #define __PV_IS_CALLEE_SAVE(func)			\
751 	((struct paravirt_callee_save) { func })
752 
753 #ifdef CONFIG_PARAVIRT_XXL
754 static inline notrace unsigned long arch_local_save_flags(void)
755 {
756 	return PVOP_CALLEE0(unsigned long, irq.save_fl);
757 }
758 
759 static inline notrace void arch_local_irq_restore(unsigned long f)
760 {
761 	PVOP_VCALLEE1(irq.restore_fl, f);
762 }
763 
764 static inline notrace void arch_local_irq_disable(void)
765 {
766 	PVOP_VCALLEE0(irq.irq_disable);
767 }
768 
769 static inline notrace void arch_local_irq_enable(void)
770 {
771 	PVOP_VCALLEE0(irq.irq_enable);
772 }
773 
774 static inline notrace unsigned long arch_local_irq_save(void)
775 {
776 	unsigned long f;
777 
778 	f = arch_local_save_flags();
779 	arch_local_irq_disable();
780 	return f;
781 }
782 #endif
783 
784 
785 /* Make sure as little as possible of this mess escapes. */
786 #undef PARAVIRT_CALL
787 #undef __PVOP_CALL
788 #undef __PVOP_VCALL
789 #undef PVOP_VCALL0
790 #undef PVOP_CALL0
791 #undef PVOP_VCALL1
792 #undef PVOP_CALL1
793 #undef PVOP_VCALL2
794 #undef PVOP_CALL2
795 #undef PVOP_VCALL3
796 #undef PVOP_CALL3
797 #undef PVOP_VCALL4
798 #undef PVOP_CALL4
799 
800 extern void default_banner(void);
801 
802 #else  /* __ASSEMBLY__ */
803 
804 #define _PVSITE(ptype, ops, word, algn)		\
805 771:;						\
806 	ops;					\
807 772:;						\
808 	.pushsection .parainstructions,"a";	\
809 	 .align	algn;				\
810 	 word 771b;				\
811 	 .byte ptype;				\
812 	 .byte 772b-771b;			\
813 	.popsection
814 
815 
816 #define COND_PUSH(set, mask, reg)			\
817 	.if ((~(set)) & mask); push %reg; .endif
818 #define COND_POP(set, mask, reg)			\
819 	.if ((~(set)) & mask); pop %reg; .endif
820 
821 #ifdef CONFIG_X86_64
822 
823 #define PV_SAVE_REGS(set)			\
824 	COND_PUSH(set, CLBR_RAX, rax);		\
825 	COND_PUSH(set, CLBR_RCX, rcx);		\
826 	COND_PUSH(set, CLBR_RDX, rdx);		\
827 	COND_PUSH(set, CLBR_RSI, rsi);		\
828 	COND_PUSH(set, CLBR_RDI, rdi);		\
829 	COND_PUSH(set, CLBR_R8, r8);		\
830 	COND_PUSH(set, CLBR_R9, r9);		\
831 	COND_PUSH(set, CLBR_R10, r10);		\
832 	COND_PUSH(set, CLBR_R11, r11)
833 #define PV_RESTORE_REGS(set)			\
834 	COND_POP(set, CLBR_R11, r11);		\
835 	COND_POP(set, CLBR_R10, r10);		\
836 	COND_POP(set, CLBR_R9, r9);		\
837 	COND_POP(set, CLBR_R8, r8);		\
838 	COND_POP(set, CLBR_RDI, rdi);		\
839 	COND_POP(set, CLBR_RSI, rsi);		\
840 	COND_POP(set, CLBR_RDX, rdx);		\
841 	COND_POP(set, CLBR_RCX, rcx);		\
842 	COND_POP(set, CLBR_RAX, rax)
843 
844 #define PARA_PATCH(off)		((off) / 8)
845 #define PARA_SITE(ptype, ops)	_PVSITE(ptype, ops, .quad, 8)
846 #define PARA_INDIRECT(addr)	*addr(%rip)
847 #else
848 #define PV_SAVE_REGS(set)			\
849 	COND_PUSH(set, CLBR_EAX, eax);		\
850 	COND_PUSH(set, CLBR_EDI, edi);		\
851 	COND_PUSH(set, CLBR_ECX, ecx);		\
852 	COND_PUSH(set, CLBR_EDX, edx)
853 #define PV_RESTORE_REGS(set)			\
854 	COND_POP(set, CLBR_EDX, edx);		\
855 	COND_POP(set, CLBR_ECX, ecx);		\
856 	COND_POP(set, CLBR_EDI, edi);		\
857 	COND_POP(set, CLBR_EAX, eax)
858 
859 #define PARA_PATCH(off)		((off) / 4)
860 #define PARA_SITE(ptype, ops)	_PVSITE(ptype, ops, .long, 4)
861 #define PARA_INDIRECT(addr)	*%cs:addr
862 #endif
863 
864 #ifdef CONFIG_PARAVIRT_XXL
865 #define INTERRUPT_RETURN						\
866 	PARA_SITE(PARA_PATCH(PV_CPU_iret),				\
867 		  ANNOTATE_RETPOLINE_SAFE;				\
868 		  jmp PARA_INDIRECT(pv_ops+PV_CPU_iret);)
869 
870 #define DISABLE_INTERRUPTS(clobbers)					\
871 	PARA_SITE(PARA_PATCH(PV_IRQ_irq_disable),			\
872 		  PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE);		\
873 		  ANNOTATE_RETPOLINE_SAFE;				\
874 		  call PARA_INDIRECT(pv_ops+PV_IRQ_irq_disable);	\
875 		  PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
876 
877 #define ENABLE_INTERRUPTS(clobbers)					\
878 	PARA_SITE(PARA_PATCH(PV_IRQ_irq_enable),			\
879 		  PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE);		\
880 		  ANNOTATE_RETPOLINE_SAFE;				\
881 		  call PARA_INDIRECT(pv_ops+PV_IRQ_irq_enable);		\
882 		  PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
883 #endif
884 
885 #ifdef CONFIG_X86_64
886 #ifdef CONFIG_PARAVIRT_XXL
887 /*
888  * If swapgs is used while the userspace stack is still current,
889  * there's no way to call a pvop.  The PV replacement *must* be
890  * inlined, or the swapgs instruction must be trapped and emulated.
891  */
892 #define SWAPGS_UNSAFE_STACK						\
893 	PARA_SITE(PARA_PATCH(PV_CPU_swapgs), swapgs)
894 
895 /*
896  * Note: swapgs is very special, and in practise is either going to be
897  * implemented with a single "swapgs" instruction or something very
898  * special.  Either way, we don't need to save any registers for
899  * it.
900  */
901 #define SWAPGS								\
902 	PARA_SITE(PARA_PATCH(PV_CPU_swapgs),				\
903 		  ANNOTATE_RETPOLINE_SAFE;				\
904 		  call PARA_INDIRECT(pv_ops+PV_CPU_swapgs);		\
905 		 )
906 #endif
907 
908 #define GET_CR2_INTO_RAX				\
909 	ANNOTATE_RETPOLINE_SAFE;				\
910 	call PARA_INDIRECT(pv_ops+PV_MMU_read_cr2);
911 
912 #ifdef CONFIG_PARAVIRT_XXL
913 #define USERGS_SYSRET64							\
914 	PARA_SITE(PARA_PATCH(PV_CPU_usergs_sysret64),			\
915 		  ANNOTATE_RETPOLINE_SAFE;				\
916 		  jmp PARA_INDIRECT(pv_ops+PV_CPU_usergs_sysret64);)
917 
918 #ifdef CONFIG_DEBUG_ENTRY
919 #define SAVE_FLAGS(clobbers)                                        \
920 	PARA_SITE(PARA_PATCH(PV_IRQ_save_fl),			    \
921 		  PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE);        \
922 		  ANNOTATE_RETPOLINE_SAFE;			    \
923 		  call PARA_INDIRECT(pv_ops+PV_IRQ_save_fl);	    \
924 		  PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
925 #endif
926 #endif
927 
928 #endif	/* CONFIG_X86_32 */
929 
930 #endif /* __ASSEMBLY__ */
931 #else  /* CONFIG_PARAVIRT */
932 # define default_banner x86_init_noop
933 #endif /* !CONFIG_PARAVIRT */
934 
935 #ifndef __ASSEMBLY__
936 #ifndef CONFIG_PARAVIRT_XXL
937 static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm,
938 					  struct mm_struct *mm)
939 {
940 }
941 #endif
942 
943 #ifndef CONFIG_PARAVIRT
944 static inline void paravirt_arch_exit_mmap(struct mm_struct *mm)
945 {
946 }
947 #endif
948 #endif /* __ASSEMBLY__ */
949 #endif /* _ASM_X86_PARAVIRT_H */
950