xref: /openbmc/linux/arch/x86/include/asm/paravirt.h (revision a44d924c) 
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_PARAVIRT_H
3 #define _ASM_X86_PARAVIRT_H
4 /* Various instructions on x86 need to be replaced for
5  * para-virtualization: those hooks are defined here. */
6 
7 #ifdef CONFIG_PARAVIRT
8 #include <asm/pgtable_types.h>
9 #include <asm/asm.h>
10 #include <asm/nospec-branch.h>
11 
12 #include <asm/paravirt_types.h>
13 
14 #ifndef __ASSEMBLY__
15 #include <linux/bug.h>
16 #include <linux/types.h>
17 #include <linux/cpumask.h>
18 #include <asm/frame.h>
19 
20 static inline unsigned long long paravirt_sched_clock(void)
21 {
22 	return PVOP_CALL0(unsigned long long, time.sched_clock);
23 }
24 
25 struct static_key;
26 extern struct static_key paravirt_steal_enabled;
27 extern struct static_key paravirt_steal_rq_enabled;
28 
29 __visible void __native_queued_spin_unlock(struct qspinlock *lock);
30 bool pv_is_native_spin_unlock(void);
31 __visible bool __native_vcpu_is_preempted(long cpu);
32 bool pv_is_native_vcpu_is_preempted(void);
33 
34 static inline u64 paravirt_steal_clock(int cpu)
35 {
36 	return PVOP_CALL1(u64, time.steal_clock, cpu);
37 }
38 
39 /* The paravirtualized I/O functions */
40 static inline void slow_down_io(void)
41 {
42 	pv_ops.cpu.io_delay();
43 #ifdef REALLY_SLOW_IO
44 	pv_ops.cpu.io_delay();
45 	pv_ops.cpu.io_delay();
46 	pv_ops.cpu.io_delay();
47 #endif
48 }
49 
50 static inline void __flush_tlb(void)
51 {
52 	PVOP_VCALL0(mmu.flush_tlb_user);
53 }
54 
55 static inline void __flush_tlb_global(void)
56 {
57 	PVOP_VCALL0(mmu.flush_tlb_kernel);
58 }
59 
60 static inline void __flush_tlb_one_user(unsigned long addr)
61 {
62 	PVOP_VCALL1(mmu.flush_tlb_one_user, addr);
63 }
64 
65 static inline void flush_tlb_others(const struct cpumask *cpumask,
66 				    const struct flush_tlb_info *info)
67 {
68 	PVOP_VCALL2(mmu.flush_tlb_others, cpumask, info);
69 }
70 
71 static inline void paravirt_tlb_remove_table(struct mmu_gather *tlb, void *table)
72 {
73 	PVOP_VCALL2(mmu.tlb_remove_table, tlb, table);
74 }
75 
76 static inline void paravirt_arch_exit_mmap(struct mm_struct *mm)
77 {
78 	PVOP_VCALL1(mmu.exit_mmap, mm);
79 }
80 
81 #ifdef CONFIG_PARAVIRT_XXL
82 static inline void load_sp0(unsigned long sp0)
83 {
84 	PVOP_VCALL1(cpu.load_sp0, sp0);
85 }
86 
87 /* The paravirtualized CPUID instruction. */
88 static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
89 			   unsigned int *ecx, unsigned int *edx)
90 {
91 	PVOP_VCALL4(cpu.cpuid, eax, ebx, ecx, edx);
92 }
93 
94 /*
95  * These special macros can be used to get or set a debugging register
96  */
97 static inline unsigned long paravirt_get_debugreg(int reg)
98 {
99 	return PVOP_CALL1(unsigned long, cpu.get_debugreg, reg);
100 }
101 #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg)
102 static inline void set_debugreg(unsigned long val, int reg)
103 {
104 	PVOP_VCALL2(cpu.set_debugreg, reg, val);
105 }
106 
107 static inline unsigned long read_cr0(void)
108 {
109 	return PVOP_CALL0(unsigned long, cpu.read_cr0);
110 }
111 
112 static inline void write_cr0(unsigned long x)
113 {
114 	PVOP_VCALL1(cpu.write_cr0, x);
115 }
116 
117 static inline unsigned long read_cr2(void)
118 {
119 	return PVOP_CALL0(unsigned long, mmu.read_cr2);
120 }
121 
122 static inline void write_cr2(unsigned long x)
123 {
124 	PVOP_VCALL1(mmu.write_cr2, x);
125 }
126 
127 static inline unsigned long __read_cr3(void)
128 {
129 	return PVOP_CALL0(unsigned long, mmu.read_cr3);
130 }
131 
132 static inline void write_cr3(unsigned long x)
133 {
134 	PVOP_VCALL1(mmu.write_cr3, x);
135 }
136 
137 static inline void __write_cr4(unsigned long x)
138 {
139 	PVOP_VCALL1(cpu.write_cr4, x);
140 }
141 
142 #ifdef CONFIG_X86_64
143 static inline unsigned long read_cr8(void)
144 {
145 	return PVOP_CALL0(unsigned long, cpu.read_cr8);
146 }
147 
148 static inline void write_cr8(unsigned long x)
149 {
150 	PVOP_VCALL1(cpu.write_cr8, x);
151 }
152 #endif
153 
154 static inline void arch_safe_halt(void)
155 {
156 	PVOP_VCALL0(irq.safe_halt);
157 }
158 
159 static inline void halt(void)
160 {
161 	PVOP_VCALL0(irq.halt);
162 }
163 
164 static inline void wbinvd(void)
165 {
166 	PVOP_VCALL0(cpu.wbinvd);
167 }
168 
169 #define get_kernel_rpl()  (pv_info.kernel_rpl)
170 
171 static inline u64 paravirt_read_msr(unsigned msr)
172 {
173 	return PVOP_CALL1(u64, cpu.read_msr, msr);
174 }
175 
176 static inline void paravirt_write_msr(unsigned msr,
177 				      unsigned low, unsigned high)
178 {
179 	PVOP_VCALL3(cpu.write_msr, msr, low, high);
180 }
181 
182 static inline u64 paravirt_read_msr_safe(unsigned msr, int *err)
183 {
184 	return PVOP_CALL2(u64, cpu.read_msr_safe, msr, err);
185 }
186 
187 static inline int paravirt_write_msr_safe(unsigned msr,
188 					  unsigned low, unsigned high)
189 {
190 	return PVOP_CALL3(int, cpu.write_msr_safe, msr, low, high);
191 }
192 
193 #define rdmsr(msr, val1, val2)			\
194 do {						\
195 	u64 _l = paravirt_read_msr(msr);	\
196 	val1 = (u32)_l;				\
197 	val2 = _l >> 32;			\
198 } while (0)
199 
200 #define wrmsr(msr, val1, val2)			\
201 do {						\
202 	paravirt_write_msr(msr, val1, val2);	\
203 } while (0)
204 
205 #define rdmsrl(msr, val)			\
206 do {						\
207 	val = paravirt_read_msr(msr);		\
208 } while (0)
209 
210 static inline void wrmsrl(unsigned msr, u64 val)
211 {
212 	wrmsr(msr, (u32)val, (u32)(val>>32));
213 }
214 
215 #define wrmsr_safe(msr, a, b)	paravirt_write_msr_safe(msr, a, b)
216 
217 /* rdmsr with exception handling */
218 #define rdmsr_safe(msr, a, b)				\
219 ({							\
220 	int _err;					\
221 	u64 _l = paravirt_read_msr_safe(msr, &_err);	\
222 	(*a) = (u32)_l;					\
223 	(*b) = _l >> 32;				\
224 	_err;						\
225 })
226 
227 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
228 {
229 	int err;
230 
231 	*p = paravirt_read_msr_safe(msr, &err);
232 	return err;
233 }
234 
235 static inline unsigned long long paravirt_read_pmc(int counter)
236 {
237 	return PVOP_CALL1(u64, cpu.read_pmc, counter);
238 }
239 
240 #define rdpmc(counter, low, high)		\
241 do {						\
242 	u64 _l = paravirt_read_pmc(counter);	\
243 	low = (u32)_l;				\
244 	high = _l >> 32;			\
245 } while (0)
246 
247 #define rdpmcl(counter, val) ((val) = paravirt_read_pmc(counter))
248 
249 static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
250 {
251 	PVOP_VCALL2(cpu.alloc_ldt, ldt, entries);
252 }
253 
254 static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
255 {
256 	PVOP_VCALL2(cpu.free_ldt, ldt, entries);
257 }
258 
259 static inline void load_TR_desc(void)
260 {
261 	PVOP_VCALL0(cpu.load_tr_desc);
262 }
263 static inline void load_gdt(const struct desc_ptr *dtr)
264 {
265 	PVOP_VCALL1(cpu.load_gdt, dtr);
266 }
267 static inline void load_idt(const struct desc_ptr *dtr)
268 {
269 	PVOP_VCALL1(cpu.load_idt, dtr);
270 }
271 static inline void set_ldt(const void *addr, unsigned entries)
272 {
273 	PVOP_VCALL2(cpu.set_ldt, addr, entries);
274 }
275 static inline unsigned long paravirt_store_tr(void)
276 {
277 	return PVOP_CALL0(unsigned long, cpu.store_tr);
278 }
279 
280 #define store_tr(tr)	((tr) = paravirt_store_tr())
281 static inline void load_TLS(struct thread_struct *t, unsigned cpu)
282 {
283 	PVOP_VCALL2(cpu.load_tls, t, cpu);
284 }
285 
286 #ifdef CONFIG_X86_64
287 static inline void load_gs_index(unsigned int gs)
288 {
289 	PVOP_VCALL1(cpu.load_gs_index, gs);
290 }
291 #endif
292 
293 static inline void write_ldt_entry(struct desc_struct *dt, int entry,
294 				   const void *desc)
295 {
296 	PVOP_VCALL3(cpu.write_ldt_entry, dt, entry, desc);
297 }
298 
299 static inline void write_gdt_entry(struct desc_struct *dt, int entry,
300 				   void *desc, int type)
301 {
302 	PVOP_VCALL4(cpu.write_gdt_entry, dt, entry, desc, type);
303 }
304 
305 static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g)
306 {
307 	PVOP_VCALL3(cpu.write_idt_entry, dt, entry, g);
308 }
309 static inline void set_iopl_mask(unsigned mask)
310 {
311 	PVOP_VCALL1(cpu.set_iopl_mask, mask);
312 }
313 
314 static inline void paravirt_activate_mm(struct mm_struct *prev,
315 					struct mm_struct *next)
316 {
317 	PVOP_VCALL2(mmu.activate_mm, prev, next);
318 }
319 
320 static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm,
321 					  struct mm_struct *mm)
322 {
323 	PVOP_VCALL2(mmu.dup_mmap, oldmm, mm);
324 }
325 
326 static inline int paravirt_pgd_alloc(struct mm_struct *mm)
327 {
328 	return PVOP_CALL1(int, mmu.pgd_alloc, mm);
329 }
330 
331 static inline void paravirt_pgd_free(struct mm_struct *mm, pgd_t *pgd)
332 {
333 	PVOP_VCALL2(mmu.pgd_free, mm, pgd);
334 }
335 
336 static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned long pfn)
337 {
338 	PVOP_VCALL2(mmu.alloc_pte, mm, pfn);
339 }
340 static inline void paravirt_release_pte(unsigned long pfn)
341 {
342 	PVOP_VCALL1(mmu.release_pte, pfn);
343 }
344 
345 static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned long pfn)
346 {
347 	PVOP_VCALL2(mmu.alloc_pmd, mm, pfn);
348 }
349 
350 static inline void paravirt_release_pmd(unsigned long pfn)
351 {
352 	PVOP_VCALL1(mmu.release_pmd, pfn);
353 }
354 
355 static inline void paravirt_alloc_pud(struct mm_struct *mm, unsigned long pfn)
356 {
357 	PVOP_VCALL2(mmu.alloc_pud, mm, pfn);
358 }
359 static inline void paravirt_release_pud(unsigned long pfn)
360 {
361 	PVOP_VCALL1(mmu.release_pud, pfn);
362 }
363 
364 static inline void paravirt_alloc_p4d(struct mm_struct *mm, unsigned long pfn)
365 {
366 	PVOP_VCALL2(mmu.alloc_p4d, mm, pfn);
367 }
368 
369 static inline void paravirt_release_p4d(unsigned long pfn)
370 {
371 	PVOP_VCALL1(mmu.release_p4d, pfn);
372 }
373 
374 static inline pte_t __pte(pteval_t val)
375 {
376 	pteval_t ret;
377 
378 	if (sizeof(pteval_t) > sizeof(long))
379 		ret = PVOP_CALLEE2(pteval_t, mmu.make_pte, val, (u64)val >> 32);
380 	else
381 		ret = PVOP_CALLEE1(pteval_t, mmu.make_pte, val);
382 
383 	return (pte_t) { .pte = ret };
384 }
385 
386 static inline pteval_t pte_val(pte_t pte)
387 {
388 	pteval_t ret;
389 
390 	if (sizeof(pteval_t) > sizeof(long))
391 		ret = PVOP_CALLEE2(pteval_t, mmu.pte_val,
392 				   pte.pte, (u64)pte.pte >> 32);
393 	else
394 		ret = PVOP_CALLEE1(pteval_t, mmu.pte_val, pte.pte);
395 
396 	return ret;
397 }
398 
399 static inline pgd_t __pgd(pgdval_t val)
400 {
401 	pgdval_t ret;
402 
403 	if (sizeof(pgdval_t) > sizeof(long))
404 		ret = PVOP_CALLEE2(pgdval_t, mmu.make_pgd, val, (u64)val >> 32);
405 	else
406 		ret = PVOP_CALLEE1(pgdval_t, mmu.make_pgd, val);
407 
408 	return (pgd_t) { ret };
409 }
410 
411 static inline pgdval_t pgd_val(pgd_t pgd)
412 {
413 	pgdval_t ret;
414 
415 	if (sizeof(pgdval_t) > sizeof(long))
416 		ret =  PVOP_CALLEE2(pgdval_t, mmu.pgd_val,
417 				    pgd.pgd, (u64)pgd.pgd >> 32);
418 	else
419 		ret =  PVOP_CALLEE1(pgdval_t, mmu.pgd_val, pgd.pgd);
420 
421 	return ret;
422 }
423 
424 #define  __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
425 static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, unsigned long addr,
426 					   pte_t *ptep)
427 {
428 	pteval_t ret;
429 
430 	ret = PVOP_CALL3(pteval_t, mmu.ptep_modify_prot_start, mm, addr, ptep);
431 
432 	return (pte_t) { .pte = ret };
433 }
434 
435 static inline void ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr,
436 					   pte_t *ptep, pte_t pte)
437 {
438 	if (sizeof(pteval_t) > sizeof(long))
439 		/* 5 arg words */
440 		pv_ops.mmu.ptep_modify_prot_commit(mm, addr, ptep, pte);
441 	else
442 		PVOP_VCALL4(mmu.ptep_modify_prot_commit,
443 			    mm, addr, ptep, pte.pte);
444 }
445 
446 static inline void set_pte(pte_t *ptep, pte_t pte)
447 {
448 	if (sizeof(pteval_t) > sizeof(long))
449 		PVOP_VCALL3(mmu.set_pte, ptep, pte.pte, (u64)pte.pte >> 32);
450 	else
451 		PVOP_VCALL2(mmu.set_pte, ptep, pte.pte);
452 }
453 
454 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
455 			      pte_t *ptep, pte_t pte)
456 {
457 	if (sizeof(pteval_t) > sizeof(long))
458 		/* 5 arg words */
459 		pv_ops.mmu.set_pte_at(mm, addr, ptep, pte);
460 	else
461 		PVOP_VCALL4(mmu.set_pte_at, mm, addr, ptep, pte.pte);
462 }
463 
464 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
465 {
466 	pmdval_t val = native_pmd_val(pmd);
467 
468 	if (sizeof(pmdval_t) > sizeof(long))
469 		PVOP_VCALL3(mmu.set_pmd, pmdp, val, (u64)val >> 32);
470 	else
471 		PVOP_VCALL2(mmu.set_pmd, pmdp, val);
472 }
473 
474 #if CONFIG_PGTABLE_LEVELS >= 3
475 static inline pmd_t __pmd(pmdval_t val)
476 {
477 	pmdval_t ret;
478 
479 	if (sizeof(pmdval_t) > sizeof(long))
480 		ret = PVOP_CALLEE2(pmdval_t, mmu.make_pmd, val, (u64)val >> 32);
481 	else
482 		ret = PVOP_CALLEE1(pmdval_t, mmu.make_pmd, val);
483 
484 	return (pmd_t) { ret };
485 }
486 
487 static inline pmdval_t pmd_val(pmd_t pmd)
488 {
489 	pmdval_t ret;
490 
491 	if (sizeof(pmdval_t) > sizeof(long))
492 		ret =  PVOP_CALLEE2(pmdval_t, mmu.pmd_val,
493 				    pmd.pmd, (u64)pmd.pmd >> 32);
494 	else
495 		ret =  PVOP_CALLEE1(pmdval_t, mmu.pmd_val, pmd.pmd);
496 
497 	return ret;
498 }
499 
500 static inline void set_pud(pud_t *pudp, pud_t pud)
501 {
502 	pudval_t val = native_pud_val(pud);
503 
504 	if (sizeof(pudval_t) > sizeof(long))
505 		PVOP_VCALL3(mmu.set_pud, pudp, val, (u64)val >> 32);
506 	else
507 		PVOP_VCALL2(mmu.set_pud, pudp, val);
508 }
509 #if CONFIG_PGTABLE_LEVELS >= 4
510 static inline pud_t __pud(pudval_t val)
511 {
512 	pudval_t ret;
513 
514 	ret = PVOP_CALLEE1(pudval_t, mmu.make_pud, val);
515 
516 	return (pud_t) { ret };
517 }
518 
519 static inline pudval_t pud_val(pud_t pud)
520 {
521 	return PVOP_CALLEE1(pudval_t, mmu.pud_val, pud.pud);
522 }
523 
524 static inline void pud_clear(pud_t *pudp)
525 {
526 	set_pud(pudp, __pud(0));
527 }
528 
529 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d)
530 {
531 	p4dval_t val = native_p4d_val(p4d);
532 
533 	PVOP_VCALL2(mmu.set_p4d, p4dp, val);
534 }
535 
536 #if CONFIG_PGTABLE_LEVELS >= 5
537 
538 static inline p4d_t __p4d(p4dval_t val)
539 {
540 	p4dval_t ret = PVOP_CALLEE1(p4dval_t, mmu.make_p4d, val);
541 
542 	return (p4d_t) { ret };
543 }
544 
545 static inline p4dval_t p4d_val(p4d_t p4d)
546 {
547 	return PVOP_CALLEE1(p4dval_t, mmu.p4d_val, p4d.p4d);
548 }
549 
550 static inline void __set_pgd(pgd_t *pgdp, pgd_t pgd)
551 {
552 	PVOP_VCALL2(mmu.set_pgd, pgdp, native_pgd_val(pgd));
553 }
554 
555 #define set_pgd(pgdp, pgdval) do {					\
556 	if (pgtable_l5_enabled())						\
557 		__set_pgd(pgdp, pgdval);				\
558 	else								\
559 		set_p4d((p4d_t *)(pgdp), (p4d_t) { (pgdval).pgd });	\
560 } while (0)
561 
562 #define pgd_clear(pgdp) do {						\
563 	if (pgtable_l5_enabled())						\
564 		set_pgd(pgdp, __pgd(0));				\
565 } while (0)
566 
567 #endif  /* CONFIG_PGTABLE_LEVELS == 5 */
568 
569 static inline void p4d_clear(p4d_t *p4dp)
570 {
571 	set_p4d(p4dp, __p4d(0));
572 }
573 
574 #endif	/* CONFIG_PGTABLE_LEVELS == 4 */
575 
576 #endif	/* CONFIG_PGTABLE_LEVELS >= 3 */
577 
578 #ifdef CONFIG_X86_PAE
579 /* Special-case pte-setting operations for PAE, which can't update a
580    64-bit pte atomically */
581 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
582 {
583 	PVOP_VCALL3(mmu.set_pte_atomic, ptep, pte.pte, pte.pte >> 32);
584 }
585 
586 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
587 			     pte_t *ptep)
588 {
589 	PVOP_VCALL3(mmu.pte_clear, mm, addr, ptep);
590 }
591 
592 static inline void pmd_clear(pmd_t *pmdp)
593 {
594 	PVOP_VCALL1(mmu.pmd_clear, pmdp);
595 }
596 #else  /* !CONFIG_X86_PAE */
597 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
598 {
599 	set_pte(ptep, pte);
600 }
601 
602 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
603 			     pte_t *ptep)
604 {
605 	set_pte_at(mm, addr, ptep, __pte(0));
606 }
607 
608 static inline void pmd_clear(pmd_t *pmdp)
609 {
610 	set_pmd(pmdp, __pmd(0));
611 }
612 #endif	/* CONFIG_X86_PAE */
613 
614 #define  __HAVE_ARCH_START_CONTEXT_SWITCH
615 static inline void arch_start_context_switch(struct task_struct *prev)
616 {
617 	PVOP_VCALL1(cpu.start_context_switch, prev);
618 }
619 
620 static inline void arch_end_context_switch(struct task_struct *next)
621 {
622 	PVOP_VCALL1(cpu.end_context_switch, next);
623 }
624 
625 #define  __HAVE_ARCH_ENTER_LAZY_MMU_MODE
626 static inline void arch_enter_lazy_mmu_mode(void)
627 {
628 	PVOP_VCALL0(mmu.lazy_mode.enter);
629 }
630 
631 static inline void arch_leave_lazy_mmu_mode(void)
632 {
633 	PVOP_VCALL0(mmu.lazy_mode.leave);
634 }
635 
636 static inline void arch_flush_lazy_mmu_mode(void)
637 {
638 	PVOP_VCALL0(mmu.lazy_mode.flush);
639 }
640 
641 static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx,
642 				phys_addr_t phys, pgprot_t flags)
643 {
644 	pv_ops.mmu.set_fixmap(idx, phys, flags);
645 }
646 #endif
647 
648 #if defined(CONFIG_SMP) && defined(CONFIG_PARAVIRT_SPINLOCKS)
649 
650 static __always_inline void pv_queued_spin_lock_slowpath(struct qspinlock *lock,
651 							u32 val)
652 {
653 	PVOP_VCALL2(lock.queued_spin_lock_slowpath, lock, val);
654 }
655 
656 static __always_inline void pv_queued_spin_unlock(struct qspinlock *lock)
657 {
658 	PVOP_VCALLEE1(lock.queued_spin_unlock, lock);
659 }
660 
661 static __always_inline void pv_wait(u8 *ptr, u8 val)
662 {
663 	PVOP_VCALL2(lock.wait, ptr, val);
664 }
665 
666 static __always_inline void pv_kick(int cpu)
667 {
668 	PVOP_VCALL1(lock.kick, cpu);
669 }
670 
671 static __always_inline bool pv_vcpu_is_preempted(long cpu)
672 {
673 	return PVOP_CALLEE1(bool, lock.vcpu_is_preempted, cpu);
674 }
675 
676 void __raw_callee_save___native_queued_spin_unlock(struct qspinlock *lock);
677 bool __raw_callee_save___native_vcpu_is_preempted(long cpu);
678 
679 #endif /* SMP && PARAVIRT_SPINLOCKS */
680 
681 #ifdef CONFIG_X86_32
682 #define PV_SAVE_REGS "pushl %ecx; pushl %edx;"
683 #define PV_RESTORE_REGS "popl %edx; popl %ecx;"
684 
685 /* save and restore all caller-save registers, except return value */
686 #define PV_SAVE_ALL_CALLER_REGS		"pushl %ecx;"
687 #define PV_RESTORE_ALL_CALLER_REGS	"popl  %ecx;"
688 
689 #define PV_FLAGS_ARG "0"
690 #define PV_EXTRA_CLOBBERS
691 #define PV_VEXTRA_CLOBBERS
692 #else
693 /* save and restore all caller-save registers, except return value */
694 #define PV_SAVE_ALL_CALLER_REGS						\
695 	"push %rcx;"							\
696 	"push %rdx;"							\
697 	"push %rsi;"							\
698 	"push %rdi;"							\
699 	"push %r8;"							\
700 	"push %r9;"							\
701 	"push %r10;"							\
702 	"push %r11;"
703 #define PV_RESTORE_ALL_CALLER_REGS					\
704 	"pop %r11;"							\
705 	"pop %r10;"							\
706 	"pop %r9;"							\
707 	"pop %r8;"							\
708 	"pop %rdi;"							\
709 	"pop %rsi;"							\
710 	"pop %rdx;"							\
711 	"pop %rcx;"
712 
713 /* We save some registers, but all of them, that's too much. We clobber all
714  * caller saved registers but the argument parameter */
715 #define PV_SAVE_REGS "pushq %%rdi;"
716 #define PV_RESTORE_REGS "popq %%rdi;"
717 #define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx", "rsi"
718 #define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx", "rsi"
719 #define PV_FLAGS_ARG "D"
720 #endif
721 
722 /*
723  * Generate a thunk around a function which saves all caller-save
724  * registers except for the return value.  This allows C functions to
725  * be called from assembler code where fewer than normal registers are
726  * available.  It may also help code generation around calls from C
727  * code if the common case doesn't use many registers.
728  *
729  * When a callee is wrapped in a thunk, the caller can assume that all
730  * arg regs and all scratch registers are preserved across the
731  * call. The return value in rax/eax will not be saved, even for void
732  * functions.
733  */
734 #define PV_THUNK_NAME(func) "__raw_callee_save_" #func
735 #define PV_CALLEE_SAVE_REGS_THUNK(func)					\
736 	extern typeof(func) __raw_callee_save_##func;			\
737 									\
738 	asm(".pushsection .text;"					\
739 	    ".globl " PV_THUNK_NAME(func) ";"				\
740 	    ".type " PV_THUNK_NAME(func) ", @function;"			\
741 	    PV_THUNK_NAME(func) ":"					\
742 	    FRAME_BEGIN							\
743 	    PV_SAVE_ALL_CALLER_REGS					\
744 	    "call " #func ";"						\
745 	    PV_RESTORE_ALL_CALLER_REGS					\
746 	    FRAME_END							\
747 	    "ret;"							\
748 	    ".popsection")
749 
750 /* Get a reference to a callee-save function */
751 #define PV_CALLEE_SAVE(func)						\
752 	((struct paravirt_callee_save) { __raw_callee_save_##func })
753 
754 /* Promise that "func" already uses the right calling convention */
755 #define __PV_IS_CALLEE_SAVE(func)			\
756 	((struct paravirt_callee_save) { func })
757 
758 #ifdef CONFIG_PARAVIRT_XXL
759 static inline notrace unsigned long arch_local_save_flags(void)
760 {
761 	return PVOP_CALLEE0(unsigned long, irq.save_fl);
762 }
763 
764 static inline notrace void arch_local_irq_restore(unsigned long f)
765 {
766 	PVOP_VCALLEE1(irq.restore_fl, f);
767 }
768 
769 static inline notrace void arch_local_irq_disable(void)
770 {
771 	PVOP_VCALLEE0(irq.irq_disable);
772 }
773 
774 static inline notrace void arch_local_irq_enable(void)
775 {
776 	PVOP_VCALLEE0(irq.irq_enable);
777 }
778 
779 static inline notrace unsigned long arch_local_irq_save(void)
780 {
781 	unsigned long f;
782 
783 	f = arch_local_save_flags();
784 	arch_local_irq_disable();
785 	return f;
786 }
787 #endif
788 
789 
790 /* Make sure as little as possible of this mess escapes. */
791 #undef PARAVIRT_CALL
792 #undef __PVOP_CALL
793 #undef __PVOP_VCALL
794 #undef PVOP_VCALL0
795 #undef PVOP_CALL0
796 #undef PVOP_VCALL1
797 #undef PVOP_CALL1
798 #undef PVOP_VCALL2
799 #undef PVOP_CALL2
800 #undef PVOP_VCALL3
801 #undef PVOP_CALL3
802 #undef PVOP_VCALL4
803 #undef PVOP_CALL4
804 
805 extern void default_banner(void);
806 
807 #else  /* __ASSEMBLY__ */
808 
809 #define _PVSITE(ptype, ops, word, algn)		\
810 771:;						\
811 	ops;					\
812 772:;						\
813 	.pushsection .parainstructions,"a";	\
814 	 .align	algn;				\
815 	 word 771b;				\
816 	 .byte ptype;				\
817 	 .byte 772b-771b;			\
818 	.popsection
819 
820 
821 #define COND_PUSH(set, mask, reg)			\
822 	.if ((~(set)) & mask); push %reg; .endif
823 #define COND_POP(set, mask, reg)			\
824 	.if ((~(set)) & mask); pop %reg; .endif
825 
826 #ifdef CONFIG_X86_64
827 
828 #define PV_SAVE_REGS(set)			\
829 	COND_PUSH(set, CLBR_RAX, rax);		\
830 	COND_PUSH(set, CLBR_RCX, rcx);		\
831 	COND_PUSH(set, CLBR_RDX, rdx);		\
832 	COND_PUSH(set, CLBR_RSI, rsi);		\
833 	COND_PUSH(set, CLBR_RDI, rdi);		\
834 	COND_PUSH(set, CLBR_R8, r8);		\
835 	COND_PUSH(set, CLBR_R9, r9);		\
836 	COND_PUSH(set, CLBR_R10, r10);		\
837 	COND_PUSH(set, CLBR_R11, r11)
838 #define PV_RESTORE_REGS(set)			\
839 	COND_POP(set, CLBR_R11, r11);		\
840 	COND_POP(set, CLBR_R10, r10);		\
841 	COND_POP(set, CLBR_R9, r9);		\
842 	COND_POP(set, CLBR_R8, r8);		\
843 	COND_POP(set, CLBR_RDI, rdi);		\
844 	COND_POP(set, CLBR_RSI, rsi);		\
845 	COND_POP(set, CLBR_RDX, rdx);		\
846 	COND_POP(set, CLBR_RCX, rcx);		\
847 	COND_POP(set, CLBR_RAX, rax)
848 
849 #define PARA_PATCH(off)		((off) / 8)
850 #define PARA_SITE(ptype, ops)	_PVSITE(ptype, ops, .quad, 8)
851 #define PARA_INDIRECT(addr)	*addr(%rip)
852 #else
853 #define PV_SAVE_REGS(set)			\
854 	COND_PUSH(set, CLBR_EAX, eax);		\
855 	COND_PUSH(set, CLBR_EDI, edi);		\
856 	COND_PUSH(set, CLBR_ECX, ecx);		\
857 	COND_PUSH(set, CLBR_EDX, edx)
858 #define PV_RESTORE_REGS(set)			\
859 	COND_POP(set, CLBR_EDX, edx);		\
860 	COND_POP(set, CLBR_ECX, ecx);		\
861 	COND_POP(set, CLBR_EDI, edi);		\
862 	COND_POP(set, CLBR_EAX, eax)
863 
864 #define PARA_PATCH(off)		((off) / 4)
865 #define PARA_SITE(ptype, ops)	_PVSITE(ptype, ops, .long, 4)
866 #define PARA_INDIRECT(addr)	*%cs:addr
867 #endif
868 
869 #ifdef CONFIG_PARAVIRT_XXL
870 #define INTERRUPT_RETURN						\
871 	PARA_SITE(PARA_PATCH(PV_CPU_iret),				\
872 		  ANNOTATE_RETPOLINE_SAFE;				\
873 		  jmp PARA_INDIRECT(pv_ops+PV_CPU_iret);)
874 
875 #define DISABLE_INTERRUPTS(clobbers)					\
876 	PARA_SITE(PARA_PATCH(PV_IRQ_irq_disable),			\
877 		  PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE);		\
878 		  ANNOTATE_RETPOLINE_SAFE;				\
879 		  call PARA_INDIRECT(pv_ops+PV_IRQ_irq_disable);	\
880 		  PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
881 
882 #define ENABLE_INTERRUPTS(clobbers)					\
883 	PARA_SITE(PARA_PATCH(PV_IRQ_irq_enable),			\
884 		  PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE);		\
885 		  ANNOTATE_RETPOLINE_SAFE;				\
886 		  call PARA_INDIRECT(pv_ops+PV_IRQ_irq_enable);		\
887 		  PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
888 #endif
889 
890 #ifdef CONFIG_X86_64
891 #ifdef CONFIG_PARAVIRT_XXL
892 /*
893  * If swapgs is used while the userspace stack is still current,
894  * there's no way to call a pvop.  The PV replacement *must* be
895  * inlined, or the swapgs instruction must be trapped and emulated.
896  */
897 #define SWAPGS_UNSAFE_STACK						\
898 	PARA_SITE(PARA_PATCH(PV_CPU_swapgs), swapgs)
899 
900 /*
901  * Note: swapgs is very special, and in practise is either going to be
902  * implemented with a single "swapgs" instruction or something very
903  * special.  Either way, we don't need to save any registers for
904  * it.
905  */
906 #define SWAPGS								\
907 	PARA_SITE(PARA_PATCH(PV_CPU_swapgs),				\
908 		  ANNOTATE_RETPOLINE_SAFE;				\
909 		  call PARA_INDIRECT(pv_ops+PV_CPU_swapgs);		\
910 		 )
911 #endif
912 
913 #define GET_CR2_INTO_RAX				\
914 	ANNOTATE_RETPOLINE_SAFE;				\
915 	call PARA_INDIRECT(pv_ops+PV_MMU_read_cr2);
916 
917 #ifdef CONFIG_PARAVIRT_XXL
918 #define USERGS_SYSRET64							\
919 	PARA_SITE(PARA_PATCH(PV_CPU_usergs_sysret64),			\
920 		  ANNOTATE_RETPOLINE_SAFE;				\
921 		  jmp PARA_INDIRECT(pv_ops+PV_CPU_usergs_sysret64);)
922 
923 #ifdef CONFIG_DEBUG_ENTRY
924 #define SAVE_FLAGS(clobbers)                                        \
925 	PARA_SITE(PARA_PATCH(PV_IRQ_save_fl),			    \
926 		  PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE);        \
927 		  ANNOTATE_RETPOLINE_SAFE;			    \
928 		  call PARA_INDIRECT(pv_ops+PV_IRQ_save_fl);	    \
929 		  PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
930 #endif
931 #endif
932 
933 #endif	/* CONFIG_X86_32 */
934 
935 #endif /* __ASSEMBLY__ */
936 #else  /* CONFIG_PARAVIRT */
937 # define default_banner x86_init_noop
938 #endif /* !CONFIG_PARAVIRT */
939 
940 #ifndef __ASSEMBLY__
941 #ifndef CONFIG_PARAVIRT_XXL
942 static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm,
943 					  struct mm_struct *mm)
944 {
945 }
946 #endif
947 
948 #ifndef CONFIG_PARAVIRT
949 static inline void paravirt_arch_exit_mmap(struct mm_struct *mm)
950 {
951 }
952 #endif
953 #endif /* __ASSEMBLY__ */
954 #endif /* _ASM_X86_PARAVIRT_H */
955