1bb898558SAl Viro /* OLPC machine specific definitions */ 2bb898558SAl Viro 31965aae3SH. Peter Anvin #ifndef _ASM_X86_OLPC_H 41965aae3SH. Peter Anvin #define _ASM_X86_OLPC_H 5bb898558SAl Viro 6bb898558SAl Viro #include <asm/geode.h> 7bb898558SAl Viro 8bb898558SAl Viro struct olpc_platform_t { 9bb898558SAl Viro int flags; 10bb898558SAl Viro uint32_t boardrev; 11bb898558SAl Viro int ecver; 12bb898558SAl Viro }; 13bb898558SAl Viro 14bb898558SAl Viro #define OLPC_F_PRESENT 0x01 15bb898558SAl Viro #define OLPC_F_DCON 0x02 16bb898558SAl Viro 17bb898558SAl Viro #ifdef CONFIG_OLPC 18bb898558SAl Viro 19bb898558SAl Viro extern struct olpc_platform_t olpc_platform_info; 20bb898558SAl Viro 21bb898558SAl Viro /* 22bb898558SAl Viro * OLPC board IDs contain the major build number within the mask 0x0ff0, 23bb898558SAl Viro * and the minor build number withing 0x000f. Pre-builds have a minor 24bb898558SAl Viro * number less than 8, and normal builds start at 8. For example, 0x0B10 25bb898558SAl Viro * is a PreB1, and 0x0C18 is a C1. 26bb898558SAl Viro */ 27bb898558SAl Viro 28bb898558SAl Viro static inline uint32_t olpc_board(uint8_t id) 29bb898558SAl Viro { 30bb898558SAl Viro return (id << 4) | 0x8; 31bb898558SAl Viro } 32bb898558SAl Viro 33bb898558SAl Viro static inline uint32_t olpc_board_pre(uint8_t id) 34bb898558SAl Viro { 35bb898558SAl Viro return id << 4; 36bb898558SAl Viro } 37bb898558SAl Viro 38bb898558SAl Viro static inline int machine_is_olpc(void) 39bb898558SAl Viro { 40bb898558SAl Viro return (olpc_platform_info.flags & OLPC_F_PRESENT) ? 1 : 0; 41bb898558SAl Viro } 42bb898558SAl Viro 43bb898558SAl Viro /* 44bb898558SAl Viro * The DCON is OLPC's Display Controller. It has a number of unique 45bb898558SAl Viro * features that we might want to take advantage of.. 46bb898558SAl Viro */ 47bb898558SAl Viro static inline int olpc_has_dcon(void) 48bb898558SAl Viro { 49bb898558SAl Viro return (olpc_platform_info.flags & OLPC_F_DCON) ? 1 : 0; 50bb898558SAl Viro } 51bb898558SAl Viro 52bb898558SAl Viro /* 53bb898558SAl Viro * The "Mass Production" version of OLPC's XO is identified as being model 54bb898558SAl Viro * C2. During the prototype phase, the following models (in chronological 55bb898558SAl Viro * order) were created: A1, B1, B2, B3, B4, C1. The A1 through B2 models 56bb898558SAl Viro * were based on Geode GX CPUs, and models after that were based upon 57bb898558SAl Viro * Geode LX CPUs. There were also some hand-assembled models floating 58bb898558SAl Viro * around, referred to as PreB1, PreB2, etc. 59bb898558SAl Viro */ 60bb898558SAl Viro static inline int olpc_board_at_least(uint32_t rev) 61bb898558SAl Viro { 62bb898558SAl Viro return olpc_platform_info.boardrev >= rev; 63bb898558SAl Viro } 64bb898558SAl Viro 65bb898558SAl Viro #else 66bb898558SAl Viro 67bb898558SAl Viro static inline int machine_is_olpc(void) 68bb898558SAl Viro { 69bb898558SAl Viro return 0; 70bb898558SAl Viro } 71bb898558SAl Viro 72bb898558SAl Viro static inline int olpc_has_dcon(void) 73bb898558SAl Viro { 74bb898558SAl Viro return 0; 75bb898558SAl Viro } 76bb898558SAl Viro 77bb898558SAl Viro #endif 78bb898558SAl Viro 79d5d0e88cSThomas Gleixner extern int pci_olpc_init(void); 80d5d0e88cSThomas Gleixner 81bb898558SAl Viro /* EC related functions */ 82bb898558SAl Viro 83bb898558SAl Viro extern int olpc_ec_cmd(unsigned char cmd, unsigned char *inbuf, size_t inlen, 84bb898558SAl Viro unsigned char *outbuf, size_t outlen); 85bb898558SAl Viro 86bb898558SAl Viro extern int olpc_ec_mask_set(uint8_t bits); 87bb898558SAl Viro extern int olpc_ec_mask_unset(uint8_t bits); 88bb898558SAl Viro 89bb898558SAl Viro /* EC commands */ 90bb898558SAl Viro 91bb898558SAl Viro #define EC_FIRMWARE_REV 0x08 92260586d2SDaniel Drake #define EC_WLAN_ENTER_RESET 0x35 93260586d2SDaniel Drake #define EC_WLAN_LEAVE_RESET 0x25 94bb898558SAl Viro 95bb898558SAl Viro /* SCI source values */ 96bb898558SAl Viro 97bb898558SAl Viro #define EC_SCI_SRC_EMPTY 0x00 98bb898558SAl Viro #define EC_SCI_SRC_GAME 0x01 99bb898558SAl Viro #define EC_SCI_SRC_BATTERY 0x02 100bb898558SAl Viro #define EC_SCI_SRC_BATSOC 0x04 101bb898558SAl Viro #define EC_SCI_SRC_BATERR 0x08 102bb898558SAl Viro #define EC_SCI_SRC_EBOOK 0x10 103bb898558SAl Viro #define EC_SCI_SRC_WLAN 0x20 104bb898558SAl Viro #define EC_SCI_SRC_ACPWR 0x40 105bb898558SAl Viro #define EC_SCI_SRC_ALL 0x7F 106bb898558SAl Viro 107bb898558SAl Viro /* GPIO assignments */ 108bb898558SAl Viro 1093c554946SAndres Salomon #define OLPC_GPIO_MIC_AC 1 1107637c925SAndres Salomon #define OLPC_GPIO_DCON_STAT0 5 1117637c925SAndres Salomon #define OLPC_GPIO_DCON_STAT1 6 1127637c925SAndres Salomon #define OLPC_GPIO_DCON_IRQ 7 113bb898558SAl Viro #define OLPC_GPIO_THRM_ALRM geode_gpio(10) 1147637c925SAndres Salomon #define OLPC_GPIO_DCON_LOAD 11 1157637c925SAndres Salomon #define OLPC_GPIO_DCON_BLANK 12 1167637c925SAndres Salomon #define OLPC_GPIO_SMB_CLK 14 1177637c925SAndres Salomon #define OLPC_GPIO_SMB_DATA 15 118bb898558SAl Viro #define OLPC_GPIO_WORKAUX geode_gpio(24) 119bb898558SAl Viro #define OLPC_GPIO_LID geode_gpio(26) 120bb898558SAl Viro #define OLPC_GPIO_ECSCI geode_gpio(27) 121bb898558SAl Viro 1221965aae3SH. Peter Anvin #endif /* _ASM_X86_OLPC_H */ 123