1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef _ASM_X86_NOSPEC_BRANCH_H_ 4 #define _ASM_X86_NOSPEC_BRANCH_H_ 5 6 #include <linux/static_key.h> 7 #include <linux/objtool.h> 8 #include <linux/linkage.h> 9 10 #include <asm/alternative.h> 11 #include <asm/cpufeatures.h> 12 #include <asm/msr-index.h> 13 #include <asm/unwind_hints.h> 14 #include <asm/percpu.h> 15 #include <asm/current.h> 16 17 /* 18 * Call depth tracking for Intel SKL CPUs to address the RSB underflow 19 * issue in software. 20 * 21 * The tracking does not use a counter. It uses uses arithmetic shift 22 * right on call entry and logical shift left on return. 23 * 24 * The depth tracking variable is initialized to 0x8000.... when the call 25 * depth is zero. The arithmetic shift right sign extends the MSB and 26 * saturates after the 12th call. The shift count is 5 for both directions 27 * so the tracking covers 12 nested calls. 28 * 29 * Call 30 * 0: 0x8000000000000000 0x0000000000000000 31 * 1: 0xfc00000000000000 0xf000000000000000 32 * ... 33 * 11: 0xfffffffffffffff8 0xfffffffffffffc00 34 * 12: 0xffffffffffffffff 0xffffffffffffffe0 35 * 36 * After a return buffer fill the depth is credited 12 calls before the 37 * next stuffing has to take place. 38 * 39 * There is a inaccuracy for situations like this: 40 * 41 * 10 calls 42 * 5 returns 43 * 3 calls 44 * 4 returns 45 * 3 calls 46 * .... 47 * 48 * The shift count might cause this to be off by one in either direction, 49 * but there is still a cushion vs. the RSB depth. The algorithm does not 50 * claim to be perfect and it can be speculated around by the CPU, but it 51 * is considered that it obfuscates the problem enough to make exploitation 52 * extremly difficult. 53 */ 54 #define RET_DEPTH_SHIFT 5 55 #define RSB_RET_STUFF_LOOPS 16 56 #define RET_DEPTH_INIT 0x8000000000000000ULL 57 #define RET_DEPTH_INIT_FROM_CALL 0xfc00000000000000ULL 58 #define RET_DEPTH_CREDIT 0xffffffffffffffffULL 59 60 #ifdef CONFIG_CALL_THUNKS_DEBUG 61 # define CALL_THUNKS_DEBUG_INC_CALLS \ 62 incq %gs:__x86_call_count; 63 # define CALL_THUNKS_DEBUG_INC_RETS \ 64 incq %gs:__x86_ret_count; 65 # define CALL_THUNKS_DEBUG_INC_STUFFS \ 66 incq %gs:__x86_stuffs_count; 67 # define CALL_THUNKS_DEBUG_INC_CTXSW \ 68 incq %gs:__x86_ctxsw_count; 69 #else 70 # define CALL_THUNKS_DEBUG_INC_CALLS 71 # define CALL_THUNKS_DEBUG_INC_RETS 72 # define CALL_THUNKS_DEBUG_INC_STUFFS 73 # define CALL_THUNKS_DEBUG_INC_CTXSW 74 #endif 75 76 #if defined(CONFIG_CALL_DEPTH_TRACKING) && !defined(COMPILE_OFFSETS) 77 78 #include <asm/asm-offsets.h> 79 80 #define CREDIT_CALL_DEPTH \ 81 movq $-1, PER_CPU_VAR(pcpu_hot + X86_call_depth); 82 83 #define ASM_CREDIT_CALL_DEPTH \ 84 movq $-1, PER_CPU_VAR(pcpu_hot + X86_call_depth); 85 86 #define RESET_CALL_DEPTH \ 87 xor %eax, %eax; \ 88 bts $63, %rax; \ 89 movq %rax, PER_CPU_VAR(pcpu_hot + X86_call_depth); 90 91 #define RESET_CALL_DEPTH_FROM_CALL \ 92 movb $0xfc, %al; \ 93 shl $56, %rax; \ 94 movq %rax, PER_CPU_VAR(pcpu_hot + X86_call_depth); \ 95 CALL_THUNKS_DEBUG_INC_CALLS 96 97 #define INCREMENT_CALL_DEPTH \ 98 sarq $5, %gs:pcpu_hot + X86_call_depth; \ 99 CALL_THUNKS_DEBUG_INC_CALLS 100 101 #define ASM_INCREMENT_CALL_DEPTH \ 102 sarq $5, PER_CPU_VAR(pcpu_hot + X86_call_depth); \ 103 CALL_THUNKS_DEBUG_INC_CALLS 104 105 #else 106 #define CREDIT_CALL_DEPTH 107 #define ASM_CREDIT_CALL_DEPTH 108 #define RESET_CALL_DEPTH 109 #define INCREMENT_CALL_DEPTH 110 #define ASM_INCREMENT_CALL_DEPTH 111 #define RESET_CALL_DEPTH_FROM_CALL 112 #endif 113 114 /* 115 * Fill the CPU return stack buffer. 116 * 117 * Each entry in the RSB, if used for a speculative 'ret', contains an 118 * infinite 'pause; lfence; jmp' loop to capture speculative execution. 119 * 120 * This is required in various cases for retpoline and IBRS-based 121 * mitigations for the Spectre variant 2 vulnerability. Sometimes to 122 * eliminate potentially bogus entries from the RSB, and sometimes 123 * purely to ensure that it doesn't get empty, which on some CPUs would 124 * allow predictions from other (unwanted!) sources to be used. 125 * 126 * We define a CPP macro such that it can be used from both .S files and 127 * inline assembly. It's possible to do a .macro and then include that 128 * from C via asm(".include <asm/nospec-branch.h>") but let's not go there. 129 */ 130 131 #define RETPOLINE_THUNK_SIZE 32 132 #define RSB_CLEAR_LOOPS 32 /* To forcibly overwrite all entries */ 133 134 /* 135 * Common helper for __FILL_RETURN_BUFFER and __FILL_ONE_RETURN. 136 */ 137 #define __FILL_RETURN_SLOT \ 138 ANNOTATE_INTRA_FUNCTION_CALL; \ 139 call 772f; \ 140 int3; \ 141 772: 142 143 /* 144 * Stuff the entire RSB. 145 * 146 * Google experimented with loop-unrolling and this turned out to be 147 * the optimal version - two calls, each with their own speculation 148 * trap should their return address end up getting used, in a loop. 149 */ 150 #ifdef CONFIG_X86_64 151 #define __FILL_RETURN_BUFFER(reg, nr) \ 152 mov $(nr/2), reg; \ 153 771: \ 154 __FILL_RETURN_SLOT \ 155 __FILL_RETURN_SLOT \ 156 add $(BITS_PER_LONG/8) * 2, %_ASM_SP; \ 157 dec reg; \ 158 jnz 771b; \ 159 /* barrier for jnz misprediction */ \ 160 lfence; \ 161 ASM_CREDIT_CALL_DEPTH \ 162 CALL_THUNKS_DEBUG_INC_CTXSW 163 #else 164 /* 165 * i386 doesn't unconditionally have LFENCE, as such it can't 166 * do a loop. 167 */ 168 #define __FILL_RETURN_BUFFER(reg, nr) \ 169 .rept nr; \ 170 __FILL_RETURN_SLOT; \ 171 .endr; \ 172 add $(BITS_PER_LONG/8) * nr, %_ASM_SP; 173 #endif 174 175 /* 176 * Stuff a single RSB slot. 177 * 178 * To mitigate Post-Barrier RSB speculation, one CALL instruction must be 179 * forced to retire before letting a RET instruction execute. 180 * 181 * On PBRSB-vulnerable CPUs, it is not safe for a RET to be executed 182 * before this point. 183 */ 184 #define __FILL_ONE_RETURN \ 185 __FILL_RETURN_SLOT \ 186 add $(BITS_PER_LONG/8), %_ASM_SP; \ 187 lfence; 188 189 #ifdef __ASSEMBLY__ 190 191 /* 192 * This should be used immediately before an indirect jump/call. It tells 193 * objtool the subsequent indirect jump/call is vouched safe for retpoline 194 * builds. 195 */ 196 .macro ANNOTATE_RETPOLINE_SAFE 197 .Lhere_\@: 198 .pushsection .discard.retpoline_safe 199 .long .Lhere_\@ 200 .popsection 201 .endm 202 203 /* 204 * (ab)use RETPOLINE_SAFE on RET to annotate away 'bare' RET instructions 205 * vs RETBleed validation. 206 */ 207 #define ANNOTATE_UNRET_SAFE ANNOTATE_RETPOLINE_SAFE 208 209 /* 210 * Abuse ANNOTATE_RETPOLINE_SAFE on a NOP to indicate UNRET_END, should 211 * eventually turn into it's own annotation. 212 */ 213 .macro VALIDATE_UNRET_END 214 #if defined(CONFIG_NOINSTR_VALIDATION) && \ 215 (defined(CONFIG_CPU_UNRET_ENTRY) || defined(CONFIG_CPU_SRSO)) 216 ANNOTATE_RETPOLINE_SAFE 217 nop 218 #endif 219 .endm 220 221 /* 222 * Equivalent to -mindirect-branch-cs-prefix; emit the 5 byte jmp/call 223 * to the retpoline thunk with a CS prefix when the register requires 224 * a RAX prefix byte to encode. Also see apply_retpolines(). 225 */ 226 .macro __CS_PREFIX reg:req 227 .irp rs,r8,r9,r10,r11,r12,r13,r14,r15 228 .ifc \reg,\rs 229 .byte 0x2e 230 .endif 231 .endr 232 .endm 233 234 /* 235 * JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple 236 * indirect jmp/call which may be susceptible to the Spectre variant 2 237 * attack. 238 * 239 * NOTE: these do not take kCFI into account and are thus not comparable to C 240 * indirect calls, take care when using. The target of these should be an ENDBR 241 * instruction irrespective of kCFI. 242 */ 243 .macro JMP_NOSPEC reg:req 244 #ifdef CONFIG_RETPOLINE 245 __CS_PREFIX \reg 246 jmp __x86_indirect_thunk_\reg 247 #else 248 jmp *%\reg 249 int3 250 #endif 251 .endm 252 253 .macro CALL_NOSPEC reg:req 254 #ifdef CONFIG_RETPOLINE 255 __CS_PREFIX \reg 256 call __x86_indirect_thunk_\reg 257 #else 258 call *%\reg 259 #endif 260 .endm 261 262 /* 263 * A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP 264 * monstrosity above, manually. 265 */ 266 .macro FILL_RETURN_BUFFER reg:req nr:req ftr:req ftr2=ALT_NOT(X86_FEATURE_ALWAYS) 267 ALTERNATIVE_2 "jmp .Lskip_rsb_\@", \ 268 __stringify(__FILL_RETURN_BUFFER(\reg,\nr)), \ftr, \ 269 __stringify(nop;nop;__FILL_ONE_RETURN), \ftr2 270 271 .Lskip_rsb_\@: 272 .endm 273 274 /* 275 * The CALL to srso_alias_untrain_ret() must be patched in directly at 276 * the spot where untraining must be done, ie., srso_alias_untrain_ret() 277 * must be the target of a CALL instruction instead of indirectly 278 * jumping to a wrapper which then calls it. Therefore, this macro is 279 * called outside of __UNTRAIN_RET below, for the time being, before the 280 * kernel can support nested alternatives with arbitrary nesting. 281 */ 282 .macro CALL_UNTRAIN_RET 283 #if defined(CONFIG_CPU_UNRET_ENTRY) || defined(CONFIG_CPU_SRSO) 284 ALTERNATIVE_2 "", "call entry_untrain_ret", X86_FEATURE_UNRET, \ 285 "call srso_alias_untrain_ret", X86_FEATURE_SRSO_ALIAS 286 #endif 287 .endm 288 289 /* 290 * Mitigate RETBleed for AMD/Hygon Zen uarch. Requires KERNEL CR3 because the 291 * return thunk isn't mapped into the userspace tables (then again, AMD 292 * typically has NO_MELTDOWN). 293 * 294 * While retbleed_untrain_ret() doesn't clobber anything but requires stack, 295 * entry_ibpb() will clobber AX, CX, DX. 296 * 297 * As such, this must be placed after every *SWITCH_TO_KERNEL_CR3 at a point 298 * where we have a stack but before any RET instruction. 299 */ 300 .macro __UNTRAIN_RET ibpb_feature, call_depth_insns 301 #if defined(CONFIG_RETHUNK) || defined(CONFIG_CPU_IBPB_ENTRY) 302 VALIDATE_UNRET_END 303 CALL_UNTRAIN_RET 304 ALTERNATIVE_2 "", \ 305 "call entry_ibpb", \ibpb_feature, \ 306 __stringify(\call_depth_insns), X86_FEATURE_CALL_DEPTH 307 #endif 308 .endm 309 310 #define UNTRAIN_RET \ 311 __UNTRAIN_RET X86_FEATURE_ENTRY_IBPB, __stringify(RESET_CALL_DEPTH) 312 313 #define UNTRAIN_RET_VM \ 314 __UNTRAIN_RET X86_FEATURE_IBPB_ON_VMEXIT, __stringify(RESET_CALL_DEPTH) 315 316 #define UNTRAIN_RET_FROM_CALL \ 317 __UNTRAIN_RET X86_FEATURE_ENTRY_IBPB, __stringify(RESET_CALL_DEPTH_FROM_CALL) 318 319 320 .macro CALL_DEPTH_ACCOUNT 321 #ifdef CONFIG_CALL_DEPTH_TRACKING 322 ALTERNATIVE "", \ 323 __stringify(ASM_INCREMENT_CALL_DEPTH), X86_FEATURE_CALL_DEPTH 324 #endif 325 .endm 326 327 /* 328 * Macro to execute VERW instruction that mitigate transient data sampling 329 * attacks such as MDS. On affected systems a microcode update overloaded VERW 330 * instruction to also clear the CPU buffers. VERW clobbers CFLAGS.ZF. 331 * 332 * Note: Only the memory operand variant of VERW clears the CPU buffers. 333 */ 334 .macro CLEAR_CPU_BUFFERS 335 #ifdef CONFIG_X86_64 336 ALTERNATIVE "", "verw mds_verw_sel(%rip)", X86_FEATURE_CLEAR_CPU_BUF 337 #else 338 /* 339 * In 32bit mode, the memory operand must be a %cs reference. The data 340 * segments may not be usable (vm86 mode), and the stack segment may not 341 * be flat (ESPFIX32). 342 */ 343 ALTERNATIVE "", "verw %cs:mds_verw_sel", X86_FEATURE_CLEAR_CPU_BUF 344 #endif 345 .endm 346 347 #ifdef CONFIG_X86_64 348 .macro CLEAR_BRANCH_HISTORY 349 ALTERNATIVE "", "call clear_bhb_loop", X86_FEATURE_CLEAR_BHB_LOOP 350 .endm 351 352 .macro CLEAR_BRANCH_HISTORY_VMEXIT 353 ALTERNATIVE "", "call clear_bhb_loop", X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT 354 .endm 355 #else 356 #define CLEAR_BRANCH_HISTORY 357 #define CLEAR_BRANCH_HISTORY_VMEXIT 358 #endif 359 360 #else /* __ASSEMBLY__ */ 361 362 #define ANNOTATE_RETPOLINE_SAFE \ 363 "999:\n\t" \ 364 ".pushsection .discard.retpoline_safe\n\t" \ 365 ".long 999b\n\t" \ 366 ".popsection\n\t" 367 368 typedef u8 retpoline_thunk_t[RETPOLINE_THUNK_SIZE]; 369 extern retpoline_thunk_t __x86_indirect_thunk_array[]; 370 extern retpoline_thunk_t __x86_indirect_call_thunk_array[]; 371 extern retpoline_thunk_t __x86_indirect_jump_thunk_array[]; 372 373 #ifdef CONFIG_RETHUNK 374 extern void __x86_return_thunk(void); 375 #else 376 static inline void __x86_return_thunk(void) {} 377 #endif 378 379 #ifdef CONFIG_CPU_UNRET_ENTRY 380 extern void retbleed_return_thunk(void); 381 #else 382 static inline void retbleed_return_thunk(void) {} 383 #endif 384 385 extern void srso_alias_untrain_ret(void); 386 387 #ifdef CONFIG_CPU_SRSO 388 extern void srso_return_thunk(void); 389 extern void srso_alias_return_thunk(void); 390 #else 391 static inline void srso_return_thunk(void) {} 392 static inline void srso_alias_return_thunk(void) {} 393 #endif 394 395 extern void retbleed_return_thunk(void); 396 extern void srso_return_thunk(void); 397 extern void srso_alias_return_thunk(void); 398 399 extern void retbleed_untrain_ret(void); 400 extern void srso_untrain_ret(void); 401 extern void srso_alias_untrain_ret(void); 402 403 extern void entry_untrain_ret(void); 404 extern void entry_ibpb(void); 405 406 #ifdef CONFIG_X86_64 407 extern void clear_bhb_loop(void); 408 #endif 409 410 extern void (*x86_return_thunk)(void); 411 412 #ifdef CONFIG_CALL_DEPTH_TRACKING 413 extern void __x86_return_skl(void); 414 415 static inline void x86_set_skl_return_thunk(void) 416 { 417 x86_return_thunk = &__x86_return_skl; 418 } 419 420 #define CALL_DEPTH_ACCOUNT \ 421 ALTERNATIVE("", \ 422 __stringify(INCREMENT_CALL_DEPTH), \ 423 X86_FEATURE_CALL_DEPTH) 424 425 #ifdef CONFIG_CALL_THUNKS_DEBUG 426 DECLARE_PER_CPU(u64, __x86_call_count); 427 DECLARE_PER_CPU(u64, __x86_ret_count); 428 DECLARE_PER_CPU(u64, __x86_stuffs_count); 429 DECLARE_PER_CPU(u64, __x86_ctxsw_count); 430 #endif 431 #else 432 static inline void x86_set_skl_return_thunk(void) {} 433 434 #define CALL_DEPTH_ACCOUNT "" 435 436 #endif 437 438 #ifdef CONFIG_RETPOLINE 439 440 #define GEN(reg) \ 441 extern retpoline_thunk_t __x86_indirect_thunk_ ## reg; 442 #include <asm/GEN-for-each-reg.h> 443 #undef GEN 444 445 #define GEN(reg) \ 446 extern retpoline_thunk_t __x86_indirect_call_thunk_ ## reg; 447 #include <asm/GEN-for-each-reg.h> 448 #undef GEN 449 450 #define GEN(reg) \ 451 extern retpoline_thunk_t __x86_indirect_jump_thunk_ ## reg; 452 #include <asm/GEN-for-each-reg.h> 453 #undef GEN 454 455 #ifdef CONFIG_X86_64 456 457 /* 458 * Inline asm uses the %V modifier which is only in newer GCC 459 * which is ensured when CONFIG_RETPOLINE is defined. 460 */ 461 # define CALL_NOSPEC \ 462 ALTERNATIVE_2( \ 463 ANNOTATE_RETPOLINE_SAFE \ 464 "call *%[thunk_target]\n", \ 465 "call __x86_indirect_thunk_%V[thunk_target]\n", \ 466 X86_FEATURE_RETPOLINE, \ 467 "lfence;\n" \ 468 ANNOTATE_RETPOLINE_SAFE \ 469 "call *%[thunk_target]\n", \ 470 X86_FEATURE_RETPOLINE_LFENCE) 471 472 # define THUNK_TARGET(addr) [thunk_target] "r" (addr) 473 474 #else /* CONFIG_X86_32 */ 475 /* 476 * For i386 we use the original ret-equivalent retpoline, because 477 * otherwise we'll run out of registers. We don't care about CET 478 * here, anyway. 479 */ 480 # define CALL_NOSPEC \ 481 ALTERNATIVE_2( \ 482 ANNOTATE_RETPOLINE_SAFE \ 483 "call *%[thunk_target]\n", \ 484 " jmp 904f;\n" \ 485 " .align 16\n" \ 486 "901: call 903f;\n" \ 487 "902: pause;\n" \ 488 " lfence;\n" \ 489 " jmp 902b;\n" \ 490 " .align 16\n" \ 491 "903: lea 4(%%esp), %%esp;\n" \ 492 " pushl %[thunk_target];\n" \ 493 " ret;\n" \ 494 " .align 16\n" \ 495 "904: call 901b;\n", \ 496 X86_FEATURE_RETPOLINE, \ 497 "lfence;\n" \ 498 ANNOTATE_RETPOLINE_SAFE \ 499 "call *%[thunk_target]\n", \ 500 X86_FEATURE_RETPOLINE_LFENCE) 501 502 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr) 503 #endif 504 #else /* No retpoline for C / inline asm */ 505 # define CALL_NOSPEC "call *%[thunk_target]\n" 506 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr) 507 #endif 508 509 /* The Spectre V2 mitigation variants */ 510 enum spectre_v2_mitigation { 511 SPECTRE_V2_NONE, 512 SPECTRE_V2_RETPOLINE, 513 SPECTRE_V2_LFENCE, 514 SPECTRE_V2_EIBRS, 515 SPECTRE_V2_EIBRS_RETPOLINE, 516 SPECTRE_V2_EIBRS_LFENCE, 517 SPECTRE_V2_IBRS, 518 }; 519 520 /* The indirect branch speculation control variants */ 521 enum spectre_v2_user_mitigation { 522 SPECTRE_V2_USER_NONE, 523 SPECTRE_V2_USER_STRICT, 524 SPECTRE_V2_USER_STRICT_PREFERRED, 525 SPECTRE_V2_USER_PRCTL, 526 SPECTRE_V2_USER_SECCOMP, 527 }; 528 529 /* The Speculative Store Bypass disable variants */ 530 enum ssb_mitigation { 531 SPEC_STORE_BYPASS_NONE, 532 SPEC_STORE_BYPASS_DISABLE, 533 SPEC_STORE_BYPASS_PRCTL, 534 SPEC_STORE_BYPASS_SECCOMP, 535 }; 536 537 static __always_inline 538 void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature) 539 { 540 asm volatile(ALTERNATIVE("", "wrmsr", %c[feature]) 541 : : "c" (msr), 542 "a" ((u32)val), 543 "d" ((u32)(val >> 32)), 544 [feature] "i" (feature) 545 : "memory"); 546 } 547 548 extern u64 x86_pred_cmd; 549 550 static inline void indirect_branch_prediction_barrier(void) 551 { 552 alternative_msr_write(MSR_IA32_PRED_CMD, x86_pred_cmd, X86_FEATURE_USE_IBPB); 553 } 554 555 /* The Intel SPEC CTRL MSR base value cache */ 556 extern u64 x86_spec_ctrl_base; 557 DECLARE_PER_CPU(u64, x86_spec_ctrl_current); 558 extern void update_spec_ctrl_cond(u64 val); 559 extern u64 spec_ctrl_current(void); 560 561 /* 562 * With retpoline, we must use IBRS to restrict branch prediction 563 * before calling into firmware. 564 * 565 * (Implemented as CPP macros due to header hell.) 566 */ 567 #define firmware_restrict_branch_speculation_start() \ 568 do { \ 569 preempt_disable(); \ 570 alternative_msr_write(MSR_IA32_SPEC_CTRL, \ 571 spec_ctrl_current() | SPEC_CTRL_IBRS, \ 572 X86_FEATURE_USE_IBRS_FW); \ 573 alternative_msr_write(MSR_IA32_PRED_CMD, PRED_CMD_IBPB, \ 574 X86_FEATURE_USE_IBPB_FW); \ 575 } while (0) 576 577 #define firmware_restrict_branch_speculation_end() \ 578 do { \ 579 alternative_msr_write(MSR_IA32_SPEC_CTRL, \ 580 spec_ctrl_current(), \ 581 X86_FEATURE_USE_IBRS_FW); \ 582 preempt_enable(); \ 583 } while (0) 584 585 DECLARE_STATIC_KEY_FALSE(switch_to_cond_stibp); 586 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_ibpb); 587 DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb); 588 589 DECLARE_STATIC_KEY_FALSE(mds_idle_clear); 590 591 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush); 592 593 DECLARE_STATIC_KEY_FALSE(mmio_stale_data_clear); 594 595 extern u16 mds_verw_sel; 596 597 #include <asm/segment.h> 598 599 /** 600 * mds_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability 601 * 602 * This uses the otherwise unused and obsolete VERW instruction in 603 * combination with microcode which triggers a CPU buffer flush when the 604 * instruction is executed. 605 */ 606 static __always_inline void mds_clear_cpu_buffers(void) 607 { 608 static const u16 ds = __KERNEL_DS; 609 610 /* 611 * Has to be the memory-operand variant because only that 612 * guarantees the CPU buffer flush functionality according to 613 * documentation. The register-operand variant does not. 614 * Works with any segment selector, but a valid writable 615 * data segment is the fastest variant. 616 * 617 * "cc" clobber is required because VERW modifies ZF. 618 */ 619 asm volatile("verw %[ds]" : : [ds] "m" (ds) : "cc"); 620 } 621 622 /** 623 * mds_idle_clear_cpu_buffers - Mitigation for MDS vulnerability 624 * 625 * Clear CPU buffers if the corresponding static key is enabled 626 */ 627 static __always_inline void mds_idle_clear_cpu_buffers(void) 628 { 629 if (static_branch_likely(&mds_idle_clear)) 630 mds_clear_cpu_buffers(); 631 } 632 633 #endif /* __ASSEMBLY__ */ 634 635 #endif /* _ASM_X86_NOSPEC_BRANCH_H_ */ 636