1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef _ASM_X86_NOSPEC_BRANCH_H_ 4 #define _ASM_X86_NOSPEC_BRANCH_H_ 5 6 #include <linux/static_key.h> 7 #include <linux/objtool.h> 8 #include <linux/linkage.h> 9 10 #include <asm/alternative.h> 11 #include <asm/cpufeatures.h> 12 #include <asm/msr-index.h> 13 #include <asm/unwind_hints.h> 14 #include <asm/percpu.h> 15 #include <asm/current.h> 16 17 /* 18 * Call depth tracking for Intel SKL CPUs to address the RSB underflow 19 * issue in software. 20 * 21 * The tracking does not use a counter. It uses uses arithmetic shift 22 * right on call entry and logical shift left on return. 23 * 24 * The depth tracking variable is initialized to 0x8000.... when the call 25 * depth is zero. The arithmetic shift right sign extends the MSB and 26 * saturates after the 12th call. The shift count is 5 for both directions 27 * so the tracking covers 12 nested calls. 28 * 29 * Call 30 * 0: 0x8000000000000000 0x0000000000000000 31 * 1: 0xfc00000000000000 0xf000000000000000 32 * ... 33 * 11: 0xfffffffffffffff8 0xfffffffffffffc00 34 * 12: 0xffffffffffffffff 0xffffffffffffffe0 35 * 36 * After a return buffer fill the depth is credited 12 calls before the 37 * next stuffing has to take place. 38 * 39 * There is a inaccuracy for situations like this: 40 * 41 * 10 calls 42 * 5 returns 43 * 3 calls 44 * 4 returns 45 * 3 calls 46 * .... 47 * 48 * The shift count might cause this to be off by one in either direction, 49 * but there is still a cushion vs. the RSB depth. The algorithm does not 50 * claim to be perfect and it can be speculated around by the CPU, but it 51 * is considered that it obfuscates the problem enough to make exploitation 52 * extremly difficult. 53 */ 54 #define RET_DEPTH_SHIFT 5 55 #define RSB_RET_STUFF_LOOPS 16 56 #define RET_DEPTH_INIT 0x8000000000000000ULL 57 #define RET_DEPTH_INIT_FROM_CALL 0xfc00000000000000ULL 58 #define RET_DEPTH_CREDIT 0xffffffffffffffffULL 59 60 #ifdef CONFIG_CALL_THUNKS_DEBUG 61 # define CALL_THUNKS_DEBUG_INC_CALLS \ 62 incq %gs:__x86_call_count; 63 # define CALL_THUNKS_DEBUG_INC_RETS \ 64 incq %gs:__x86_ret_count; 65 # define CALL_THUNKS_DEBUG_INC_STUFFS \ 66 incq %gs:__x86_stuffs_count; 67 # define CALL_THUNKS_DEBUG_INC_CTXSW \ 68 incq %gs:__x86_ctxsw_count; 69 #else 70 # define CALL_THUNKS_DEBUG_INC_CALLS 71 # define CALL_THUNKS_DEBUG_INC_RETS 72 # define CALL_THUNKS_DEBUG_INC_STUFFS 73 # define CALL_THUNKS_DEBUG_INC_CTXSW 74 #endif 75 76 #if defined(CONFIG_CALL_DEPTH_TRACKING) && !defined(COMPILE_OFFSETS) 77 78 #include <asm/asm-offsets.h> 79 80 #define CREDIT_CALL_DEPTH \ 81 movq $-1, PER_CPU_VAR(pcpu_hot + X86_call_depth); 82 83 #define ASM_CREDIT_CALL_DEPTH \ 84 movq $-1, PER_CPU_VAR(pcpu_hot + X86_call_depth); 85 86 #define RESET_CALL_DEPTH \ 87 xor %eax, %eax; \ 88 bts $63, %rax; \ 89 movq %rax, PER_CPU_VAR(pcpu_hot + X86_call_depth); 90 91 #define RESET_CALL_DEPTH_FROM_CALL \ 92 movb $0xfc, %al; \ 93 shl $56, %rax; \ 94 movq %rax, PER_CPU_VAR(pcpu_hot + X86_call_depth); \ 95 CALL_THUNKS_DEBUG_INC_CALLS 96 97 #define INCREMENT_CALL_DEPTH \ 98 sarq $5, %gs:pcpu_hot + X86_call_depth; \ 99 CALL_THUNKS_DEBUG_INC_CALLS 100 101 #define ASM_INCREMENT_CALL_DEPTH \ 102 sarq $5, PER_CPU_VAR(pcpu_hot + X86_call_depth); \ 103 CALL_THUNKS_DEBUG_INC_CALLS 104 105 #else 106 #define CREDIT_CALL_DEPTH 107 #define ASM_CREDIT_CALL_DEPTH 108 #define RESET_CALL_DEPTH 109 #define INCREMENT_CALL_DEPTH 110 #define ASM_INCREMENT_CALL_DEPTH 111 #define RESET_CALL_DEPTH_FROM_CALL 112 #endif 113 114 /* 115 * Fill the CPU return stack buffer. 116 * 117 * Each entry in the RSB, if used for a speculative 'ret', contains an 118 * infinite 'pause; lfence; jmp' loop to capture speculative execution. 119 * 120 * This is required in various cases for retpoline and IBRS-based 121 * mitigations for the Spectre variant 2 vulnerability. Sometimes to 122 * eliminate potentially bogus entries from the RSB, and sometimes 123 * purely to ensure that it doesn't get empty, which on some CPUs would 124 * allow predictions from other (unwanted!) sources to be used. 125 * 126 * We define a CPP macro such that it can be used from both .S files and 127 * inline assembly. It's possible to do a .macro and then include that 128 * from C via asm(".include <asm/nospec-branch.h>") but let's not go there. 129 */ 130 131 #define RETPOLINE_THUNK_SIZE 32 132 #define RSB_CLEAR_LOOPS 32 /* To forcibly overwrite all entries */ 133 134 /* 135 * Common helper for __FILL_RETURN_BUFFER and __FILL_ONE_RETURN. 136 */ 137 #define __FILL_RETURN_SLOT \ 138 ANNOTATE_INTRA_FUNCTION_CALL; \ 139 call 772f; \ 140 int3; \ 141 772: 142 143 /* 144 * Stuff the entire RSB. 145 * 146 * Google experimented with loop-unrolling and this turned out to be 147 * the optimal version - two calls, each with their own speculation 148 * trap should their return address end up getting used, in a loop. 149 */ 150 #ifdef CONFIG_X86_64 151 #define __FILL_RETURN_BUFFER(reg, nr) \ 152 mov $(nr/2), reg; \ 153 771: \ 154 __FILL_RETURN_SLOT \ 155 __FILL_RETURN_SLOT \ 156 add $(BITS_PER_LONG/8) * 2, %_ASM_SP; \ 157 dec reg; \ 158 jnz 771b; \ 159 /* barrier for jnz misprediction */ \ 160 lfence; \ 161 ASM_CREDIT_CALL_DEPTH \ 162 CALL_THUNKS_DEBUG_INC_CTXSW 163 #else 164 /* 165 * i386 doesn't unconditionally have LFENCE, as such it can't 166 * do a loop. 167 */ 168 #define __FILL_RETURN_BUFFER(reg, nr) \ 169 .rept nr; \ 170 __FILL_RETURN_SLOT; \ 171 .endr; \ 172 add $(BITS_PER_LONG/8) * nr, %_ASM_SP; 173 #endif 174 175 /* 176 * Stuff a single RSB slot. 177 * 178 * To mitigate Post-Barrier RSB speculation, one CALL instruction must be 179 * forced to retire before letting a RET instruction execute. 180 * 181 * On PBRSB-vulnerable CPUs, it is not safe for a RET to be executed 182 * before this point. 183 */ 184 #define __FILL_ONE_RETURN \ 185 __FILL_RETURN_SLOT \ 186 add $(BITS_PER_LONG/8), %_ASM_SP; \ 187 lfence; 188 189 #ifdef __ASSEMBLY__ 190 191 /* 192 * This should be used immediately before an indirect jump/call. It tells 193 * objtool the subsequent indirect jump/call is vouched safe for retpoline 194 * builds. 195 */ 196 .macro ANNOTATE_RETPOLINE_SAFE 197 .Lhere_\@: 198 .pushsection .discard.retpoline_safe 199 .long .Lhere_\@ 200 .popsection 201 .endm 202 203 /* 204 * (ab)use RETPOLINE_SAFE on RET to annotate away 'bare' RET instructions 205 * vs RETBleed validation. 206 */ 207 #define ANNOTATE_UNRET_SAFE ANNOTATE_RETPOLINE_SAFE 208 209 /* 210 * Abuse ANNOTATE_RETPOLINE_SAFE on a NOP to indicate UNRET_END, should 211 * eventually turn into it's own annotation. 212 */ 213 .macro VALIDATE_UNRET_END 214 #if defined(CONFIG_NOINSTR_VALIDATION) && \ 215 (defined(CONFIG_CPU_UNRET_ENTRY) || defined(CONFIG_CPU_SRSO)) 216 ANNOTATE_RETPOLINE_SAFE 217 nop 218 #endif 219 .endm 220 221 /* 222 * Equivalent to -mindirect-branch-cs-prefix; emit the 5 byte jmp/call 223 * to the retpoline thunk with a CS prefix when the register requires 224 * a RAX prefix byte to encode. Also see apply_retpolines(). 225 */ 226 .macro __CS_PREFIX reg:req 227 .irp rs,r8,r9,r10,r11,r12,r13,r14,r15 228 .ifc \reg,\rs 229 .byte 0x2e 230 .endif 231 .endr 232 .endm 233 234 /* 235 * JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple 236 * indirect jmp/call which may be susceptible to the Spectre variant 2 237 * attack. 238 * 239 * NOTE: these do not take kCFI into account and are thus not comparable to C 240 * indirect calls, take care when using. The target of these should be an ENDBR 241 * instruction irrespective of kCFI. 242 */ 243 .macro JMP_NOSPEC reg:req 244 #ifdef CONFIG_RETPOLINE 245 __CS_PREFIX \reg 246 jmp __x86_indirect_thunk_\reg 247 #else 248 jmp *%\reg 249 int3 250 #endif 251 .endm 252 253 .macro CALL_NOSPEC reg:req 254 #ifdef CONFIG_RETPOLINE 255 __CS_PREFIX \reg 256 call __x86_indirect_thunk_\reg 257 #else 258 call *%\reg 259 #endif 260 .endm 261 262 /* 263 * A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP 264 * monstrosity above, manually. 265 */ 266 .macro FILL_RETURN_BUFFER reg:req nr:req ftr:req ftr2=ALT_NOT(X86_FEATURE_ALWAYS) 267 ALTERNATIVE_2 "jmp .Lskip_rsb_\@", \ 268 __stringify(__FILL_RETURN_BUFFER(\reg,\nr)), \ftr, \ 269 __stringify(nop;nop;__FILL_ONE_RETURN), \ftr2 270 271 .Lskip_rsb_\@: 272 .endm 273 274 /* 275 * The CALL to srso_alias_untrain_ret() must be patched in directly at 276 * the spot where untraining must be done, ie., srso_alias_untrain_ret() 277 * must be the target of a CALL instruction instead of indirectly 278 * jumping to a wrapper which then calls it. Therefore, this macro is 279 * called outside of __UNTRAIN_RET below, for the time being, before the 280 * kernel can support nested alternatives with arbitrary nesting. 281 */ 282 .macro CALL_UNTRAIN_RET 283 #if defined(CONFIG_CPU_UNRET_ENTRY) || defined(CONFIG_CPU_SRSO) 284 ALTERNATIVE_2 "", "call entry_untrain_ret", X86_FEATURE_UNRET, \ 285 "call srso_alias_untrain_ret", X86_FEATURE_SRSO_ALIAS 286 #endif 287 .endm 288 289 /* 290 * Mitigate RETBleed for AMD/Hygon Zen uarch. Requires KERNEL CR3 because the 291 * return thunk isn't mapped into the userspace tables (then again, AMD 292 * typically has NO_MELTDOWN). 293 * 294 * While retbleed_untrain_ret() doesn't clobber anything but requires stack, 295 * entry_ibpb() will clobber AX, CX, DX. 296 * 297 * As such, this must be placed after every *SWITCH_TO_KERNEL_CR3 at a point 298 * where we have a stack but before any RET instruction. 299 */ 300 .macro __UNTRAIN_RET ibpb_feature, call_depth_insns 301 #if defined(CONFIG_RETHUNK) || defined(CONFIG_CPU_IBPB_ENTRY) 302 VALIDATE_UNRET_END 303 CALL_UNTRAIN_RET 304 ALTERNATIVE_2 "", \ 305 "call entry_ibpb", \ibpb_feature, \ 306 __stringify(\call_depth_insns), X86_FEATURE_CALL_DEPTH 307 #endif 308 .endm 309 310 #define UNTRAIN_RET \ 311 __UNTRAIN_RET X86_FEATURE_ENTRY_IBPB, __stringify(RESET_CALL_DEPTH) 312 313 #define UNTRAIN_RET_VM \ 314 __UNTRAIN_RET X86_FEATURE_IBPB_ON_VMEXIT, __stringify(RESET_CALL_DEPTH) 315 316 #define UNTRAIN_RET_FROM_CALL \ 317 __UNTRAIN_RET X86_FEATURE_ENTRY_IBPB, __stringify(RESET_CALL_DEPTH_FROM_CALL) 318 319 320 .macro CALL_DEPTH_ACCOUNT 321 #ifdef CONFIG_CALL_DEPTH_TRACKING 322 ALTERNATIVE "", \ 323 __stringify(ASM_INCREMENT_CALL_DEPTH), X86_FEATURE_CALL_DEPTH 324 #endif 325 .endm 326 327 /* 328 * Macro to execute VERW instruction that mitigate transient data sampling 329 * attacks such as MDS. On affected systems a microcode update overloaded VERW 330 * instruction to also clear the CPU buffers. VERW clobbers CFLAGS.ZF. 331 * 332 * Note: Only the memory operand variant of VERW clears the CPU buffers. 333 */ 334 .macro CLEAR_CPU_BUFFERS 335 ALTERNATIVE "", __stringify(verw _ASM_RIP(mds_verw_sel)), X86_FEATURE_CLEAR_CPU_BUF 336 .endm 337 338 #ifdef CONFIG_X86_64 339 .macro CLEAR_BRANCH_HISTORY 340 ALTERNATIVE "", "call clear_bhb_loop", X86_FEATURE_CLEAR_BHB_LOOP 341 .endm 342 343 .macro CLEAR_BRANCH_HISTORY_VMEXIT 344 ALTERNATIVE "", "call clear_bhb_loop", X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT 345 .endm 346 #else 347 #define CLEAR_BRANCH_HISTORY 348 #define CLEAR_BRANCH_HISTORY_VMEXIT 349 #endif 350 351 #else /* __ASSEMBLY__ */ 352 353 #define ANNOTATE_RETPOLINE_SAFE \ 354 "999:\n\t" \ 355 ".pushsection .discard.retpoline_safe\n\t" \ 356 ".long 999b\n\t" \ 357 ".popsection\n\t" 358 359 typedef u8 retpoline_thunk_t[RETPOLINE_THUNK_SIZE]; 360 extern retpoline_thunk_t __x86_indirect_thunk_array[]; 361 extern retpoline_thunk_t __x86_indirect_call_thunk_array[]; 362 extern retpoline_thunk_t __x86_indirect_jump_thunk_array[]; 363 364 #ifdef CONFIG_RETHUNK 365 extern void __x86_return_thunk(void); 366 #else 367 static inline void __x86_return_thunk(void) {} 368 #endif 369 370 #ifdef CONFIG_CPU_UNRET_ENTRY 371 extern void retbleed_return_thunk(void); 372 #else 373 static inline void retbleed_return_thunk(void) {} 374 #endif 375 376 extern void srso_alias_untrain_ret(void); 377 378 #ifdef CONFIG_CPU_SRSO 379 extern void srso_return_thunk(void); 380 extern void srso_alias_return_thunk(void); 381 #else 382 static inline void srso_return_thunk(void) {} 383 static inline void srso_alias_return_thunk(void) {} 384 #endif 385 386 extern void retbleed_return_thunk(void); 387 extern void srso_return_thunk(void); 388 extern void srso_alias_return_thunk(void); 389 390 extern void retbleed_untrain_ret(void); 391 extern void srso_untrain_ret(void); 392 extern void srso_alias_untrain_ret(void); 393 394 extern void entry_untrain_ret(void); 395 extern void entry_ibpb(void); 396 397 #ifdef CONFIG_X86_64 398 extern void clear_bhb_loop(void); 399 #endif 400 401 extern void (*x86_return_thunk)(void); 402 403 #ifdef CONFIG_CALL_DEPTH_TRACKING 404 extern void __x86_return_skl(void); 405 406 static inline void x86_set_skl_return_thunk(void) 407 { 408 x86_return_thunk = &__x86_return_skl; 409 } 410 411 #define CALL_DEPTH_ACCOUNT \ 412 ALTERNATIVE("", \ 413 __stringify(INCREMENT_CALL_DEPTH), \ 414 X86_FEATURE_CALL_DEPTH) 415 416 #ifdef CONFIG_CALL_THUNKS_DEBUG 417 DECLARE_PER_CPU(u64, __x86_call_count); 418 DECLARE_PER_CPU(u64, __x86_ret_count); 419 DECLARE_PER_CPU(u64, __x86_stuffs_count); 420 DECLARE_PER_CPU(u64, __x86_ctxsw_count); 421 #endif 422 #else 423 static inline void x86_set_skl_return_thunk(void) {} 424 425 #define CALL_DEPTH_ACCOUNT "" 426 427 #endif 428 429 #ifdef CONFIG_RETPOLINE 430 431 #define GEN(reg) \ 432 extern retpoline_thunk_t __x86_indirect_thunk_ ## reg; 433 #include <asm/GEN-for-each-reg.h> 434 #undef GEN 435 436 #define GEN(reg) \ 437 extern retpoline_thunk_t __x86_indirect_call_thunk_ ## reg; 438 #include <asm/GEN-for-each-reg.h> 439 #undef GEN 440 441 #define GEN(reg) \ 442 extern retpoline_thunk_t __x86_indirect_jump_thunk_ ## reg; 443 #include <asm/GEN-for-each-reg.h> 444 #undef GEN 445 446 #ifdef CONFIG_X86_64 447 448 /* 449 * Inline asm uses the %V modifier which is only in newer GCC 450 * which is ensured when CONFIG_RETPOLINE is defined. 451 */ 452 # define CALL_NOSPEC \ 453 ALTERNATIVE_2( \ 454 ANNOTATE_RETPOLINE_SAFE \ 455 "call *%[thunk_target]\n", \ 456 "call __x86_indirect_thunk_%V[thunk_target]\n", \ 457 X86_FEATURE_RETPOLINE, \ 458 "lfence;\n" \ 459 ANNOTATE_RETPOLINE_SAFE \ 460 "call *%[thunk_target]\n", \ 461 X86_FEATURE_RETPOLINE_LFENCE) 462 463 # define THUNK_TARGET(addr) [thunk_target] "r" (addr) 464 465 #else /* CONFIG_X86_32 */ 466 /* 467 * For i386 we use the original ret-equivalent retpoline, because 468 * otherwise we'll run out of registers. We don't care about CET 469 * here, anyway. 470 */ 471 # define CALL_NOSPEC \ 472 ALTERNATIVE_2( \ 473 ANNOTATE_RETPOLINE_SAFE \ 474 "call *%[thunk_target]\n", \ 475 " jmp 904f;\n" \ 476 " .align 16\n" \ 477 "901: call 903f;\n" \ 478 "902: pause;\n" \ 479 " lfence;\n" \ 480 " jmp 902b;\n" \ 481 " .align 16\n" \ 482 "903: lea 4(%%esp), %%esp;\n" \ 483 " pushl %[thunk_target];\n" \ 484 " ret;\n" \ 485 " .align 16\n" \ 486 "904: call 901b;\n", \ 487 X86_FEATURE_RETPOLINE, \ 488 "lfence;\n" \ 489 ANNOTATE_RETPOLINE_SAFE \ 490 "call *%[thunk_target]\n", \ 491 X86_FEATURE_RETPOLINE_LFENCE) 492 493 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr) 494 #endif 495 #else /* No retpoline for C / inline asm */ 496 # define CALL_NOSPEC "call *%[thunk_target]\n" 497 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr) 498 #endif 499 500 /* The Spectre V2 mitigation variants */ 501 enum spectre_v2_mitigation { 502 SPECTRE_V2_NONE, 503 SPECTRE_V2_RETPOLINE, 504 SPECTRE_V2_LFENCE, 505 SPECTRE_V2_EIBRS, 506 SPECTRE_V2_EIBRS_RETPOLINE, 507 SPECTRE_V2_EIBRS_LFENCE, 508 SPECTRE_V2_IBRS, 509 }; 510 511 /* The indirect branch speculation control variants */ 512 enum spectre_v2_user_mitigation { 513 SPECTRE_V2_USER_NONE, 514 SPECTRE_V2_USER_STRICT, 515 SPECTRE_V2_USER_STRICT_PREFERRED, 516 SPECTRE_V2_USER_PRCTL, 517 SPECTRE_V2_USER_SECCOMP, 518 }; 519 520 /* The Speculative Store Bypass disable variants */ 521 enum ssb_mitigation { 522 SPEC_STORE_BYPASS_NONE, 523 SPEC_STORE_BYPASS_DISABLE, 524 SPEC_STORE_BYPASS_PRCTL, 525 SPEC_STORE_BYPASS_SECCOMP, 526 }; 527 528 static __always_inline 529 void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature) 530 { 531 asm volatile(ALTERNATIVE("", "wrmsr", %c[feature]) 532 : : "c" (msr), 533 "a" ((u32)val), 534 "d" ((u32)(val >> 32)), 535 [feature] "i" (feature) 536 : "memory"); 537 } 538 539 extern u64 x86_pred_cmd; 540 541 static inline void indirect_branch_prediction_barrier(void) 542 { 543 alternative_msr_write(MSR_IA32_PRED_CMD, x86_pred_cmd, X86_FEATURE_USE_IBPB); 544 } 545 546 /* The Intel SPEC CTRL MSR base value cache */ 547 extern u64 x86_spec_ctrl_base; 548 DECLARE_PER_CPU(u64, x86_spec_ctrl_current); 549 extern void update_spec_ctrl_cond(u64 val); 550 extern u64 spec_ctrl_current(void); 551 552 /* 553 * With retpoline, we must use IBRS to restrict branch prediction 554 * before calling into firmware. 555 * 556 * (Implemented as CPP macros due to header hell.) 557 */ 558 #define firmware_restrict_branch_speculation_start() \ 559 do { \ 560 preempt_disable(); \ 561 alternative_msr_write(MSR_IA32_SPEC_CTRL, \ 562 spec_ctrl_current() | SPEC_CTRL_IBRS, \ 563 X86_FEATURE_USE_IBRS_FW); \ 564 alternative_msr_write(MSR_IA32_PRED_CMD, PRED_CMD_IBPB, \ 565 X86_FEATURE_USE_IBPB_FW); \ 566 } while (0) 567 568 #define firmware_restrict_branch_speculation_end() \ 569 do { \ 570 alternative_msr_write(MSR_IA32_SPEC_CTRL, \ 571 spec_ctrl_current(), \ 572 X86_FEATURE_USE_IBRS_FW); \ 573 preempt_enable(); \ 574 } while (0) 575 576 DECLARE_STATIC_KEY_FALSE(switch_to_cond_stibp); 577 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_ibpb); 578 DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb); 579 580 DECLARE_STATIC_KEY_FALSE(mds_idle_clear); 581 582 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush); 583 584 DECLARE_STATIC_KEY_FALSE(mmio_stale_data_clear); 585 586 extern u16 mds_verw_sel; 587 588 #include <asm/segment.h> 589 590 /** 591 * mds_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability 592 * 593 * This uses the otherwise unused and obsolete VERW instruction in 594 * combination with microcode which triggers a CPU buffer flush when the 595 * instruction is executed. 596 */ 597 static __always_inline void mds_clear_cpu_buffers(void) 598 { 599 static const u16 ds = __KERNEL_DS; 600 601 /* 602 * Has to be the memory-operand variant because only that 603 * guarantees the CPU buffer flush functionality according to 604 * documentation. The register-operand variant does not. 605 * Works with any segment selector, but a valid writable 606 * data segment is the fastest variant. 607 * 608 * "cc" clobber is required because VERW modifies ZF. 609 */ 610 asm volatile("verw %[ds]" : : [ds] "m" (ds) : "cc"); 611 } 612 613 /** 614 * mds_idle_clear_cpu_buffers - Mitigation for MDS vulnerability 615 * 616 * Clear CPU buffers if the corresponding static key is enabled 617 */ 618 static __always_inline void mds_idle_clear_cpu_buffers(void) 619 { 620 if (static_branch_likely(&mds_idle_clear)) 621 mds_clear_cpu_buffers(); 622 } 623 624 #endif /* __ASSEMBLY__ */ 625 626 #endif /* _ASM_X86_NOSPEC_BRANCH_H_ */ 627