1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef _ASM_X86_NOSPEC_BRANCH_H_ 4 #define _ASM_X86_NOSPEC_BRANCH_H_ 5 6 #include <linux/static_key.h> 7 #include <linux/objtool.h> 8 #include <linux/linkage.h> 9 10 #include <asm/alternative.h> 11 #include <asm/cpufeatures.h> 12 #include <asm/msr-index.h> 13 #include <asm/unwind_hints.h> 14 #include <asm/percpu.h> 15 16 #define RETPOLINE_THUNK_SIZE 32 17 18 /* 19 * Fill the CPU return stack buffer. 20 * 21 * Each entry in the RSB, if used for a speculative 'ret', contains an 22 * infinite 'pause; lfence; jmp' loop to capture speculative execution. 23 * 24 * This is required in various cases for retpoline and IBRS-based 25 * mitigations for the Spectre variant 2 vulnerability. Sometimes to 26 * eliminate potentially bogus entries from the RSB, and sometimes 27 * purely to ensure that it doesn't get empty, which on some CPUs would 28 * allow predictions from other (unwanted!) sources to be used. 29 * 30 * We define a CPP macro such that it can be used from both .S files and 31 * inline assembly. It's possible to do a .macro and then include that 32 * from C via asm(".include <asm/nospec-branch.h>") but let's not go there. 33 */ 34 35 #define RSB_CLEAR_LOOPS 32 /* To forcibly overwrite all entries */ 36 37 /* 38 * Google experimented with loop-unrolling and this turned out to be 39 * the optimal version - two calls, each with their own speculation 40 * trap should their return address end up getting used, in a loop. 41 */ 42 #define __FILL_RETURN_BUFFER(reg, nr, sp) \ 43 mov $(nr/2), reg; \ 44 771: \ 45 ANNOTATE_INTRA_FUNCTION_CALL; \ 46 call 772f; \ 47 773: /* speculation trap */ \ 48 UNWIND_HINT_EMPTY; \ 49 pause; \ 50 lfence; \ 51 jmp 773b; \ 52 772: \ 53 ANNOTATE_INTRA_FUNCTION_CALL; \ 54 call 774f; \ 55 775: /* speculation trap */ \ 56 UNWIND_HINT_EMPTY; \ 57 pause; \ 58 lfence; \ 59 jmp 775b; \ 60 774: \ 61 add $(BITS_PER_LONG/8) * 2, sp; \ 62 dec reg; \ 63 jnz 771b; 64 65 #ifdef __ASSEMBLY__ 66 67 /* 68 * This should be used immediately before an indirect jump/call. It tells 69 * objtool the subsequent indirect jump/call is vouched safe for retpoline 70 * builds. 71 */ 72 .macro ANNOTATE_RETPOLINE_SAFE 73 .Lannotate_\@: 74 .pushsection .discard.retpoline_safe 75 _ASM_PTR .Lannotate_\@ 76 .popsection 77 .endm 78 79 /* 80 * (ab)use RETPOLINE_SAFE on RET to annotate away 'bare' RET instructions 81 * vs RETBleed validation. 82 */ 83 #define ANNOTATE_UNRET_SAFE ANNOTATE_RETPOLINE_SAFE 84 85 /* 86 * Abuse ANNOTATE_RETPOLINE_SAFE on a NOP to indicate UNRET_END, should 87 * eventually turn into it's own annotation. 88 */ 89 .macro ANNOTATE_UNRET_END 90 #ifdef CONFIG_DEBUG_ENTRY 91 ANNOTATE_RETPOLINE_SAFE 92 nop 93 #endif 94 .endm 95 96 /* 97 * Equivalent to -mindirect-branch-cs-prefix; emit the 5 byte jmp/call 98 * to the retpoline thunk with a CS prefix when the register requires 99 * a RAX prefix byte to encode. Also see apply_retpolines(). 100 */ 101 .macro __CS_PREFIX reg:req 102 .irp rs,r8,r9,r10,r11,r12,r13,r14,r15 103 .ifc \reg,\rs 104 .byte 0x2e 105 .endif 106 .endr 107 .endm 108 109 /* 110 * JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple 111 * indirect jmp/call which may be susceptible to the Spectre variant 2 112 * attack. 113 */ 114 .macro JMP_NOSPEC reg:req 115 #ifdef CONFIG_RETPOLINE 116 __CS_PREFIX \reg 117 jmp __x86_indirect_thunk_\reg 118 #else 119 jmp *%\reg 120 int3 121 #endif 122 .endm 123 124 .macro CALL_NOSPEC reg:req 125 #ifdef CONFIG_RETPOLINE 126 __CS_PREFIX \reg 127 call __x86_indirect_thunk_\reg 128 #else 129 call *%\reg 130 #endif 131 .endm 132 133 /* 134 * A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP 135 * monstrosity above, manually. 136 */ 137 .macro FILL_RETURN_BUFFER reg:req nr:req ftr:req 138 ALTERNATIVE "jmp .Lskip_rsb_\@", "", \ftr 139 __FILL_RETURN_BUFFER(\reg,\nr,%_ASM_SP) 140 .Lskip_rsb_\@: 141 .endm 142 143 #ifdef CONFIG_CPU_UNRET_ENTRY 144 #define CALL_ZEN_UNTRAIN_RET "call zen_untrain_ret" 145 #else 146 #define CALL_ZEN_UNTRAIN_RET "" 147 #endif 148 149 /* 150 * Mitigate RETBleed for AMD/Hygon Zen uarch. Requires KERNEL CR3 because the 151 * return thunk isn't mapped into the userspace tables (then again, AMD 152 * typically has NO_MELTDOWN). 153 * 154 * While zen_untrain_ret() doesn't clobber anything but requires stack, 155 * entry_ibpb() will clobber AX, CX, DX. 156 * 157 * As such, this must be placed after every *SWITCH_TO_KERNEL_CR3 at a point 158 * where we have a stack but before any RET instruction. 159 */ 160 .macro UNTRAIN_RET 161 #if defined(CONFIG_CPU_UNRET_ENTRY) || defined(CONFIG_CPU_IBPB_ENTRY) 162 ANNOTATE_UNRET_END 163 ALTERNATIVE_2 "", \ 164 CALL_ZEN_UNTRAIN_RET, X86_FEATURE_UNRET, \ 165 "call entry_ibpb", X86_FEATURE_ENTRY_IBPB 166 #endif 167 .endm 168 169 #else /* __ASSEMBLY__ */ 170 171 #define ANNOTATE_RETPOLINE_SAFE \ 172 "999:\n\t" \ 173 ".pushsection .discard.retpoline_safe\n\t" \ 174 _ASM_PTR " 999b\n\t" \ 175 ".popsection\n\t" 176 177 typedef u8 retpoline_thunk_t[RETPOLINE_THUNK_SIZE]; 178 extern retpoline_thunk_t __x86_indirect_thunk_array[]; 179 180 extern void __x86_return_thunk(void); 181 extern void zen_untrain_ret(void); 182 extern void entry_ibpb(void); 183 184 #ifdef CONFIG_RETPOLINE 185 186 #define GEN(reg) \ 187 extern retpoline_thunk_t __x86_indirect_thunk_ ## reg; 188 #include <asm/GEN-for-each-reg.h> 189 #undef GEN 190 191 #ifdef CONFIG_X86_64 192 193 /* 194 * Inline asm uses the %V modifier which is only in newer GCC 195 * which is ensured when CONFIG_RETPOLINE is defined. 196 */ 197 # define CALL_NOSPEC \ 198 ALTERNATIVE_2( \ 199 ANNOTATE_RETPOLINE_SAFE \ 200 "call *%[thunk_target]\n", \ 201 "call __x86_indirect_thunk_%V[thunk_target]\n", \ 202 X86_FEATURE_RETPOLINE, \ 203 "lfence;\n" \ 204 ANNOTATE_RETPOLINE_SAFE \ 205 "call *%[thunk_target]\n", \ 206 X86_FEATURE_RETPOLINE_LFENCE) 207 208 # define THUNK_TARGET(addr) [thunk_target] "r" (addr) 209 210 #else /* CONFIG_X86_32 */ 211 /* 212 * For i386 we use the original ret-equivalent retpoline, because 213 * otherwise we'll run out of registers. We don't care about CET 214 * here, anyway. 215 */ 216 # define CALL_NOSPEC \ 217 ALTERNATIVE_2( \ 218 ANNOTATE_RETPOLINE_SAFE \ 219 "call *%[thunk_target]\n", \ 220 " jmp 904f;\n" \ 221 " .align 16\n" \ 222 "901: call 903f;\n" \ 223 "902: pause;\n" \ 224 " lfence;\n" \ 225 " jmp 902b;\n" \ 226 " .align 16\n" \ 227 "903: lea 4(%%esp), %%esp;\n" \ 228 " pushl %[thunk_target];\n" \ 229 " ret;\n" \ 230 " .align 16\n" \ 231 "904: call 901b;\n", \ 232 X86_FEATURE_RETPOLINE, \ 233 "lfence;\n" \ 234 ANNOTATE_RETPOLINE_SAFE \ 235 "call *%[thunk_target]\n", \ 236 X86_FEATURE_RETPOLINE_LFENCE) 237 238 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr) 239 #endif 240 #else /* No retpoline for C / inline asm */ 241 # define CALL_NOSPEC "call *%[thunk_target]\n" 242 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr) 243 #endif 244 245 /* The Spectre V2 mitigation variants */ 246 enum spectre_v2_mitigation { 247 SPECTRE_V2_NONE, 248 SPECTRE_V2_RETPOLINE, 249 SPECTRE_V2_LFENCE, 250 SPECTRE_V2_EIBRS, 251 SPECTRE_V2_EIBRS_RETPOLINE, 252 SPECTRE_V2_EIBRS_LFENCE, 253 SPECTRE_V2_IBRS, 254 }; 255 256 /* The indirect branch speculation control variants */ 257 enum spectre_v2_user_mitigation { 258 SPECTRE_V2_USER_NONE, 259 SPECTRE_V2_USER_STRICT, 260 SPECTRE_V2_USER_STRICT_PREFERRED, 261 SPECTRE_V2_USER_PRCTL, 262 SPECTRE_V2_USER_SECCOMP, 263 }; 264 265 /* The Speculative Store Bypass disable variants */ 266 enum ssb_mitigation { 267 SPEC_STORE_BYPASS_NONE, 268 SPEC_STORE_BYPASS_DISABLE, 269 SPEC_STORE_BYPASS_PRCTL, 270 SPEC_STORE_BYPASS_SECCOMP, 271 }; 272 273 extern char __indirect_thunk_start[]; 274 extern char __indirect_thunk_end[]; 275 276 static __always_inline 277 void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature) 278 { 279 asm volatile(ALTERNATIVE("", "wrmsr", %c[feature]) 280 : : "c" (msr), 281 "a" ((u32)val), 282 "d" ((u32)(val >> 32)), 283 [feature] "i" (feature) 284 : "memory"); 285 } 286 287 static inline void indirect_branch_prediction_barrier(void) 288 { 289 u64 val = PRED_CMD_IBPB; 290 291 alternative_msr_write(MSR_IA32_PRED_CMD, val, X86_FEATURE_USE_IBPB); 292 } 293 294 /* The Intel SPEC CTRL MSR base value cache */ 295 extern u64 x86_spec_ctrl_base; 296 DECLARE_PER_CPU(u64, x86_spec_ctrl_current); 297 extern void write_spec_ctrl_current(u64 val, bool force); 298 extern u64 spec_ctrl_current(void); 299 300 /* 301 * With retpoline, we must use IBRS to restrict branch prediction 302 * before calling into firmware. 303 * 304 * (Implemented as CPP macros due to header hell.) 305 */ 306 #define firmware_restrict_branch_speculation_start() \ 307 do { \ 308 preempt_disable(); \ 309 alternative_msr_write(MSR_IA32_SPEC_CTRL, \ 310 spec_ctrl_current() | SPEC_CTRL_IBRS, \ 311 X86_FEATURE_USE_IBRS_FW); \ 312 alternative_msr_write(MSR_IA32_PRED_CMD, PRED_CMD_IBPB, \ 313 X86_FEATURE_USE_IBPB_FW); \ 314 } while (0) 315 316 #define firmware_restrict_branch_speculation_end() \ 317 do { \ 318 alternative_msr_write(MSR_IA32_SPEC_CTRL, \ 319 spec_ctrl_current(), \ 320 X86_FEATURE_USE_IBRS_FW); \ 321 preempt_enable(); \ 322 } while (0) 323 324 DECLARE_STATIC_KEY_FALSE(switch_to_cond_stibp); 325 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_ibpb); 326 DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb); 327 328 DECLARE_STATIC_KEY_FALSE(mds_user_clear); 329 DECLARE_STATIC_KEY_FALSE(mds_idle_clear); 330 331 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush); 332 333 DECLARE_STATIC_KEY_FALSE(mmio_stale_data_clear); 334 335 #include <asm/segment.h> 336 337 /** 338 * mds_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability 339 * 340 * This uses the otherwise unused and obsolete VERW instruction in 341 * combination with microcode which triggers a CPU buffer flush when the 342 * instruction is executed. 343 */ 344 static __always_inline void mds_clear_cpu_buffers(void) 345 { 346 static const u16 ds = __KERNEL_DS; 347 348 /* 349 * Has to be the memory-operand variant because only that 350 * guarantees the CPU buffer flush functionality according to 351 * documentation. The register-operand variant does not. 352 * Works with any segment selector, but a valid writable 353 * data segment is the fastest variant. 354 * 355 * "cc" clobber is required because VERW modifies ZF. 356 */ 357 asm volatile("verw %[ds]" : : [ds] "m" (ds) : "cc"); 358 } 359 360 /** 361 * mds_user_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability 362 * 363 * Clear CPU buffers if the corresponding static key is enabled 364 */ 365 static __always_inline void mds_user_clear_cpu_buffers(void) 366 { 367 if (static_branch_likely(&mds_user_clear)) 368 mds_clear_cpu_buffers(); 369 } 370 371 /** 372 * mds_idle_clear_cpu_buffers - Mitigation for MDS vulnerability 373 * 374 * Clear CPU buffers if the corresponding static key is enabled 375 */ 376 static inline void mds_idle_clear_cpu_buffers(void) 377 { 378 if (static_branch_likely(&mds_idle_clear)) 379 mds_clear_cpu_buffers(); 380 } 381 382 #endif /* __ASSEMBLY__ */ 383 384 #endif /* _ASM_X86_NOSPEC_BRANCH_H_ */ 385