1 /* SPDX-License-Identifier: GPL-2.0 */
2 
3 #ifndef _ASM_X86_NOSPEC_BRANCH_H_
4 #define _ASM_X86_NOSPEC_BRANCH_H_
5 
6 #include <linux/static_key.h>
7 #include <linux/objtool.h>
8 #include <linux/linkage.h>
9 
10 #include <asm/alternative.h>
11 #include <asm/cpufeatures.h>
12 #include <asm/msr-index.h>
13 #include <asm/unwind_hints.h>
14 #include <asm/percpu.h>
15 #include <asm/current.h>
16 
17 /*
18  * Call depth tracking for Intel SKL CPUs to address the RSB underflow
19  * issue in software.
20  *
21  * The tracking does not use a counter. It uses uses arithmetic shift
22  * right on call entry and logical shift left on return.
23  *
24  * The depth tracking variable is initialized to 0x8000.... when the call
25  * depth is zero. The arithmetic shift right sign extends the MSB and
26  * saturates after the 12th call. The shift count is 5 for both directions
27  * so the tracking covers 12 nested calls.
28  *
29  *  Call
30  *  0: 0x8000000000000000	0x0000000000000000
31  *  1: 0xfc00000000000000	0xf000000000000000
32  * ...
33  * 11: 0xfffffffffffffff8	0xfffffffffffffc00
34  * 12: 0xffffffffffffffff	0xffffffffffffffe0
35  *
36  * After a return buffer fill the depth is credited 12 calls before the
37  * next stuffing has to take place.
38  *
39  * There is a inaccuracy for situations like this:
40  *
41  *  10 calls
42  *   5 returns
43  *   3 calls
44  *   4 returns
45  *   3 calls
46  *   ....
47  *
48  * The shift count might cause this to be off by one in either direction,
49  * but there is still a cushion vs. the RSB depth. The algorithm does not
50  * claim to be perfect and it can be speculated around by the CPU, but it
51  * is considered that it obfuscates the problem enough to make exploitation
52  * extremly difficult.
53  */
54 #define RET_DEPTH_SHIFT			5
55 #define RSB_RET_STUFF_LOOPS		16
56 #define RET_DEPTH_INIT			0x8000000000000000ULL
57 #define RET_DEPTH_INIT_FROM_CALL	0xfc00000000000000ULL
58 #define RET_DEPTH_CREDIT		0xffffffffffffffffULL
59 
60 #ifdef CONFIG_CALL_THUNKS_DEBUG
61 # define CALL_THUNKS_DEBUG_INC_CALLS				\
62 	incq	%gs:__x86_call_count;
63 # define CALL_THUNKS_DEBUG_INC_RETS				\
64 	incq	%gs:__x86_ret_count;
65 # define CALL_THUNKS_DEBUG_INC_STUFFS				\
66 	incq	%gs:__x86_stuffs_count;
67 # define CALL_THUNKS_DEBUG_INC_CTXSW				\
68 	incq	%gs:__x86_ctxsw_count;
69 #else
70 # define CALL_THUNKS_DEBUG_INC_CALLS
71 # define CALL_THUNKS_DEBUG_INC_RETS
72 # define CALL_THUNKS_DEBUG_INC_STUFFS
73 # define CALL_THUNKS_DEBUG_INC_CTXSW
74 #endif
75 
76 #if defined(CONFIG_CALL_DEPTH_TRACKING) && !defined(COMPILE_OFFSETS)
77 
78 #include <asm/asm-offsets.h>
79 
80 #define CREDIT_CALL_DEPTH					\
81 	movq	$-1, PER_CPU_VAR(pcpu_hot + X86_call_depth);
82 
83 #define ASM_CREDIT_CALL_DEPTH					\
84 	movq	$-1, PER_CPU_VAR(pcpu_hot + X86_call_depth);
85 
86 #define RESET_CALL_DEPTH					\
87 	xor	%eax, %eax;					\
88 	bts	$63, %rax;					\
89 	movq	%rax, PER_CPU_VAR(pcpu_hot + X86_call_depth);
90 
91 #define RESET_CALL_DEPTH_FROM_CALL				\
92 	movb	$0xfc, %al;					\
93 	shl	$56, %rax;					\
94 	movq	%rax, PER_CPU_VAR(pcpu_hot + X86_call_depth);	\
95 	CALL_THUNKS_DEBUG_INC_CALLS
96 
97 #define INCREMENT_CALL_DEPTH					\
98 	sarq	$5, %gs:pcpu_hot + X86_call_depth;		\
99 	CALL_THUNKS_DEBUG_INC_CALLS
100 
101 #define ASM_INCREMENT_CALL_DEPTH				\
102 	sarq	$5, PER_CPU_VAR(pcpu_hot + X86_call_depth);	\
103 	CALL_THUNKS_DEBUG_INC_CALLS
104 
105 #else
106 #define CREDIT_CALL_DEPTH
107 #define ASM_CREDIT_CALL_DEPTH
108 #define RESET_CALL_DEPTH
109 #define INCREMENT_CALL_DEPTH
110 #define ASM_INCREMENT_CALL_DEPTH
111 #define RESET_CALL_DEPTH_FROM_CALL
112 #endif
113 
114 /*
115  * Fill the CPU return stack buffer.
116  *
117  * Each entry in the RSB, if used for a speculative 'ret', contains an
118  * infinite 'pause; lfence; jmp' loop to capture speculative execution.
119  *
120  * This is required in various cases for retpoline and IBRS-based
121  * mitigations for the Spectre variant 2 vulnerability. Sometimes to
122  * eliminate potentially bogus entries from the RSB, and sometimes
123  * purely to ensure that it doesn't get empty, which on some CPUs would
124  * allow predictions from other (unwanted!) sources to be used.
125  *
126  * We define a CPP macro such that it can be used from both .S files and
127  * inline assembly. It's possible to do a .macro and then include that
128  * from C via asm(".include <asm/nospec-branch.h>") but let's not go there.
129  */
130 
131 #define RETPOLINE_THUNK_SIZE	32
132 #define RSB_CLEAR_LOOPS		32	/* To forcibly overwrite all entries */
133 
134 /*
135  * Common helper for __FILL_RETURN_BUFFER and __FILL_ONE_RETURN.
136  */
137 #define __FILL_RETURN_SLOT			\
138 	ANNOTATE_INTRA_FUNCTION_CALL;		\
139 	call	772f;				\
140 	int3;					\
141 772:
142 
143 /*
144  * Stuff the entire RSB.
145  *
146  * Google experimented with loop-unrolling and this turned out to be
147  * the optimal version - two calls, each with their own speculation
148  * trap should their return address end up getting used, in a loop.
149  */
150 #ifdef CONFIG_X86_64
151 #define __FILL_RETURN_BUFFER(reg, nr)			\
152 	mov	$(nr/2), reg;				\
153 771:							\
154 	__FILL_RETURN_SLOT				\
155 	__FILL_RETURN_SLOT				\
156 	add	$(BITS_PER_LONG/8) * 2, %_ASM_SP;	\
157 	dec	reg;					\
158 	jnz	771b;					\
159 	/* barrier for jnz misprediction */		\
160 	lfence;						\
161 	ASM_CREDIT_CALL_DEPTH				\
162 	CALL_THUNKS_DEBUG_INC_CTXSW
163 #else
164 /*
165  * i386 doesn't unconditionally have LFENCE, as such it can't
166  * do a loop.
167  */
168 #define __FILL_RETURN_BUFFER(reg, nr)			\
169 	.rept nr;					\
170 	__FILL_RETURN_SLOT;				\
171 	.endr;						\
172 	add	$(BITS_PER_LONG/8) * nr, %_ASM_SP;
173 #endif
174 
175 /*
176  * Stuff a single RSB slot.
177  *
178  * To mitigate Post-Barrier RSB speculation, one CALL instruction must be
179  * forced to retire before letting a RET instruction execute.
180  *
181  * On PBRSB-vulnerable CPUs, it is not safe for a RET to be executed
182  * before this point.
183  */
184 #define __FILL_ONE_RETURN				\
185 	__FILL_RETURN_SLOT				\
186 	add	$(BITS_PER_LONG/8), %_ASM_SP;		\
187 	lfence;
188 
189 #ifdef __ASSEMBLY__
190 
191 /*
192  * This should be used immediately before an indirect jump/call. It tells
193  * objtool the subsequent indirect jump/call is vouched safe for retpoline
194  * builds.
195  */
196 .macro ANNOTATE_RETPOLINE_SAFE
197 .Lhere_\@:
198 	.pushsection .discard.retpoline_safe
199 	.long .Lhere_\@ - .
200 	.popsection
201 .endm
202 
203 /*
204  * (ab)use RETPOLINE_SAFE on RET to annotate away 'bare' RET instructions
205  * vs RETBleed validation.
206  */
207 #define ANNOTATE_UNRET_SAFE ANNOTATE_RETPOLINE_SAFE
208 
209 /*
210  * Abuse ANNOTATE_RETPOLINE_SAFE on a NOP to indicate UNRET_END, should
211  * eventually turn into it's own annotation.
212  */
213 .macro VALIDATE_UNRET_END
214 #if defined(CONFIG_NOINSTR_VALIDATION) && \
215 	(defined(CONFIG_CPU_UNRET_ENTRY) || defined(CONFIG_CPU_SRSO))
216 	ANNOTATE_RETPOLINE_SAFE
217 	nop
218 #endif
219 .endm
220 
221 /*
222  * Equivalent to -mindirect-branch-cs-prefix; emit the 5 byte jmp/call
223  * to the retpoline thunk with a CS prefix when the register requires
224  * a RAX prefix byte to encode. Also see apply_retpolines().
225  */
226 .macro __CS_PREFIX reg:req
227 	.irp rs,r8,r9,r10,r11,r12,r13,r14,r15
228 	.ifc \reg,\rs
229 	.byte 0x2e
230 	.endif
231 	.endr
232 .endm
233 
234 /*
235  * JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple
236  * indirect jmp/call which may be susceptible to the Spectre variant 2
237  * attack.
238  *
239  * NOTE: these do not take kCFI into account and are thus not comparable to C
240  * indirect calls, take care when using. The target of these should be an ENDBR
241  * instruction irrespective of kCFI.
242  */
243 .macro JMP_NOSPEC reg:req
244 #ifdef CONFIG_RETPOLINE
245 	__CS_PREFIX \reg
246 	jmp	__x86_indirect_thunk_\reg
247 #else
248 	jmp	*%\reg
249 	int3
250 #endif
251 .endm
252 
253 .macro CALL_NOSPEC reg:req
254 #ifdef CONFIG_RETPOLINE
255 	__CS_PREFIX \reg
256 	call	__x86_indirect_thunk_\reg
257 #else
258 	call	*%\reg
259 #endif
260 .endm
261 
262  /*
263   * A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP
264   * monstrosity above, manually.
265   */
266 .macro FILL_RETURN_BUFFER reg:req nr:req ftr:req ftr2=ALT_NOT(X86_FEATURE_ALWAYS)
267 	ALTERNATIVE_2 "jmp .Lskip_rsb_\@", \
268 		__stringify(__FILL_RETURN_BUFFER(\reg,\nr)), \ftr, \
269 		__stringify(nop;nop;__FILL_ONE_RETURN), \ftr2
270 
271 .Lskip_rsb_\@:
272 .endm
273 
274 #ifdef CONFIG_CPU_UNRET_ENTRY
275 #define CALL_UNTRAIN_RET	"call entry_untrain_ret"
276 #else
277 #define CALL_UNTRAIN_RET	""
278 #endif
279 
280 /*
281  * Mitigate RETBleed for AMD/Hygon Zen uarch. Requires KERNEL CR3 because the
282  * return thunk isn't mapped into the userspace tables (then again, AMD
283  * typically has NO_MELTDOWN).
284  *
285  * While retbleed_untrain_ret() doesn't clobber anything but requires stack,
286  * entry_ibpb() will clobber AX, CX, DX.
287  *
288  * As such, this must be placed after every *SWITCH_TO_KERNEL_CR3 at a point
289  * where we have a stack but before any RET instruction.
290  */
291 .macro UNTRAIN_RET
292 #if defined(CONFIG_CPU_UNRET_ENTRY) || defined(CONFIG_CPU_IBPB_ENTRY) || \
293 	defined(CONFIG_CALL_DEPTH_TRACKING) || defined(CONFIG_CPU_SRSO)
294 	VALIDATE_UNRET_END
295 	ALTERNATIVE_3 "",						\
296 		      CALL_UNTRAIN_RET, X86_FEATURE_UNRET,		\
297 		      "call entry_ibpb", X86_FEATURE_ENTRY_IBPB,	\
298 		      __stringify(RESET_CALL_DEPTH), X86_FEATURE_CALL_DEPTH
299 #endif
300 .endm
301 
302 .macro UNTRAIN_RET_VM
303 #if defined(CONFIG_CPU_UNRET_ENTRY) || defined(CONFIG_CPU_IBPB_ENTRY) || \
304 	defined(CONFIG_CALL_DEPTH_TRACKING) || defined(CONFIG_CPU_SRSO)
305 	VALIDATE_UNRET_END
306 	ALTERNATIVE_3 "",						\
307 		      CALL_UNTRAIN_RET, X86_FEATURE_UNRET,		\
308 		      "call entry_ibpb", X86_FEATURE_IBPB_ON_VMEXIT,	\
309 		      __stringify(RESET_CALL_DEPTH), X86_FEATURE_CALL_DEPTH
310 #endif
311 .endm
312 
313 .macro UNTRAIN_RET_FROM_CALL
314 #if defined(CONFIG_CPU_UNRET_ENTRY) || defined(CONFIG_CPU_IBPB_ENTRY) || \
315 	defined(CONFIG_CALL_DEPTH_TRACKING)
316 	VALIDATE_UNRET_END
317 	ALTERNATIVE_3 "",						\
318 		      CALL_UNTRAIN_RET, X86_FEATURE_UNRET,		\
319 		      "call entry_ibpb", X86_FEATURE_ENTRY_IBPB,	\
320 		      __stringify(RESET_CALL_DEPTH_FROM_CALL), X86_FEATURE_CALL_DEPTH
321 #endif
322 .endm
323 
324 
325 .macro CALL_DEPTH_ACCOUNT
326 #ifdef CONFIG_CALL_DEPTH_TRACKING
327 	ALTERNATIVE "",							\
328 		    __stringify(ASM_INCREMENT_CALL_DEPTH), X86_FEATURE_CALL_DEPTH
329 #endif
330 .endm
331 
332 #else /* __ASSEMBLY__ */
333 
334 #define ANNOTATE_RETPOLINE_SAFE					\
335 	"999:\n\t"						\
336 	".pushsection .discard.retpoline_safe\n\t"		\
337 	".long 999b - .\n\t"					\
338 	".popsection\n\t"
339 
340 typedef u8 retpoline_thunk_t[RETPOLINE_THUNK_SIZE];
341 extern retpoline_thunk_t __x86_indirect_thunk_array[];
342 extern retpoline_thunk_t __x86_indirect_call_thunk_array[];
343 extern retpoline_thunk_t __x86_indirect_jump_thunk_array[];
344 
345 #ifdef CONFIG_RETHUNK
346 extern void __x86_return_thunk(void);
347 #else
348 static inline void __x86_return_thunk(void) {}
349 #endif
350 
351 extern void retbleed_return_thunk(void);
352 extern void srso_return_thunk(void);
353 extern void srso_alias_return_thunk(void);
354 
355 extern void retbleed_untrain_ret(void);
356 extern void srso_untrain_ret(void);
357 extern void srso_alias_untrain_ret(void);
358 
359 extern void entry_untrain_ret(void);
360 extern void entry_ibpb(void);
361 
362 extern void (*x86_return_thunk)(void);
363 
364 #ifdef CONFIG_CALL_DEPTH_TRACKING
365 extern void __x86_return_skl(void);
366 
367 static inline void x86_set_skl_return_thunk(void)
368 {
369 	x86_return_thunk = &__x86_return_skl;
370 }
371 
372 #define CALL_DEPTH_ACCOUNT					\
373 	ALTERNATIVE("",						\
374 		    __stringify(INCREMENT_CALL_DEPTH),		\
375 		    X86_FEATURE_CALL_DEPTH)
376 
377 #ifdef CONFIG_CALL_THUNKS_DEBUG
378 DECLARE_PER_CPU(u64, __x86_call_count);
379 DECLARE_PER_CPU(u64, __x86_ret_count);
380 DECLARE_PER_CPU(u64, __x86_stuffs_count);
381 DECLARE_PER_CPU(u64, __x86_ctxsw_count);
382 #endif
383 #else
384 static inline void x86_set_skl_return_thunk(void) {}
385 
386 #define CALL_DEPTH_ACCOUNT ""
387 
388 #endif
389 
390 #ifdef CONFIG_RETPOLINE
391 
392 #define GEN(reg) \
393 	extern retpoline_thunk_t __x86_indirect_thunk_ ## reg;
394 #include <asm/GEN-for-each-reg.h>
395 #undef GEN
396 
397 #define GEN(reg)						\
398 	extern retpoline_thunk_t __x86_indirect_call_thunk_ ## reg;
399 #include <asm/GEN-for-each-reg.h>
400 #undef GEN
401 
402 #define GEN(reg)						\
403 	extern retpoline_thunk_t __x86_indirect_jump_thunk_ ## reg;
404 #include <asm/GEN-for-each-reg.h>
405 #undef GEN
406 
407 #ifdef CONFIG_X86_64
408 
409 /*
410  * Inline asm uses the %V modifier which is only in newer GCC
411  * which is ensured when CONFIG_RETPOLINE is defined.
412  */
413 # define CALL_NOSPEC						\
414 	ALTERNATIVE_2(						\
415 	ANNOTATE_RETPOLINE_SAFE					\
416 	"call *%[thunk_target]\n",				\
417 	"call __x86_indirect_thunk_%V[thunk_target]\n",		\
418 	X86_FEATURE_RETPOLINE,					\
419 	"lfence;\n"						\
420 	ANNOTATE_RETPOLINE_SAFE					\
421 	"call *%[thunk_target]\n",				\
422 	X86_FEATURE_RETPOLINE_LFENCE)
423 
424 # define THUNK_TARGET(addr) [thunk_target] "r" (addr)
425 
426 #else /* CONFIG_X86_32 */
427 /*
428  * For i386 we use the original ret-equivalent retpoline, because
429  * otherwise we'll run out of registers. We don't care about CET
430  * here, anyway.
431  */
432 # define CALL_NOSPEC						\
433 	ALTERNATIVE_2(						\
434 	ANNOTATE_RETPOLINE_SAFE					\
435 	"call *%[thunk_target]\n",				\
436 	"       jmp    904f;\n"					\
437 	"       .align 16\n"					\
438 	"901:	call   903f;\n"					\
439 	"902:	pause;\n"					\
440 	"    	lfence;\n"					\
441 	"       jmp    902b;\n"					\
442 	"       .align 16\n"					\
443 	"903:	lea    4(%%esp), %%esp;\n"			\
444 	"       pushl  %[thunk_target];\n"			\
445 	"       ret;\n"						\
446 	"       .align 16\n"					\
447 	"904:	call   901b;\n",				\
448 	X86_FEATURE_RETPOLINE,					\
449 	"lfence;\n"						\
450 	ANNOTATE_RETPOLINE_SAFE					\
451 	"call *%[thunk_target]\n",				\
452 	X86_FEATURE_RETPOLINE_LFENCE)
453 
454 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
455 #endif
456 #else /* No retpoline for C / inline asm */
457 # define CALL_NOSPEC "call *%[thunk_target]\n"
458 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
459 #endif
460 
461 /* The Spectre V2 mitigation variants */
462 enum spectre_v2_mitigation {
463 	SPECTRE_V2_NONE,
464 	SPECTRE_V2_RETPOLINE,
465 	SPECTRE_V2_LFENCE,
466 	SPECTRE_V2_EIBRS,
467 	SPECTRE_V2_EIBRS_RETPOLINE,
468 	SPECTRE_V2_EIBRS_LFENCE,
469 	SPECTRE_V2_IBRS,
470 };
471 
472 /* The indirect branch speculation control variants */
473 enum spectre_v2_user_mitigation {
474 	SPECTRE_V2_USER_NONE,
475 	SPECTRE_V2_USER_STRICT,
476 	SPECTRE_V2_USER_STRICT_PREFERRED,
477 	SPECTRE_V2_USER_PRCTL,
478 	SPECTRE_V2_USER_SECCOMP,
479 };
480 
481 /* The Speculative Store Bypass disable variants */
482 enum ssb_mitigation {
483 	SPEC_STORE_BYPASS_NONE,
484 	SPEC_STORE_BYPASS_DISABLE,
485 	SPEC_STORE_BYPASS_PRCTL,
486 	SPEC_STORE_BYPASS_SECCOMP,
487 };
488 
489 static __always_inline
490 void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature)
491 {
492 	asm volatile(ALTERNATIVE("", "wrmsr", %c[feature])
493 		: : "c" (msr),
494 		    "a" ((u32)val),
495 		    "d" ((u32)(val >> 32)),
496 		    [feature] "i" (feature)
497 		: "memory");
498 }
499 
500 extern u64 x86_pred_cmd;
501 
502 static inline void indirect_branch_prediction_barrier(void)
503 {
504 	alternative_msr_write(MSR_IA32_PRED_CMD, x86_pred_cmd, X86_FEATURE_USE_IBPB);
505 }
506 
507 /* The Intel SPEC CTRL MSR base value cache */
508 extern u64 x86_spec_ctrl_base;
509 DECLARE_PER_CPU(u64, x86_spec_ctrl_current);
510 extern void update_spec_ctrl_cond(u64 val);
511 extern u64 spec_ctrl_current(void);
512 
513 /*
514  * With retpoline, we must use IBRS to restrict branch prediction
515  * before calling into firmware.
516  *
517  * (Implemented as CPP macros due to header hell.)
518  */
519 #define firmware_restrict_branch_speculation_start()			\
520 do {									\
521 	preempt_disable();						\
522 	alternative_msr_write(MSR_IA32_SPEC_CTRL,			\
523 			      spec_ctrl_current() | SPEC_CTRL_IBRS,	\
524 			      X86_FEATURE_USE_IBRS_FW);			\
525 	alternative_msr_write(MSR_IA32_PRED_CMD, PRED_CMD_IBPB,		\
526 			      X86_FEATURE_USE_IBPB_FW);			\
527 } while (0)
528 
529 #define firmware_restrict_branch_speculation_end()			\
530 do {									\
531 	alternative_msr_write(MSR_IA32_SPEC_CTRL,			\
532 			      spec_ctrl_current(),			\
533 			      X86_FEATURE_USE_IBRS_FW);			\
534 	preempt_enable();						\
535 } while (0)
536 
537 DECLARE_STATIC_KEY_FALSE(switch_to_cond_stibp);
538 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
539 DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
540 
541 DECLARE_STATIC_KEY_FALSE(mds_user_clear);
542 DECLARE_STATIC_KEY_FALSE(mds_idle_clear);
543 
544 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
545 
546 DECLARE_STATIC_KEY_FALSE(mmio_stale_data_clear);
547 
548 #include <asm/segment.h>
549 
550 /**
551  * mds_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
552  *
553  * This uses the otherwise unused and obsolete VERW instruction in
554  * combination with microcode which triggers a CPU buffer flush when the
555  * instruction is executed.
556  */
557 static __always_inline void mds_clear_cpu_buffers(void)
558 {
559 	static const u16 ds = __KERNEL_DS;
560 
561 	/*
562 	 * Has to be the memory-operand variant because only that
563 	 * guarantees the CPU buffer flush functionality according to
564 	 * documentation. The register-operand variant does not.
565 	 * Works with any segment selector, but a valid writable
566 	 * data segment is the fastest variant.
567 	 *
568 	 * "cc" clobber is required because VERW modifies ZF.
569 	 */
570 	asm volatile("verw %[ds]" : : [ds] "m" (ds) : "cc");
571 }
572 
573 /**
574  * mds_user_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
575  *
576  * Clear CPU buffers if the corresponding static key is enabled
577  */
578 static __always_inline void mds_user_clear_cpu_buffers(void)
579 {
580 	if (static_branch_likely(&mds_user_clear))
581 		mds_clear_cpu_buffers();
582 }
583 
584 /**
585  * mds_idle_clear_cpu_buffers - Mitigation for MDS vulnerability
586  *
587  * Clear CPU buffers if the corresponding static key is enabled
588  */
589 static __always_inline void mds_idle_clear_cpu_buffers(void)
590 {
591 	if (static_branch_likely(&mds_idle_clear))
592 		mds_clear_cpu_buffers();
593 }
594 
595 #endif /* __ASSEMBLY__ */
596 
597 #endif /* _ASM_X86_NOSPEC_BRANCH_H_ */
598