1 #ifndef _ASM_X86_MWAIT_H 2 #define _ASM_X86_MWAIT_H 3 4 #include <linux/sched.h> 5 6 #include <asm/cpufeature.h> 7 8 #define MWAIT_SUBSTATE_MASK 0xf 9 #define MWAIT_CSTATE_MASK 0xf 10 #define MWAIT_SUBSTATE_SIZE 4 11 #define MWAIT_HINT2CSTATE(hint) (((hint) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) 12 #define MWAIT_HINT2SUBSTATE(hint) ((hint) & MWAIT_CSTATE_MASK) 13 14 #define CPUID_MWAIT_LEAF 5 15 #define CPUID5_ECX_EXTENSIONS_SUPPORTED 0x1 16 #define CPUID5_ECX_INTERRUPT_BREAK 0x2 17 18 #define MWAIT_ECX_INTERRUPT_BREAK 0x1 19 #define MWAITX_ECX_TIMER_ENABLE BIT(1) 20 #define MWAITX_MAX_LOOPS ((u32)-1) 21 #define MWAITX_DISABLE_CSTATES 0xf 22 23 static inline void __monitor(const void *eax, unsigned long ecx, 24 unsigned long edx) 25 { 26 /* "monitor %eax, %ecx, %edx;" */ 27 asm volatile(".byte 0x0f, 0x01, 0xc8;" 28 :: "a" (eax), "c" (ecx), "d"(edx)); 29 } 30 31 static inline void __monitorx(const void *eax, unsigned long ecx, 32 unsigned long edx) 33 { 34 /* "monitorx %eax, %ecx, %edx;" */ 35 asm volatile(".byte 0x0f, 0x01, 0xfa;" 36 :: "a" (eax), "c" (ecx), "d"(edx)); 37 } 38 39 static inline void __mwait(unsigned long eax, unsigned long ecx) 40 { 41 /* "mwait %eax, %ecx;" */ 42 asm volatile(".byte 0x0f, 0x01, 0xc9;" 43 :: "a" (eax), "c" (ecx)); 44 } 45 46 /* 47 * MWAITX allows for a timer expiration to get the core out a wait state in 48 * addition to the default MWAIT exit condition of a store appearing at a 49 * monitored virtual address. 50 * 51 * Registers: 52 * 53 * MWAITX ECX[1]: enable timer if set 54 * MWAITX EBX[31:0]: max wait time expressed in SW P0 clocks. The software P0 55 * frequency is the same as the TSC frequency. 56 * 57 * Below is a comparison between MWAIT and MWAITX on AMD processors: 58 * 59 * MWAIT MWAITX 60 * opcode 0f 01 c9 | 0f 01 fb 61 * ECX[0] value of RFLAGS.IF seen by instruction 62 * ECX[1] unused/#GP if set | enable timer if set 63 * ECX[31:2] unused/#GP if set 64 * EAX unused (reserve for hint) 65 * EBX[31:0] unused | max wait time (P0 clocks) 66 * 67 * MONITOR MONITORX 68 * opcode 0f 01 c8 | 0f 01 fa 69 * EAX (logical) address to monitor 70 * ECX #GP if not zero 71 */ 72 static inline void __mwaitx(unsigned long eax, unsigned long ebx, 73 unsigned long ecx) 74 { 75 /* "mwaitx %eax, %ebx, %ecx;" */ 76 asm volatile(".byte 0x0f, 0x01, 0xfb;" 77 :: "a" (eax), "b" (ebx), "c" (ecx)); 78 } 79 80 static inline void __sti_mwait(unsigned long eax, unsigned long ecx) 81 { 82 trace_hardirqs_on(); 83 /* "mwait %eax, %ecx;" */ 84 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;" 85 :: "a" (eax), "c" (ecx)); 86 } 87 88 /* 89 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI, 90 * which can obviate IPI to trigger checking of need_resched. 91 * We execute MONITOR against need_resched and enter optimized wait state 92 * through MWAIT. Whenever someone changes need_resched, we would be woken 93 * up from MWAIT (without an IPI). 94 * 95 * New with Core Duo processors, MWAIT can take some hints based on CPU 96 * capability. 97 */ 98 static inline void mwait_idle_with_hints(unsigned long eax, unsigned long ecx) 99 { 100 if (!current_set_polling_and_test()) { 101 if (static_cpu_has_bug(X86_BUG_CLFLUSH_MONITOR)) { 102 mb(); 103 clflush((void *)¤t_thread_info()->flags); 104 mb(); 105 } 106 107 __monitor((void *)¤t_thread_info()->flags, 0, 0); 108 if (!need_resched()) 109 __mwait(eax, ecx); 110 } 111 current_clr_polling(); 112 } 113 114 #endif /* _ASM_X86_MWAIT_H */ 115