1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_MSR_H 3 #define _ASM_X86_MSR_H 4 5 #include "msr-index.h" 6 7 #ifndef __ASSEMBLY__ 8 9 #include <asm/asm.h> 10 #include <asm/errno.h> 11 #include <asm/cpumask.h> 12 #include <uapi/asm/msr.h> 13 14 struct msr { 15 union { 16 struct { 17 u32 l; 18 u32 h; 19 }; 20 u64 q; 21 }; 22 }; 23 24 struct msr_info { 25 u32 msr_no; 26 struct msr reg; 27 struct msr *msrs; 28 int err; 29 }; 30 31 struct msr_regs_info { 32 u32 *regs; 33 int err; 34 }; 35 36 struct saved_msr { 37 bool valid; 38 struct msr_info info; 39 }; 40 41 struct saved_msrs { 42 unsigned int num; 43 struct saved_msr *array; 44 }; 45 46 /* 47 * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A" 48 * constraint has different meanings. For i386, "A" means exactly 49 * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead, 50 * it means rax *or* rdx. 51 */ 52 #ifdef CONFIG_X86_64 53 /* Using 64-bit values saves one instruction clearing the high half of low */ 54 #define DECLARE_ARGS(val, low, high) unsigned long low, high 55 #define EAX_EDX_VAL(val, low, high) ((low) | (high) << 32) 56 #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) 57 #else 58 #define DECLARE_ARGS(val, low, high) unsigned long long val 59 #define EAX_EDX_VAL(val, low, high) (val) 60 #define EAX_EDX_RET(val, low, high) "=A" (val) 61 #endif 62 63 #ifdef CONFIG_TRACEPOINTS 64 /* 65 * Be very careful with includes. This header is prone to include loops. 66 */ 67 #include <asm/atomic.h> 68 #include <linux/tracepoint-defs.h> 69 70 extern struct tracepoint __tracepoint_read_msr; 71 extern struct tracepoint __tracepoint_write_msr; 72 extern struct tracepoint __tracepoint_rdpmc; 73 #define msr_tracepoint_active(t) static_key_false(&(t).key) 74 extern void do_trace_write_msr(unsigned int msr, u64 val, int failed); 75 extern void do_trace_read_msr(unsigned int msr, u64 val, int failed); 76 extern void do_trace_rdpmc(unsigned int msr, u64 val, int failed); 77 #else 78 #define msr_tracepoint_active(t) false 79 static inline void do_trace_write_msr(unsigned int msr, u64 val, int failed) {} 80 static inline void do_trace_read_msr(unsigned int msr, u64 val, int failed) {} 81 static inline void do_trace_rdpmc(unsigned int msr, u64 val, int failed) {} 82 #endif 83 84 /* 85 * __rdmsr() and __wrmsr() are the two primitives which are the bare minimum MSR 86 * accessors and should not have any tracing or other functionality piggybacking 87 * on them - those are *purely* for accessing MSRs and nothing more. So don't even 88 * think of extending them - you will be slapped with a stinking trout or a frozen 89 * shark will reach you, wherever you are! You've been warned. 90 */ 91 static inline unsigned long long notrace __rdmsr(unsigned int msr) 92 { 93 DECLARE_ARGS(val, low, high); 94 95 asm volatile("1: rdmsr\n" 96 "2:\n" 97 _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_rdmsr_unsafe) 98 : EAX_EDX_RET(val, low, high) : "c" (msr)); 99 100 return EAX_EDX_VAL(val, low, high); 101 } 102 103 static inline void notrace __wrmsr(unsigned int msr, u32 low, u32 high) 104 { 105 asm volatile("1: wrmsr\n" 106 "2:\n" 107 _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_wrmsr_unsafe) 108 : : "c" (msr), "a"(low), "d" (high) : "memory"); 109 } 110 111 static inline unsigned long long native_read_msr(unsigned int msr) 112 { 113 unsigned long long val; 114 115 val = __rdmsr(msr); 116 117 if (msr_tracepoint_active(__tracepoint_read_msr)) 118 do_trace_read_msr(msr, val, 0); 119 120 return val; 121 } 122 123 static inline unsigned long long native_read_msr_safe(unsigned int msr, 124 int *err) 125 { 126 DECLARE_ARGS(val, low, high); 127 128 asm volatile("2: rdmsr ; xor %[err],%[err]\n" 129 "1:\n\t" 130 ".section .fixup,\"ax\"\n\t" 131 "3: mov %[fault],%[err]\n\t" 132 "xorl %%eax, %%eax\n\t" 133 "xorl %%edx, %%edx\n\t" 134 "jmp 1b\n\t" 135 ".previous\n\t" 136 _ASM_EXTABLE(2b, 3b) 137 : [err] "=r" (*err), EAX_EDX_RET(val, low, high) 138 : "c" (msr), [fault] "i" (-EIO)); 139 if (msr_tracepoint_active(__tracepoint_read_msr)) 140 do_trace_read_msr(msr, EAX_EDX_VAL(val, low, high), *err); 141 return EAX_EDX_VAL(val, low, high); 142 } 143 144 /* Can be uninlined because referenced by paravirt */ 145 static inline void notrace 146 native_write_msr(unsigned int msr, u32 low, u32 high) 147 { 148 __wrmsr(msr, low, high); 149 150 if (msr_tracepoint_active(__tracepoint_write_msr)) 151 do_trace_write_msr(msr, ((u64)high << 32 | low), 0); 152 } 153 154 /* Can be uninlined because referenced by paravirt */ 155 static inline int notrace 156 native_write_msr_safe(unsigned int msr, u32 low, u32 high) 157 { 158 int err; 159 160 asm volatile("2: wrmsr ; xor %[err],%[err]\n" 161 "1:\n\t" 162 ".section .fixup,\"ax\"\n\t" 163 "3: mov %[fault],%[err] ; jmp 1b\n\t" 164 ".previous\n\t" 165 _ASM_EXTABLE(2b, 3b) 166 : [err] "=a" (err) 167 : "c" (msr), "0" (low), "d" (high), 168 [fault] "i" (-EIO) 169 : "memory"); 170 if (msr_tracepoint_active(__tracepoint_write_msr)) 171 do_trace_write_msr(msr, ((u64)high << 32 | low), err); 172 return err; 173 } 174 175 extern int rdmsr_safe_regs(u32 regs[8]); 176 extern int wrmsr_safe_regs(u32 regs[8]); 177 178 /** 179 * rdtsc() - returns the current TSC without ordering constraints 180 * 181 * rdtsc() returns the result of RDTSC as a 64-bit integer. The 182 * only ordering constraint it supplies is the ordering implied by 183 * "asm volatile": it will put the RDTSC in the place you expect. The 184 * CPU can and will speculatively execute that RDTSC, though, so the 185 * results can be non-monotonic if compared on different CPUs. 186 */ 187 static __always_inline unsigned long long rdtsc(void) 188 { 189 DECLARE_ARGS(val, low, high); 190 191 asm volatile("rdtsc" : EAX_EDX_RET(val, low, high)); 192 193 return EAX_EDX_VAL(val, low, high); 194 } 195 196 /** 197 * rdtsc_ordered() - read the current TSC in program order 198 * 199 * rdtsc_ordered() returns the result of RDTSC as a 64-bit integer. 200 * It is ordered like a load to a global in-memory counter. It should 201 * be impossible to observe non-monotonic rdtsc_unordered() behavior 202 * across multiple CPUs as long as the TSC is synced. 203 */ 204 static __always_inline unsigned long long rdtsc_ordered(void) 205 { 206 /* 207 * The RDTSC instruction is not ordered relative to memory 208 * access. The Intel SDM and the AMD APM are both vague on this 209 * point, but empirically an RDTSC instruction can be 210 * speculatively executed before prior loads. An RDTSC 211 * immediately after an appropriate barrier appears to be 212 * ordered as a normal load, that is, it provides the same 213 * ordering guarantees as reading from a global memory location 214 * that some other imaginary CPU is updating continuously with a 215 * time stamp. 216 */ 217 barrier_nospec(); 218 return rdtsc(); 219 } 220 221 /* Deprecated, keep it for a cycle for easier merging: */ 222 #define rdtscll(now) do { (now) = rdtsc_ordered(); } while (0) 223 224 static inline unsigned long long native_read_pmc(int counter) 225 { 226 DECLARE_ARGS(val, low, high); 227 228 asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter)); 229 if (msr_tracepoint_active(__tracepoint_rdpmc)) 230 do_trace_rdpmc(counter, EAX_EDX_VAL(val, low, high), 0); 231 return EAX_EDX_VAL(val, low, high); 232 } 233 234 #ifdef CONFIG_PARAVIRT 235 #include <asm/paravirt.h> 236 #else 237 #include <linux/errno.h> 238 /* 239 * Access to machine-specific registers (available on 586 and better only) 240 * Note: the rd* operations modify the parameters directly (without using 241 * pointer indirection), this allows gcc to optimize better 242 */ 243 244 #define rdmsr(msr, low, high) \ 245 do { \ 246 u64 __val = native_read_msr((msr)); \ 247 (void)((low) = (u32)__val); \ 248 (void)((high) = (u32)(__val >> 32)); \ 249 } while (0) 250 251 static inline void wrmsr(unsigned int msr, u32 low, u32 high) 252 { 253 native_write_msr(msr, low, high); 254 } 255 256 #define rdmsrl(msr, val) \ 257 ((val) = native_read_msr((msr))) 258 259 static inline void wrmsrl(unsigned int msr, u64 val) 260 { 261 native_write_msr(msr, (u32)(val & 0xffffffffULL), (u32)(val >> 32)); 262 } 263 264 /* wrmsr with exception handling */ 265 static inline int wrmsr_safe(unsigned int msr, u32 low, u32 high) 266 { 267 return native_write_msr_safe(msr, low, high); 268 } 269 270 /* rdmsr with exception handling */ 271 #define rdmsr_safe(msr, low, high) \ 272 ({ \ 273 int __err; \ 274 u64 __val = native_read_msr_safe((msr), &__err); \ 275 (*low) = (u32)__val; \ 276 (*high) = (u32)(__val >> 32); \ 277 __err; \ 278 }) 279 280 static inline int rdmsrl_safe(unsigned int msr, unsigned long long *p) 281 { 282 int err; 283 284 *p = native_read_msr_safe(msr, &err); 285 return err; 286 } 287 288 #define rdpmc(counter, low, high) \ 289 do { \ 290 u64 _l = native_read_pmc((counter)); \ 291 (low) = (u32)_l; \ 292 (high) = (u32)(_l >> 32); \ 293 } while (0) 294 295 #define rdpmcl(counter, val) ((val) = native_read_pmc(counter)) 296 297 #endif /* !CONFIG_PARAVIRT */ 298 299 /* 300 * 64-bit version of wrmsr_safe(): 301 */ 302 static inline int wrmsrl_safe(u32 msr, u64 val) 303 { 304 return wrmsr_safe(msr, (u32)val, (u32)(val >> 32)); 305 } 306 307 #define write_tsc(low, high) wrmsr(MSR_IA32_TSC, (low), (high)) 308 309 #define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0) 310 311 struct msr *msrs_alloc(void); 312 void msrs_free(struct msr *msrs); 313 int msr_set_bit(u32 msr, u8 bit); 314 int msr_clear_bit(u32 msr, u8 bit); 315 316 #ifdef CONFIG_SMP 317 int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); 318 int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); 319 int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); 320 int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q); 321 void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); 322 void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); 323 int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); 324 int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); 325 int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); 326 int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q); 327 int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); 328 int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); 329 #else /* CONFIG_SMP */ 330 static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) 331 { 332 rdmsr(msr_no, *l, *h); 333 return 0; 334 } 335 static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) 336 { 337 wrmsr(msr_no, l, h); 338 return 0; 339 } 340 static inline int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) 341 { 342 rdmsrl(msr_no, *q); 343 return 0; 344 } 345 static inline int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q) 346 { 347 wrmsrl(msr_no, q); 348 return 0; 349 } 350 static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no, 351 struct msr *msrs) 352 { 353 rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h)); 354 } 355 static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no, 356 struct msr *msrs) 357 { 358 wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h); 359 } 360 static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, 361 u32 *l, u32 *h) 362 { 363 return rdmsr_safe(msr_no, l, h); 364 } 365 static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) 366 { 367 return wrmsr_safe(msr_no, l, h); 368 } 369 static inline int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) 370 { 371 return rdmsrl_safe(msr_no, q); 372 } 373 static inline int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) 374 { 375 return wrmsrl_safe(msr_no, q); 376 } 377 static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) 378 { 379 return rdmsr_safe_regs(regs); 380 } 381 static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) 382 { 383 return wrmsr_safe_regs(regs); 384 } 385 #endif /* CONFIG_SMP */ 386 #endif /* __ASSEMBLY__ */ 387 #endif /* _ASM_X86_MSR_H */ 388