1 #ifndef _ASM_X86_MSR_H 2 #define _ASM_X86_MSR_H 3 4 #include "msr-index.h" 5 6 #ifndef __ASSEMBLY__ 7 8 #include <asm/asm.h> 9 #include <asm/errno.h> 10 #include <asm/cpumask.h> 11 #include <uapi/asm/msr.h> 12 13 struct msr { 14 union { 15 struct { 16 u32 l; 17 u32 h; 18 }; 19 u64 q; 20 }; 21 }; 22 23 struct msr_info { 24 u32 msr_no; 25 struct msr reg; 26 struct msr *msrs; 27 int err; 28 }; 29 30 struct msr_regs_info { 31 u32 *regs; 32 int err; 33 }; 34 35 static inline unsigned long long native_read_tscp(unsigned int *aux) 36 { 37 unsigned long low, high; 38 asm volatile(".byte 0x0f,0x01,0xf9" 39 : "=a" (low), "=d" (high), "=c" (*aux)); 40 return low | ((u64)high << 32); 41 } 42 43 /* 44 * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A" 45 * constraint has different meanings. For i386, "A" means exactly 46 * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead, 47 * it means rax *or* rdx. 48 */ 49 #ifdef CONFIG_X86_64 50 /* Using 64-bit values saves one instruction clearing the high half of low */ 51 #define DECLARE_ARGS(val, low, high) unsigned long low, high 52 #define EAX_EDX_VAL(val, low, high) ((low) | (high) << 32) 53 #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) 54 #else 55 #define DECLARE_ARGS(val, low, high) unsigned long long val 56 #define EAX_EDX_VAL(val, low, high) (val) 57 #define EAX_EDX_RET(val, low, high) "=A" (val) 58 #endif 59 60 static inline unsigned long long native_read_msr(unsigned int msr) 61 { 62 DECLARE_ARGS(val, low, high); 63 64 asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr)); 65 return EAX_EDX_VAL(val, low, high); 66 } 67 68 static inline unsigned long long native_read_msr_safe(unsigned int msr, 69 int *err) 70 { 71 DECLARE_ARGS(val, low, high); 72 73 asm volatile("2: rdmsr ; xor %[err],%[err]\n" 74 "1:\n\t" 75 ".section .fixup,\"ax\"\n\t" 76 "3: mov %[fault],%[err] ; jmp 1b\n\t" 77 ".previous\n\t" 78 _ASM_EXTABLE(2b, 3b) 79 : [err] "=r" (*err), EAX_EDX_RET(val, low, high) 80 : "c" (msr), [fault] "i" (-EIO)); 81 return EAX_EDX_VAL(val, low, high); 82 } 83 84 static inline void native_write_msr(unsigned int msr, 85 unsigned low, unsigned high) 86 { 87 asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory"); 88 } 89 90 /* Can be uninlined because referenced by paravirt */ 91 notrace static inline int native_write_msr_safe(unsigned int msr, 92 unsigned low, unsigned high) 93 { 94 int err; 95 asm volatile("2: wrmsr ; xor %[err],%[err]\n" 96 "1:\n\t" 97 ".section .fixup,\"ax\"\n\t" 98 "3: mov %[fault],%[err] ; jmp 1b\n\t" 99 ".previous\n\t" 100 _ASM_EXTABLE(2b, 3b) 101 : [err] "=a" (err) 102 : "c" (msr), "0" (low), "d" (high), 103 [fault] "i" (-EIO) 104 : "memory"); 105 return err; 106 } 107 108 extern int rdmsr_safe_regs(u32 regs[8]); 109 extern int wrmsr_safe_regs(u32 regs[8]); 110 111 /** 112 * rdtsc() - returns the current TSC without ordering constraints 113 * 114 * rdtsc() returns the result of RDTSC as a 64-bit integer. The 115 * only ordering constraint it supplies is the ordering implied by 116 * "asm volatile": it will put the RDTSC in the place you expect. The 117 * CPU can and will speculatively execute that RDTSC, though, so the 118 * results can be non-monotonic if compared on different CPUs. 119 */ 120 static __always_inline unsigned long long rdtsc(void) 121 { 122 DECLARE_ARGS(val, low, high); 123 124 asm volatile("rdtsc" : EAX_EDX_RET(val, low, high)); 125 126 return EAX_EDX_VAL(val, low, high); 127 } 128 129 /** 130 * rdtsc_ordered() - read the current TSC in program order 131 * 132 * rdtsc_ordered() returns the result of RDTSC as a 64-bit integer. 133 * It is ordered like a load to a global in-memory counter. It should 134 * be impossible to observe non-monotonic rdtsc_unordered() behavior 135 * across multiple CPUs as long as the TSC is synced. 136 */ 137 static __always_inline unsigned long long rdtsc_ordered(void) 138 { 139 /* 140 * The RDTSC instruction is not ordered relative to memory 141 * access. The Intel SDM and the AMD APM are both vague on this 142 * point, but empirically an RDTSC instruction can be 143 * speculatively executed before prior loads. An RDTSC 144 * immediately after an appropriate barrier appears to be 145 * ordered as a normal load, that is, it provides the same 146 * ordering guarantees as reading from a global memory location 147 * that some other imaginary CPU is updating continuously with a 148 * time stamp. 149 */ 150 alternative_2("", "mfence", X86_FEATURE_MFENCE_RDTSC, 151 "lfence", X86_FEATURE_LFENCE_RDTSC); 152 return rdtsc(); 153 } 154 155 /* Deprecated, keep it for a cycle for easier merging: */ 156 #define rdtscll(now) do { (now) = rdtsc_ordered(); } while (0) 157 158 static inline unsigned long long native_read_pmc(int counter) 159 { 160 DECLARE_ARGS(val, low, high); 161 162 asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter)); 163 return EAX_EDX_VAL(val, low, high); 164 } 165 166 #ifdef CONFIG_PARAVIRT 167 #include <asm/paravirt.h> 168 #else 169 #include <linux/errno.h> 170 /* 171 * Access to machine-specific registers (available on 586 and better only) 172 * Note: the rd* operations modify the parameters directly (without using 173 * pointer indirection), this allows gcc to optimize better 174 */ 175 176 #define rdmsr(msr, low, high) \ 177 do { \ 178 u64 __val = native_read_msr((msr)); \ 179 (void)((low) = (u32)__val); \ 180 (void)((high) = (u32)(__val >> 32)); \ 181 } while (0) 182 183 static inline void wrmsr(unsigned msr, unsigned low, unsigned high) 184 { 185 native_write_msr(msr, low, high); 186 } 187 188 #define rdmsrl(msr, val) \ 189 ((val) = native_read_msr((msr))) 190 191 static inline void wrmsrl(unsigned msr, u64 val) 192 { 193 native_write_msr(msr, (u32)val, (u32)(val >> 32)); 194 } 195 196 /* wrmsr with exception handling */ 197 static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) 198 { 199 return native_write_msr_safe(msr, low, high); 200 } 201 202 /* rdmsr with exception handling */ 203 #define rdmsr_safe(msr, low, high) \ 204 ({ \ 205 int __err; \ 206 u64 __val = native_read_msr_safe((msr), &__err); \ 207 (*low) = (u32)__val; \ 208 (*high) = (u32)(__val >> 32); \ 209 __err; \ 210 }) 211 212 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) 213 { 214 int err; 215 216 *p = native_read_msr_safe(msr, &err); 217 return err; 218 } 219 220 #define rdpmc(counter, low, high) \ 221 do { \ 222 u64 _l = native_read_pmc((counter)); \ 223 (low) = (u32)_l; \ 224 (high) = (u32)(_l >> 32); \ 225 } while (0) 226 227 #define rdpmcl(counter, val) ((val) = native_read_pmc(counter)) 228 229 #endif /* !CONFIG_PARAVIRT */ 230 231 /* 232 * 64-bit version of wrmsr_safe(): 233 */ 234 static inline int wrmsrl_safe(u32 msr, u64 val) 235 { 236 return wrmsr_safe(msr, (u32)val, (u32)(val >> 32)); 237 } 238 239 #define write_tsc(low, high) wrmsr(MSR_IA32_TSC, (low), (high)) 240 241 #define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0) 242 243 struct msr *msrs_alloc(void); 244 void msrs_free(struct msr *msrs); 245 int msr_set_bit(u32 msr, u8 bit); 246 int msr_clear_bit(u32 msr, u8 bit); 247 248 #ifdef CONFIG_SMP 249 int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); 250 int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); 251 int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); 252 int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q); 253 void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); 254 void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); 255 int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); 256 int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); 257 int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); 258 int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q); 259 int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); 260 int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); 261 #else /* CONFIG_SMP */ 262 static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) 263 { 264 rdmsr(msr_no, *l, *h); 265 return 0; 266 } 267 static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) 268 { 269 wrmsr(msr_no, l, h); 270 return 0; 271 } 272 static inline int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) 273 { 274 rdmsrl(msr_no, *q); 275 return 0; 276 } 277 static inline int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q) 278 { 279 wrmsrl(msr_no, q); 280 return 0; 281 } 282 static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no, 283 struct msr *msrs) 284 { 285 rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h)); 286 } 287 static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no, 288 struct msr *msrs) 289 { 290 wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h); 291 } 292 static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, 293 u32 *l, u32 *h) 294 { 295 return rdmsr_safe(msr_no, l, h); 296 } 297 static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) 298 { 299 return wrmsr_safe(msr_no, l, h); 300 } 301 static inline int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) 302 { 303 return rdmsrl_safe(msr_no, q); 304 } 305 static inline int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) 306 { 307 return wrmsrl_safe(msr_no, q); 308 } 309 static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) 310 { 311 return rdmsr_safe_regs(regs); 312 } 313 static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) 314 { 315 return wrmsr_safe_regs(regs); 316 } 317 #endif /* CONFIG_SMP */ 318 #endif /* __ASSEMBLY__ */ 319 #endif /* _ASM_X86_MSR_H */ 320