1 #ifndef _ASM_X86_MSR_H 2 #define _ASM_X86_MSR_H 3 4 #include <asm/msr-index.h> 5 6 #ifndef __ASSEMBLY__ 7 8 #include <linux/types.h> 9 #include <linux/ioctl.h> 10 11 #define X86_IOC_RDMSR_REGS _IOWR('c', 0xA0, __u32[8]) 12 #define X86_IOC_WRMSR_REGS _IOWR('c', 0xA1, __u32[8]) 13 14 #ifdef __KERNEL__ 15 16 #include <asm/asm.h> 17 #include <asm/errno.h> 18 #include <asm/cpumask.h> 19 20 struct msr { 21 union { 22 struct { 23 u32 l; 24 u32 h; 25 }; 26 u64 q; 27 }; 28 }; 29 30 static inline unsigned long long native_read_tscp(unsigned int *aux) 31 { 32 unsigned long low, high; 33 asm volatile(".byte 0x0f,0x01,0xf9" 34 : "=a" (low), "=d" (high), "=c" (*aux)); 35 return low | ((u64)high << 32); 36 } 37 38 /* 39 * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A" 40 * constraint has different meanings. For i386, "A" means exactly 41 * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead, 42 * it means rax *or* rdx. 43 */ 44 #ifdef CONFIG_X86_64 45 #define DECLARE_ARGS(val, low, high) unsigned low, high 46 #define EAX_EDX_VAL(val, low, high) ((low) | ((u64)(high) << 32)) 47 #define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high) 48 #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) 49 #else 50 #define DECLARE_ARGS(val, low, high) unsigned long long val 51 #define EAX_EDX_VAL(val, low, high) (val) 52 #define EAX_EDX_ARGS(val, low, high) "A" (val) 53 #define EAX_EDX_RET(val, low, high) "=A" (val) 54 #endif 55 56 static inline unsigned long long native_read_msr(unsigned int msr) 57 { 58 DECLARE_ARGS(val, low, high); 59 60 asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr)); 61 return EAX_EDX_VAL(val, low, high); 62 } 63 64 static inline unsigned long long native_read_msr_safe(unsigned int msr, 65 int *err) 66 { 67 DECLARE_ARGS(val, low, high); 68 69 asm volatile("2: rdmsr ; xor %[err],%[err]\n" 70 "1:\n\t" 71 ".section .fixup,\"ax\"\n\t" 72 "3: mov %[fault],%[err] ; jmp 1b\n\t" 73 ".previous\n\t" 74 _ASM_EXTABLE(2b, 3b) 75 : [err] "=r" (*err), EAX_EDX_RET(val, low, high) 76 : "c" (msr), [fault] "i" (-EIO)); 77 return EAX_EDX_VAL(val, low, high); 78 } 79 80 static inline void native_write_msr(unsigned int msr, 81 unsigned low, unsigned high) 82 { 83 asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory"); 84 } 85 86 /* Can be uninlined because referenced by paravirt */ 87 notrace static inline int native_write_msr_safe(unsigned int msr, 88 unsigned low, unsigned high) 89 { 90 int err; 91 asm volatile("2: wrmsr ; xor %[err],%[err]\n" 92 "1:\n\t" 93 ".section .fixup,\"ax\"\n\t" 94 "3: mov %[fault],%[err] ; jmp 1b\n\t" 95 ".previous\n\t" 96 _ASM_EXTABLE(2b, 3b) 97 : [err] "=a" (err) 98 : "c" (msr), "0" (low), "d" (high), 99 [fault] "i" (-EIO) 100 : "memory"); 101 return err; 102 } 103 104 extern unsigned long long native_read_tsc(void); 105 106 extern int native_rdmsr_safe_regs(u32 regs[8]); 107 extern int native_wrmsr_safe_regs(u32 regs[8]); 108 109 static __always_inline unsigned long long __native_read_tsc(void) 110 { 111 DECLARE_ARGS(val, low, high); 112 113 asm volatile("rdtsc" : EAX_EDX_RET(val, low, high)); 114 115 return EAX_EDX_VAL(val, low, high); 116 } 117 118 static inline unsigned long long native_read_pmc(int counter) 119 { 120 DECLARE_ARGS(val, low, high); 121 122 asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter)); 123 return EAX_EDX_VAL(val, low, high); 124 } 125 126 #ifdef CONFIG_PARAVIRT 127 #include <asm/paravirt.h> 128 #else 129 #include <linux/errno.h> 130 /* 131 * Access to machine-specific registers (available on 586 and better only) 132 * Note: the rd* operations modify the parameters directly (without using 133 * pointer indirection), this allows gcc to optimize better 134 */ 135 136 #define rdmsr(msr, val1, val2) \ 137 do { \ 138 u64 __val = native_read_msr((msr)); \ 139 (val1) = (u32)__val; \ 140 (val2) = (u32)(__val >> 32); \ 141 } while (0) 142 143 static inline void wrmsr(unsigned msr, unsigned low, unsigned high) 144 { 145 native_write_msr(msr, low, high); 146 } 147 148 #define rdmsrl(msr, val) \ 149 ((val) = native_read_msr((msr))) 150 151 #define wrmsrl(msr, val) \ 152 native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32)) 153 154 /* wrmsr with exception handling */ 155 static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) 156 { 157 return native_write_msr_safe(msr, low, high); 158 } 159 160 /* rdmsr with exception handling */ 161 #define rdmsr_safe(msr, p1, p2) \ 162 ({ \ 163 int __err; \ 164 u64 __val = native_read_msr_safe((msr), &__err); \ 165 (*p1) = (u32)__val; \ 166 (*p2) = (u32)(__val >> 32); \ 167 __err; \ 168 }) 169 170 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) 171 { 172 int err; 173 174 *p = native_read_msr_safe(msr, &err); 175 return err; 176 } 177 178 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) 179 { 180 u32 gprs[8] = { 0 }; 181 int err; 182 183 gprs[1] = msr; 184 gprs[7] = 0x9c5a203a; 185 186 err = native_rdmsr_safe_regs(gprs); 187 188 *p = gprs[0] | ((u64)gprs[2] << 32); 189 190 return err; 191 } 192 193 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) 194 { 195 u32 gprs[8] = { 0 }; 196 197 gprs[0] = (u32)val; 198 gprs[1] = msr; 199 gprs[2] = val >> 32; 200 gprs[7] = 0x9c5a203a; 201 202 return native_wrmsr_safe_regs(gprs); 203 } 204 205 static inline int rdmsr_safe_regs(u32 regs[8]) 206 { 207 return native_rdmsr_safe_regs(regs); 208 } 209 210 static inline int wrmsr_safe_regs(u32 regs[8]) 211 { 212 return native_wrmsr_safe_regs(regs); 213 } 214 215 #define rdtscl(low) \ 216 ((low) = (u32)__native_read_tsc()) 217 218 #define rdtscll(val) \ 219 ((val) = __native_read_tsc()) 220 221 #define rdpmc(counter, low, high) \ 222 do { \ 223 u64 _l = native_read_pmc((counter)); \ 224 (low) = (u32)_l; \ 225 (high) = (u32)(_l >> 32); \ 226 } while (0) 227 228 #define rdtscp(low, high, aux) \ 229 do { \ 230 unsigned long long _val = native_read_tscp(&(aux)); \ 231 (low) = (u32)_val; \ 232 (high) = (u32)(_val >> 32); \ 233 } while (0) 234 235 #define rdtscpll(val, aux) (val) = native_read_tscp(&(aux)) 236 237 #endif /* !CONFIG_PARAVIRT */ 238 239 240 #define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val), \ 241 (u32)((val) >> 32)) 242 243 #define write_tsc(val1, val2) wrmsr(0x10, (val1), (val2)) 244 245 #define write_rdtscp_aux(val) wrmsr(0xc0000103, (val), 0) 246 247 #ifdef CONFIG_SMP 248 int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); 249 int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); 250 void rdmsr_on_cpus(const cpumask_t *mask, u32 msr_no, struct msr *msrs); 251 void wrmsr_on_cpus(const cpumask_t *mask, u32 msr_no, struct msr *msrs); 252 int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); 253 int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); 254 int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); 255 int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); 256 #else /* CONFIG_SMP */ 257 static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) 258 { 259 rdmsr(msr_no, *l, *h); 260 return 0; 261 } 262 static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) 263 { 264 wrmsr(msr_no, l, h); 265 return 0; 266 } 267 static inline void rdmsr_on_cpus(const cpumask_t *m, u32 msr_no, 268 struct msr *msrs) 269 { 270 rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h)); 271 } 272 static inline void wrmsr_on_cpus(const cpumask_t *m, u32 msr_no, 273 struct msr *msrs) 274 { 275 wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h); 276 } 277 static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, 278 u32 *l, u32 *h) 279 { 280 return rdmsr_safe(msr_no, l, h); 281 } 282 static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) 283 { 284 return wrmsr_safe(msr_no, l, h); 285 } 286 static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) 287 { 288 return rdmsr_safe_regs(regs); 289 } 290 static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) 291 { 292 return wrmsr_safe_regs(regs); 293 } 294 #endif /* CONFIG_SMP */ 295 #endif /* __KERNEL__ */ 296 #endif /* __ASSEMBLY__ */ 297 #endif /* _ASM_X86_MSR_H */ 298