1 #ifndef _ASM_X86_MSR_H 2 #define _ASM_X86_MSR_H 3 4 #include <asm/msr-index.h> 5 6 #ifndef __ASSEMBLY__ 7 8 #include <linux/types.h> 9 #include <linux/ioctl.h> 10 11 #define X86_IOC_RDMSR_REGS _IOWR('c', 0xA0, __u32[8]) 12 #define X86_IOC_WRMSR_REGS _IOWR('c', 0xA1, __u32[8]) 13 14 #ifdef __KERNEL__ 15 16 #include <asm/asm.h> 17 #include <asm/errno.h> 18 #include <asm/cpumask.h> 19 20 struct msr { 21 union { 22 struct { 23 u32 l; 24 u32 h; 25 }; 26 u64 q; 27 }; 28 }; 29 30 struct msr_info { 31 u32 msr_no; 32 struct msr reg; 33 struct msr *msrs; 34 int err; 35 }; 36 37 struct msr_regs_info { 38 u32 *regs; 39 int err; 40 }; 41 42 static inline unsigned long long native_read_tscp(unsigned int *aux) 43 { 44 unsigned long low, high; 45 asm volatile(".byte 0x0f,0x01,0xf9" 46 : "=a" (low), "=d" (high), "=c" (*aux)); 47 return low | ((u64)high << 32); 48 } 49 50 /* 51 * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A" 52 * constraint has different meanings. For i386, "A" means exactly 53 * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead, 54 * it means rax *or* rdx. 55 */ 56 #ifdef CONFIG_X86_64 57 #define DECLARE_ARGS(val, low, high) unsigned low, high 58 #define EAX_EDX_VAL(val, low, high) ((low) | ((u64)(high) << 32)) 59 #define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high) 60 #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) 61 #else 62 #define DECLARE_ARGS(val, low, high) unsigned long long val 63 #define EAX_EDX_VAL(val, low, high) (val) 64 #define EAX_EDX_ARGS(val, low, high) "A" (val) 65 #define EAX_EDX_RET(val, low, high) "=A" (val) 66 #endif 67 68 static inline unsigned long long native_read_msr(unsigned int msr) 69 { 70 DECLARE_ARGS(val, low, high); 71 72 asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr)); 73 return EAX_EDX_VAL(val, low, high); 74 } 75 76 static inline unsigned long long native_read_msr_safe(unsigned int msr, 77 int *err) 78 { 79 DECLARE_ARGS(val, low, high); 80 81 asm volatile("2: rdmsr ; xor %[err],%[err]\n" 82 "1:\n\t" 83 ".section .fixup,\"ax\"\n\t" 84 "3: mov %[fault],%[err] ; jmp 1b\n\t" 85 ".previous\n\t" 86 _ASM_EXTABLE(2b, 3b) 87 : [err] "=r" (*err), EAX_EDX_RET(val, low, high) 88 : "c" (msr), [fault] "i" (-EIO)); 89 return EAX_EDX_VAL(val, low, high); 90 } 91 92 static inline void native_write_msr(unsigned int msr, 93 unsigned low, unsigned high) 94 { 95 asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory"); 96 } 97 98 /* Can be uninlined because referenced by paravirt */ 99 notrace static inline int native_write_msr_safe(unsigned int msr, 100 unsigned low, unsigned high) 101 { 102 int err; 103 asm volatile("2: wrmsr ; xor %[err],%[err]\n" 104 "1:\n\t" 105 ".section .fixup,\"ax\"\n\t" 106 "3: mov %[fault],%[err] ; jmp 1b\n\t" 107 ".previous\n\t" 108 _ASM_EXTABLE(2b, 3b) 109 : [err] "=a" (err) 110 : "c" (msr), "0" (low), "d" (high), 111 [fault] "i" (-EIO) 112 : "memory"); 113 return err; 114 } 115 116 extern unsigned long long native_read_tsc(void); 117 118 extern int rdmsr_safe_regs(u32 regs[8]); 119 extern int wrmsr_safe_regs(u32 regs[8]); 120 121 static __always_inline unsigned long long __native_read_tsc(void) 122 { 123 DECLARE_ARGS(val, low, high); 124 125 asm volatile("rdtsc" : EAX_EDX_RET(val, low, high)); 126 127 return EAX_EDX_VAL(val, low, high); 128 } 129 130 static inline unsigned long long native_read_pmc(int counter) 131 { 132 DECLARE_ARGS(val, low, high); 133 134 asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter)); 135 return EAX_EDX_VAL(val, low, high); 136 } 137 138 #ifdef CONFIG_PARAVIRT 139 #include <asm/paravirt.h> 140 #else 141 #include <linux/errno.h> 142 /* 143 * Access to machine-specific registers (available on 586 and better only) 144 * Note: the rd* operations modify the parameters directly (without using 145 * pointer indirection), this allows gcc to optimize better 146 */ 147 148 #define rdmsr(msr, val1, val2) \ 149 do { \ 150 u64 __val = native_read_msr((msr)); \ 151 (void)((val1) = (u32)__val); \ 152 (void)((val2) = (u32)(__val >> 32)); \ 153 } while (0) 154 155 static inline void wrmsr(unsigned msr, unsigned low, unsigned high) 156 { 157 native_write_msr(msr, low, high); 158 } 159 160 #define rdmsrl(msr, val) \ 161 ((val) = native_read_msr((msr))) 162 163 #define wrmsrl(msr, val) \ 164 native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32)) 165 166 /* wrmsr with exception handling */ 167 static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) 168 { 169 return native_write_msr_safe(msr, low, high); 170 } 171 172 /* rdmsr with exception handling */ 173 #define rdmsr_safe(msr, p1, p2) \ 174 ({ \ 175 int __err; \ 176 u64 __val = native_read_msr_safe((msr), &__err); \ 177 (*p1) = (u32)__val; \ 178 (*p2) = (u32)(__val >> 32); \ 179 __err; \ 180 }) 181 182 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) 183 { 184 int err; 185 186 *p = native_read_msr_safe(msr, &err); 187 return err; 188 } 189 190 #define rdtscl(low) \ 191 ((low) = (u32)__native_read_tsc()) 192 193 #define rdtscll(val) \ 194 ((val) = __native_read_tsc()) 195 196 #define rdpmc(counter, low, high) \ 197 do { \ 198 u64 _l = native_read_pmc((counter)); \ 199 (low) = (u32)_l; \ 200 (high) = (u32)(_l >> 32); \ 201 } while (0) 202 203 #define rdpmcl(counter, val) ((val) = native_read_pmc(counter)) 204 205 #define rdtscp(low, high, aux) \ 206 do { \ 207 unsigned long long _val = native_read_tscp(&(aux)); \ 208 (low) = (u32)_val; \ 209 (high) = (u32)(_val >> 32); \ 210 } while (0) 211 212 #define rdtscpll(val, aux) (val) = native_read_tscp(&(aux)) 213 214 #endif /* !CONFIG_PARAVIRT */ 215 216 #define wrmsrl_safe(msr, val) wrmsr_safe((msr), (u32)(val), \ 217 (u32)((val) >> 32)) 218 219 #define write_tsc(val1, val2) wrmsr(MSR_IA32_TSC, (val1), (val2)) 220 221 #define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0) 222 223 struct msr *msrs_alloc(void); 224 void msrs_free(struct msr *msrs); 225 226 #ifdef CONFIG_SMP 227 int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); 228 int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); 229 void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); 230 void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); 231 int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); 232 int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); 233 int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); 234 int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); 235 #else /* CONFIG_SMP */ 236 static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) 237 { 238 rdmsr(msr_no, *l, *h); 239 return 0; 240 } 241 static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) 242 { 243 wrmsr(msr_no, l, h); 244 return 0; 245 } 246 static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no, 247 struct msr *msrs) 248 { 249 rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h)); 250 } 251 static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no, 252 struct msr *msrs) 253 { 254 wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h); 255 } 256 static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, 257 u32 *l, u32 *h) 258 { 259 return rdmsr_safe(msr_no, l, h); 260 } 261 static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) 262 { 263 return wrmsr_safe(msr_no, l, h); 264 } 265 static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) 266 { 267 return rdmsr_safe_regs(regs); 268 } 269 static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) 270 { 271 return wrmsr_safe_regs(regs); 272 } 273 #endif /* CONFIG_SMP */ 274 #endif /* __KERNEL__ */ 275 #endif /* __ASSEMBLY__ */ 276 #endif /* _ASM_X86_MSR_H */ 277