1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_MSR_INDEX_H 3 #define _ASM_X86_MSR_INDEX_H 4 5 /* 6 * CPU model specific register (MSR) numbers. 7 * 8 * Do not add new entries to this file unless the definitions are shared 9 * between multiple compilation units. 10 */ 11 12 /* x86-64 specific MSRs */ 13 #define MSR_EFER 0xc0000080 /* extended feature register */ 14 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 15 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 16 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 17 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 18 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 19 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 20 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 21 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 22 23 /* EFER bits: */ 24 #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 25 #define _EFER_LME 8 /* Long mode enable */ 26 #define _EFER_LMA 10 /* Long mode active (read-only) */ 27 #define _EFER_NX 11 /* No execute enable */ 28 #define _EFER_SVME 12 /* Enable virtualization */ 29 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 30 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 31 32 #define EFER_SCE (1<<_EFER_SCE) 33 #define EFER_LME (1<<_EFER_LME) 34 #define EFER_LMA (1<<_EFER_LMA) 35 #define EFER_NX (1<<_EFER_NX) 36 #define EFER_SVME (1<<_EFER_SVME) 37 #define EFER_LMSLE (1<<_EFER_LMSLE) 38 #define EFER_FFXSR (1<<_EFER_FFXSR) 39 40 /* Intel MSRs. Some also available on other CPUs */ 41 42 #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 43 #define SPEC_CTRL_IBRS (1 << 0) /* Indirect Branch Restricted Speculation */ 44 #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ 45 #define SPEC_CTRL_STIBP (1 << SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ 46 #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ 47 #define SPEC_CTRL_SSBD (1 << SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ 48 49 #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 50 #define PRED_CMD_IBPB (1 << 0) /* Indirect Branch Prediction Barrier */ 51 52 #define MSR_PPIN_CTL 0x0000004e 53 #define MSR_PPIN 0x0000004f 54 55 #define MSR_IA32_PERFCTR0 0x000000c1 56 #define MSR_IA32_PERFCTR1 0x000000c2 57 #define MSR_FSB_FREQ 0x000000cd 58 #define MSR_PLATFORM_INFO 0x000000ce 59 #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 60 #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) 61 62 #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 63 #define NHM_C3_AUTO_DEMOTE (1UL << 25) 64 #define NHM_C1_AUTO_DEMOTE (1UL << 26) 65 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 66 #define SNB_C3_AUTO_UNDEMOTE (1UL << 27) 67 #define SNB_C1_AUTO_UNDEMOTE (1UL << 28) 68 69 #define MSR_MTRRcap 0x000000fe 70 71 #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 72 #define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to Meltdown */ 73 #define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */ 74 #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH (1 << 3) /* Skip L1D flush on vmentry */ 75 #define ARCH_CAP_SSB_NO (1 << 4) /* 76 * Not susceptible to Speculative Store Bypass 77 * attack, so no Speculative Store Bypass 78 * control required. 79 */ 80 81 #define MSR_IA32_FLUSH_CMD 0x0000010b 82 #define L1D_FLUSH (1 << 0) /* 83 * Writeback and invalidate the 84 * L1 data cache. 85 */ 86 87 #define MSR_IA32_BBL_CR_CTL 0x00000119 88 #define MSR_IA32_BBL_CR_CTL3 0x0000011e 89 90 #define MSR_IA32_SYSENTER_CS 0x00000174 91 #define MSR_IA32_SYSENTER_ESP 0x00000175 92 #define MSR_IA32_SYSENTER_EIP 0x00000176 93 94 #define MSR_IA32_MCG_CAP 0x00000179 95 #define MSR_IA32_MCG_STATUS 0x0000017a 96 #define MSR_IA32_MCG_CTL 0x0000017b 97 #define MSR_IA32_MCG_EXT_CTL 0x000004d0 98 99 #define MSR_OFFCORE_RSP_0 0x000001a6 100 #define MSR_OFFCORE_RSP_1 0x000001a7 101 #define MSR_TURBO_RATIO_LIMIT 0x000001ad 102 #define MSR_TURBO_RATIO_LIMIT1 0x000001ae 103 #define MSR_TURBO_RATIO_LIMIT2 0x000001af 104 105 #define MSR_LBR_SELECT 0x000001c8 106 #define MSR_LBR_TOS 0x000001c9 107 #define MSR_LBR_NHM_FROM 0x00000680 108 #define MSR_LBR_NHM_TO 0x000006c0 109 #define MSR_LBR_CORE_FROM 0x00000040 110 #define MSR_LBR_CORE_TO 0x00000060 111 112 #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 113 #define LBR_INFO_MISPRED BIT_ULL(63) 114 #define LBR_INFO_IN_TX BIT_ULL(62) 115 #define LBR_INFO_ABORT BIT_ULL(61) 116 #define LBR_INFO_CYCLES 0xffff 117 118 #define MSR_IA32_PEBS_ENABLE 0x000003f1 119 #define MSR_IA32_DS_AREA 0x00000600 120 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 121 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 122 123 #define MSR_IA32_RTIT_CTL 0x00000570 124 #define RTIT_CTL_TRACEEN BIT(0) 125 #define RTIT_CTL_CYCLEACC BIT(1) 126 #define RTIT_CTL_OS BIT(2) 127 #define RTIT_CTL_USR BIT(3) 128 #define RTIT_CTL_PWR_EVT_EN BIT(4) 129 #define RTIT_CTL_FUP_ON_PTW BIT(5) 130 #define RTIT_CTL_FABRIC_EN BIT(6) 131 #define RTIT_CTL_CR3EN BIT(7) 132 #define RTIT_CTL_TOPA BIT(8) 133 #define RTIT_CTL_MTC_EN BIT(9) 134 #define RTIT_CTL_TSC_EN BIT(10) 135 #define RTIT_CTL_DISRETC BIT(11) 136 #define RTIT_CTL_PTW_EN BIT(12) 137 #define RTIT_CTL_BRANCH_EN BIT(13) 138 #define RTIT_CTL_MTC_RANGE_OFFSET 14 139 #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 140 #define RTIT_CTL_CYC_THRESH_OFFSET 19 141 #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 142 #define RTIT_CTL_PSB_FREQ_OFFSET 24 143 #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 144 #define RTIT_CTL_ADDR0_OFFSET 32 145 #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) 146 #define RTIT_CTL_ADDR1_OFFSET 36 147 #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) 148 #define RTIT_CTL_ADDR2_OFFSET 40 149 #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) 150 #define RTIT_CTL_ADDR3_OFFSET 44 151 #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) 152 #define MSR_IA32_RTIT_STATUS 0x00000571 153 #define RTIT_STATUS_FILTEREN BIT(0) 154 #define RTIT_STATUS_CONTEXTEN BIT(1) 155 #define RTIT_STATUS_TRIGGEREN BIT(2) 156 #define RTIT_STATUS_BUFFOVF BIT(3) 157 #define RTIT_STATUS_ERROR BIT(4) 158 #define RTIT_STATUS_STOPPED BIT(5) 159 #define RTIT_STATUS_BYTECNT_OFFSET 32 160 #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) 161 #define MSR_IA32_RTIT_ADDR0_A 0x00000580 162 #define MSR_IA32_RTIT_ADDR0_B 0x00000581 163 #define MSR_IA32_RTIT_ADDR1_A 0x00000582 164 #define MSR_IA32_RTIT_ADDR1_B 0x00000583 165 #define MSR_IA32_RTIT_ADDR2_A 0x00000584 166 #define MSR_IA32_RTIT_ADDR2_B 0x00000585 167 #define MSR_IA32_RTIT_ADDR3_A 0x00000586 168 #define MSR_IA32_RTIT_ADDR3_B 0x00000587 169 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 170 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 171 #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 172 173 #define MSR_MTRRfix64K_00000 0x00000250 174 #define MSR_MTRRfix16K_80000 0x00000258 175 #define MSR_MTRRfix16K_A0000 0x00000259 176 #define MSR_MTRRfix4K_C0000 0x00000268 177 #define MSR_MTRRfix4K_C8000 0x00000269 178 #define MSR_MTRRfix4K_D0000 0x0000026a 179 #define MSR_MTRRfix4K_D8000 0x0000026b 180 #define MSR_MTRRfix4K_E0000 0x0000026c 181 #define MSR_MTRRfix4K_E8000 0x0000026d 182 #define MSR_MTRRfix4K_F0000 0x0000026e 183 #define MSR_MTRRfix4K_F8000 0x0000026f 184 #define MSR_MTRRdefType 0x000002ff 185 186 #define MSR_IA32_CR_PAT 0x00000277 187 188 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 189 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 190 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 191 #define MSR_IA32_LASTINTFROMIP 0x000001dd 192 #define MSR_IA32_LASTINTTOIP 0x000001de 193 194 /* DEBUGCTLMSR bits (others vary by model): */ 195 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 196 #define DEBUGCTLMSR_BTF_SHIFT 1 197 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 198 #define DEBUGCTLMSR_TR (1UL << 6) 199 #define DEBUGCTLMSR_BTS (1UL << 7) 200 #define DEBUGCTLMSR_BTINT (1UL << 8) 201 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 202 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 203 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 204 #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) 205 #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 206 #define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 207 208 #define MSR_PEBS_FRONTEND 0x000003f7 209 210 #define MSR_IA32_POWER_CTL 0x000001fc 211 212 #define MSR_IA32_MC0_CTL 0x00000400 213 #define MSR_IA32_MC0_STATUS 0x00000401 214 #define MSR_IA32_MC0_ADDR 0x00000402 215 #define MSR_IA32_MC0_MISC 0x00000403 216 217 /* C-state Residency Counters */ 218 #define MSR_PKG_C3_RESIDENCY 0x000003f8 219 #define MSR_PKG_C6_RESIDENCY 0x000003f9 220 #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 221 #define MSR_PKG_C7_RESIDENCY 0x000003fa 222 #define MSR_CORE_C3_RESIDENCY 0x000003fc 223 #define MSR_CORE_C6_RESIDENCY 0x000003fd 224 #define MSR_CORE_C7_RESIDENCY 0x000003fe 225 #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 226 #define MSR_PKG_C2_RESIDENCY 0x0000060d 227 #define MSR_PKG_C8_RESIDENCY 0x00000630 228 #define MSR_PKG_C9_RESIDENCY 0x00000631 229 #define MSR_PKG_C10_RESIDENCY 0x00000632 230 231 /* Interrupt Response Limit */ 232 #define MSR_PKGC3_IRTL 0x0000060a 233 #define MSR_PKGC6_IRTL 0x0000060b 234 #define MSR_PKGC7_IRTL 0x0000060c 235 #define MSR_PKGC8_IRTL 0x00000633 236 #define MSR_PKGC9_IRTL 0x00000634 237 #define MSR_PKGC10_IRTL 0x00000635 238 239 /* Run Time Average Power Limiting (RAPL) Interface */ 240 241 #define MSR_RAPL_POWER_UNIT 0x00000606 242 243 #define MSR_PKG_POWER_LIMIT 0x00000610 244 #define MSR_PKG_ENERGY_STATUS 0x00000611 245 #define MSR_PKG_PERF_STATUS 0x00000613 246 #define MSR_PKG_POWER_INFO 0x00000614 247 248 #define MSR_DRAM_POWER_LIMIT 0x00000618 249 #define MSR_DRAM_ENERGY_STATUS 0x00000619 250 #define MSR_DRAM_PERF_STATUS 0x0000061b 251 #define MSR_DRAM_POWER_INFO 0x0000061c 252 253 #define MSR_PP0_POWER_LIMIT 0x00000638 254 #define MSR_PP0_ENERGY_STATUS 0x00000639 255 #define MSR_PP0_POLICY 0x0000063a 256 #define MSR_PP0_PERF_STATUS 0x0000063b 257 258 #define MSR_PP1_POWER_LIMIT 0x00000640 259 #define MSR_PP1_ENERGY_STATUS 0x00000641 260 #define MSR_PP1_POLICY 0x00000642 261 262 /* Config TDP MSRs */ 263 #define MSR_CONFIG_TDP_NOMINAL 0x00000648 264 #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 265 #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 266 #define MSR_CONFIG_TDP_CONTROL 0x0000064B 267 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 268 269 #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 270 271 #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 272 #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 273 #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 274 #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 275 276 #define MSR_CORE_C1_RES 0x00000660 277 #define MSR_MODULE_C6_RES_MS 0x00000664 278 279 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 280 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 281 282 #define MSR_ATOM_CORE_RATIOS 0x0000066a 283 #define MSR_ATOM_CORE_VIDS 0x0000066b 284 #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 285 #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 286 287 288 #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 289 #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 290 #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 291 292 /* Hardware P state interface */ 293 #define MSR_PPERF 0x0000064e 294 #define MSR_PERF_LIMIT_REASONS 0x0000064f 295 #define MSR_PM_ENABLE 0x00000770 296 #define MSR_HWP_CAPABILITIES 0x00000771 297 #define MSR_HWP_REQUEST_PKG 0x00000772 298 #define MSR_HWP_INTERRUPT 0x00000773 299 #define MSR_HWP_REQUEST 0x00000774 300 #define MSR_HWP_STATUS 0x00000777 301 302 /* CPUID.6.EAX */ 303 #define HWP_BASE_BIT (1<<7) 304 #define HWP_NOTIFICATIONS_BIT (1<<8) 305 #define HWP_ACTIVITY_WINDOW_BIT (1<<9) 306 #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 307 #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 308 309 /* IA32_HWP_CAPABILITIES */ 310 #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 311 #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 312 #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 313 #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 314 315 /* IA32_HWP_REQUEST */ 316 #define HWP_MIN_PERF(x) (x & 0xff) 317 #define HWP_MAX_PERF(x) ((x & 0xff) << 8) 318 #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 319 #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) 320 #define HWP_EPP_PERFORMANCE 0x00 321 #define HWP_EPP_BALANCE_PERFORMANCE 0x80 322 #define HWP_EPP_BALANCE_POWERSAVE 0xC0 323 #define HWP_EPP_POWERSAVE 0xFF 324 #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) 325 #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) 326 327 /* IA32_HWP_STATUS */ 328 #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 329 #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 330 331 /* IA32_HWP_INTERRUPT */ 332 #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 333 #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 334 335 #define MSR_AMD64_MC0_MASK 0xc0010044 336 337 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 338 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 339 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 340 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 341 342 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 343 344 /* These are consecutive and not in the normal 4er MCE bank block */ 345 #define MSR_IA32_MC0_CTL2 0x00000280 346 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 347 348 #define MSR_P6_PERFCTR0 0x000000c1 349 #define MSR_P6_PERFCTR1 0x000000c2 350 #define MSR_P6_EVNTSEL0 0x00000186 351 #define MSR_P6_EVNTSEL1 0x00000187 352 353 #define MSR_KNC_PERFCTR0 0x00000020 354 #define MSR_KNC_PERFCTR1 0x00000021 355 #define MSR_KNC_EVNTSEL0 0x00000028 356 #define MSR_KNC_EVNTSEL1 0x00000029 357 358 /* Alternative perfctr range with full access. */ 359 #define MSR_IA32_PMC0 0x000004c1 360 361 /* AMD64 MSRs. Not complete. See the architecture manual for a more 362 complete list. */ 363 364 #define MSR_AMD64_PATCH_LEVEL 0x0000008b 365 #define MSR_AMD64_TSC_RATIO 0xc0000104 366 #define MSR_AMD64_NB_CFG 0xc001001f 367 #define MSR_AMD64_PATCH_LOADER 0xc0010020 368 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 369 #define MSR_AMD64_OSVW_STATUS 0xc0010141 370 #define MSR_AMD64_LS_CFG 0xc0011020 371 #define MSR_AMD64_DC_CFG 0xc0011022 372 #define MSR_AMD64_BU_CFG2 0xc001102a 373 #define MSR_AMD64_IBSFETCHCTL 0xc0011030 374 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 375 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 376 #define MSR_AMD64_IBSFETCH_REG_COUNT 3 377 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 378 #define MSR_AMD64_IBSOPCTL 0xc0011033 379 #define MSR_AMD64_IBSOPRIP 0xc0011034 380 #define MSR_AMD64_IBSOPDATA 0xc0011035 381 #define MSR_AMD64_IBSOPDATA2 0xc0011036 382 #define MSR_AMD64_IBSOPDATA3 0xc0011037 383 #define MSR_AMD64_IBSDCLINAD 0xc0011038 384 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 385 #define MSR_AMD64_IBSOP_REG_COUNT 7 386 #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 387 #define MSR_AMD64_IBSCTL 0xc001103a 388 #define MSR_AMD64_IBSBRTARGET 0xc001103b 389 #define MSR_AMD64_IBSOPDATA4 0xc001103d 390 #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 391 #define MSR_AMD64_SEV 0xc0010131 392 #define MSR_AMD64_SEV_ENABLED_BIT 0 393 #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) 394 395 #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f 396 397 /* Fam 17h MSRs */ 398 #define MSR_F17H_IRPERF 0xc00000e9 399 400 /* Fam 16h MSRs */ 401 #define MSR_F16H_L2I_PERF_CTL 0xc0010230 402 #define MSR_F16H_L2I_PERF_CTR 0xc0010231 403 #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 404 #define MSR_F16H_DR2_ADDR_MASK 0xc001101a 405 #define MSR_F16H_DR3_ADDR_MASK 0xc001101b 406 #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 407 408 /* Fam 15h MSRs */ 409 #define MSR_F15H_PERF_CTL 0xc0010200 410 #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 411 #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 412 #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 413 #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 414 #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 415 #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 416 417 #define MSR_F15H_PERF_CTR 0xc0010201 418 #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 419 #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 420 #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 421 #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 422 #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 423 #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 424 425 #define MSR_F15H_NB_PERF_CTL 0xc0010240 426 #define MSR_F15H_NB_PERF_CTR 0xc0010241 427 #define MSR_F15H_PTSC 0xc0010280 428 #define MSR_F15H_IC_CFG 0xc0011021 429 #define MSR_F15H_EX_CFG 0xc001102c 430 431 /* Fam 10h MSRs */ 432 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 433 #define FAM10H_MMIO_CONF_ENABLE (1<<0) 434 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 435 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 436 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 437 #define FAM10H_MMIO_CONF_BASE_SHIFT 20 438 #define MSR_FAM10H_NODE_ID 0xc001100c 439 #define MSR_F10H_DECFG 0xc0011029 440 #define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1 441 #define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT) 442 443 /* K8 MSRs */ 444 #define MSR_K8_TOP_MEM1 0xc001001a 445 #define MSR_K8_TOP_MEM2 0xc001001d 446 #define MSR_K8_SYSCFG 0xc0010010 447 #define MSR_K8_SYSCFG_MEM_ENCRYPT_BIT 23 448 #define MSR_K8_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_K8_SYSCFG_MEM_ENCRYPT_BIT) 449 #define MSR_K8_INT_PENDING_MSG 0xc0010055 450 /* C1E active bits in int pending message */ 451 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 452 #define MSR_K8_TSEG_ADDR 0xc0010112 453 #define MSR_K8_TSEG_MASK 0xc0010113 454 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 455 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 456 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 457 458 /* K7 MSRs */ 459 #define MSR_K7_EVNTSEL0 0xc0010000 460 #define MSR_K7_PERFCTR0 0xc0010004 461 #define MSR_K7_EVNTSEL1 0xc0010001 462 #define MSR_K7_PERFCTR1 0xc0010005 463 #define MSR_K7_EVNTSEL2 0xc0010002 464 #define MSR_K7_PERFCTR2 0xc0010006 465 #define MSR_K7_EVNTSEL3 0xc0010003 466 #define MSR_K7_PERFCTR3 0xc0010007 467 #define MSR_K7_CLK_CTL 0xc001001b 468 #define MSR_K7_HWCR 0xc0010015 469 #define MSR_K7_HWCR_SMMLOCK_BIT 0 470 #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) 471 #define MSR_K7_FID_VID_CTL 0xc0010041 472 #define MSR_K7_FID_VID_STATUS 0xc0010042 473 474 /* K6 MSRs */ 475 #define MSR_K6_WHCR 0xc0000082 476 #define MSR_K6_UWCCR 0xc0000085 477 #define MSR_K6_EPMR 0xc0000086 478 #define MSR_K6_PSOR 0xc0000087 479 #define MSR_K6_PFIR 0xc0000088 480 481 /* Centaur-Hauls/IDT defined MSRs. */ 482 #define MSR_IDT_FCR1 0x00000107 483 #define MSR_IDT_FCR2 0x00000108 484 #define MSR_IDT_FCR3 0x00000109 485 #define MSR_IDT_FCR4 0x0000010a 486 487 #define MSR_IDT_MCR0 0x00000110 488 #define MSR_IDT_MCR1 0x00000111 489 #define MSR_IDT_MCR2 0x00000112 490 #define MSR_IDT_MCR3 0x00000113 491 #define MSR_IDT_MCR4 0x00000114 492 #define MSR_IDT_MCR5 0x00000115 493 #define MSR_IDT_MCR6 0x00000116 494 #define MSR_IDT_MCR7 0x00000117 495 #define MSR_IDT_MCR_CTRL 0x00000120 496 497 /* VIA Cyrix defined MSRs*/ 498 #define MSR_VIA_FCR 0x00001107 499 #define MSR_VIA_LONGHAUL 0x0000110a 500 #define MSR_VIA_RNG 0x0000110b 501 #define MSR_VIA_BCR2 0x00001147 502 503 /* Transmeta defined MSRs */ 504 #define MSR_TMTA_LONGRUN_CTRL 0x80868010 505 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 506 #define MSR_TMTA_LRTI_READOUT 0x80868018 507 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 508 509 /* Intel defined MSRs. */ 510 #define MSR_IA32_P5_MC_ADDR 0x00000000 511 #define MSR_IA32_P5_MC_TYPE 0x00000001 512 #define MSR_IA32_TSC 0x00000010 513 #define MSR_IA32_PLATFORM_ID 0x00000017 514 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 515 #define MSR_EBC_FREQUENCY_ID 0x0000002c 516 #define MSR_SMI_COUNT 0x00000034 517 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 518 #define MSR_IA32_TSC_ADJUST 0x0000003b 519 #define MSR_IA32_BNDCFGS 0x00000d90 520 521 #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 522 523 #define MSR_IA32_XSS 0x00000da0 524 525 #define FEATURE_CONTROL_LOCKED (1<<0) 526 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 527 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 528 #define FEATURE_CONTROL_LMCE (1<<20) 529 530 #define MSR_IA32_APICBASE 0x0000001b 531 #define MSR_IA32_APICBASE_BSP (1<<8) 532 #define MSR_IA32_APICBASE_ENABLE (1<<11) 533 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 534 535 #define MSR_IA32_TSCDEADLINE 0x000006e0 536 537 #define MSR_IA32_UCODE_WRITE 0x00000079 538 #define MSR_IA32_UCODE_REV 0x0000008b 539 540 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 541 #define MSR_IA32_SMBASE 0x0000009e 542 543 #define MSR_IA32_PERF_STATUS 0x00000198 544 #define MSR_IA32_PERF_CTL 0x00000199 545 #define INTEL_PERF_CTL_MASK 0xffff 546 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 547 #define MSR_AMD_PERF_STATUS 0xc0010063 548 #define MSR_AMD_PERF_CTL 0xc0010062 549 550 #define MSR_IA32_MPERF 0x000000e7 551 #define MSR_IA32_APERF 0x000000e8 552 553 #define MSR_IA32_THERM_CONTROL 0x0000019a 554 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 555 556 #define THERM_INT_HIGH_ENABLE (1 << 0) 557 #define THERM_INT_LOW_ENABLE (1 << 1) 558 #define THERM_INT_PLN_ENABLE (1 << 24) 559 560 #define MSR_IA32_THERM_STATUS 0x0000019c 561 562 #define THERM_STATUS_PROCHOT (1 << 0) 563 #define THERM_STATUS_POWER_LIMIT (1 << 10) 564 565 #define MSR_THERM2_CTL 0x0000019d 566 567 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 568 569 #define MSR_IA32_MISC_ENABLE 0x000001a0 570 571 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 572 573 #define MSR_MISC_FEATURE_CONTROL 0x000001a4 574 #define MSR_MISC_PWR_MGMT 0x000001aa 575 576 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 577 #define ENERGY_PERF_BIAS_PERFORMANCE 0 578 #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 579 #define ENERGY_PERF_BIAS_NORMAL 6 580 #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 581 #define ENERGY_PERF_BIAS_POWERSAVE 15 582 583 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 584 585 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 586 #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 587 588 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 589 590 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 591 #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 592 #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 593 594 /* Thermal Thresholds Support */ 595 #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 596 #define THERM_SHIFT_THRESHOLD0 8 597 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 598 #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 599 #define THERM_SHIFT_THRESHOLD1 16 600 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 601 #define THERM_STATUS_THRESHOLD0 (1 << 6) 602 #define THERM_LOG_THRESHOLD0 (1 << 7) 603 #define THERM_STATUS_THRESHOLD1 (1 << 8) 604 #define THERM_LOG_THRESHOLD1 (1 << 9) 605 606 /* MISC_ENABLE bits: architectural */ 607 #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 608 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 609 #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 610 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 611 #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 612 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 613 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 614 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 615 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 616 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 617 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 618 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 619 #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 620 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 621 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 622 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 623 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 624 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 625 #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 626 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 627 628 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 629 #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 630 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 631 #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 632 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 633 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 634 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 635 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 636 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 637 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 638 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 639 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 640 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 641 #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 642 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 643 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 644 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 645 #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 646 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 647 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 648 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 649 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 650 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 651 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 652 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 653 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 654 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 655 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 656 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 657 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 658 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 659 660 /* MISC_FEATURES_ENABLES non-architectural features */ 661 #define MSR_MISC_FEATURES_ENABLES 0x00000140 662 663 #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 664 #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) 665 #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 666 667 #define MSR_IA32_TSC_DEADLINE 0x000006E0 668 669 670 #define MSR_TSX_FORCE_ABORT 0x0000010F 671 672 #define MSR_TFA_RTM_FORCE_ABORT_BIT 0 673 #define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) 674 675 /* P4/Xeon+ specific */ 676 #define MSR_IA32_MCG_EAX 0x00000180 677 #define MSR_IA32_MCG_EBX 0x00000181 678 #define MSR_IA32_MCG_ECX 0x00000182 679 #define MSR_IA32_MCG_EDX 0x00000183 680 #define MSR_IA32_MCG_ESI 0x00000184 681 #define MSR_IA32_MCG_EDI 0x00000185 682 #define MSR_IA32_MCG_EBP 0x00000186 683 #define MSR_IA32_MCG_ESP 0x00000187 684 #define MSR_IA32_MCG_EFLAGS 0x00000188 685 #define MSR_IA32_MCG_EIP 0x00000189 686 #define MSR_IA32_MCG_RESERVED 0x0000018a 687 688 /* Pentium IV performance counter MSRs */ 689 #define MSR_P4_BPU_PERFCTR0 0x00000300 690 #define MSR_P4_BPU_PERFCTR1 0x00000301 691 #define MSR_P4_BPU_PERFCTR2 0x00000302 692 #define MSR_P4_BPU_PERFCTR3 0x00000303 693 #define MSR_P4_MS_PERFCTR0 0x00000304 694 #define MSR_P4_MS_PERFCTR1 0x00000305 695 #define MSR_P4_MS_PERFCTR2 0x00000306 696 #define MSR_P4_MS_PERFCTR3 0x00000307 697 #define MSR_P4_FLAME_PERFCTR0 0x00000308 698 #define MSR_P4_FLAME_PERFCTR1 0x00000309 699 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 700 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 701 #define MSR_P4_IQ_PERFCTR0 0x0000030c 702 #define MSR_P4_IQ_PERFCTR1 0x0000030d 703 #define MSR_P4_IQ_PERFCTR2 0x0000030e 704 #define MSR_P4_IQ_PERFCTR3 0x0000030f 705 #define MSR_P4_IQ_PERFCTR4 0x00000310 706 #define MSR_P4_IQ_PERFCTR5 0x00000311 707 #define MSR_P4_BPU_CCCR0 0x00000360 708 #define MSR_P4_BPU_CCCR1 0x00000361 709 #define MSR_P4_BPU_CCCR2 0x00000362 710 #define MSR_P4_BPU_CCCR3 0x00000363 711 #define MSR_P4_MS_CCCR0 0x00000364 712 #define MSR_P4_MS_CCCR1 0x00000365 713 #define MSR_P4_MS_CCCR2 0x00000366 714 #define MSR_P4_MS_CCCR3 0x00000367 715 #define MSR_P4_FLAME_CCCR0 0x00000368 716 #define MSR_P4_FLAME_CCCR1 0x00000369 717 #define MSR_P4_FLAME_CCCR2 0x0000036a 718 #define MSR_P4_FLAME_CCCR3 0x0000036b 719 #define MSR_P4_IQ_CCCR0 0x0000036c 720 #define MSR_P4_IQ_CCCR1 0x0000036d 721 #define MSR_P4_IQ_CCCR2 0x0000036e 722 #define MSR_P4_IQ_CCCR3 0x0000036f 723 #define MSR_P4_IQ_CCCR4 0x00000370 724 #define MSR_P4_IQ_CCCR5 0x00000371 725 #define MSR_P4_ALF_ESCR0 0x000003ca 726 #define MSR_P4_ALF_ESCR1 0x000003cb 727 #define MSR_P4_BPU_ESCR0 0x000003b2 728 #define MSR_P4_BPU_ESCR1 0x000003b3 729 #define MSR_P4_BSU_ESCR0 0x000003a0 730 #define MSR_P4_BSU_ESCR1 0x000003a1 731 #define MSR_P4_CRU_ESCR0 0x000003b8 732 #define MSR_P4_CRU_ESCR1 0x000003b9 733 #define MSR_P4_CRU_ESCR2 0x000003cc 734 #define MSR_P4_CRU_ESCR3 0x000003cd 735 #define MSR_P4_CRU_ESCR4 0x000003e0 736 #define MSR_P4_CRU_ESCR5 0x000003e1 737 #define MSR_P4_DAC_ESCR0 0x000003a8 738 #define MSR_P4_DAC_ESCR1 0x000003a9 739 #define MSR_P4_FIRM_ESCR0 0x000003a4 740 #define MSR_P4_FIRM_ESCR1 0x000003a5 741 #define MSR_P4_FLAME_ESCR0 0x000003a6 742 #define MSR_P4_FLAME_ESCR1 0x000003a7 743 #define MSR_P4_FSB_ESCR0 0x000003a2 744 #define MSR_P4_FSB_ESCR1 0x000003a3 745 #define MSR_P4_IQ_ESCR0 0x000003ba 746 #define MSR_P4_IQ_ESCR1 0x000003bb 747 #define MSR_P4_IS_ESCR0 0x000003b4 748 #define MSR_P4_IS_ESCR1 0x000003b5 749 #define MSR_P4_ITLB_ESCR0 0x000003b6 750 #define MSR_P4_ITLB_ESCR1 0x000003b7 751 #define MSR_P4_IX_ESCR0 0x000003c8 752 #define MSR_P4_IX_ESCR1 0x000003c9 753 #define MSR_P4_MOB_ESCR0 0x000003aa 754 #define MSR_P4_MOB_ESCR1 0x000003ab 755 #define MSR_P4_MS_ESCR0 0x000003c0 756 #define MSR_P4_MS_ESCR1 0x000003c1 757 #define MSR_P4_PMH_ESCR0 0x000003ac 758 #define MSR_P4_PMH_ESCR1 0x000003ad 759 #define MSR_P4_RAT_ESCR0 0x000003bc 760 #define MSR_P4_RAT_ESCR1 0x000003bd 761 #define MSR_P4_SAAT_ESCR0 0x000003ae 762 #define MSR_P4_SAAT_ESCR1 0x000003af 763 #define MSR_P4_SSU_ESCR0 0x000003be 764 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 765 766 #define MSR_P4_TBPU_ESCR0 0x000003c2 767 #define MSR_P4_TBPU_ESCR1 0x000003c3 768 #define MSR_P4_TC_ESCR0 0x000003c4 769 #define MSR_P4_TC_ESCR1 0x000003c5 770 #define MSR_P4_U2L_ESCR0 0x000003b0 771 #define MSR_P4_U2L_ESCR1 0x000003b1 772 773 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 774 775 /* Intel Core-based CPU performance counters */ 776 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 777 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 778 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 779 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 780 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 781 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 782 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 783 784 /* Geode defined MSRs */ 785 #define MSR_GEODE_BUSCONT_CONF0 0x00001900 786 787 /* Intel VT MSRs */ 788 #define MSR_IA32_VMX_BASIC 0x00000480 789 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 790 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 791 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 792 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 793 #define MSR_IA32_VMX_MISC 0x00000485 794 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 795 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 796 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 797 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 798 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 799 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 800 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 801 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 802 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 803 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 804 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 805 #define MSR_IA32_VMX_VMFUNC 0x00000491 806 807 /* VMX_BASIC bits and bitmasks */ 808 #define VMX_BASIC_VMCS_SIZE_SHIFT 32 809 #define VMX_BASIC_TRUE_CTLS (1ULL << 55) 810 #define VMX_BASIC_64 0x0001000000000000LLU 811 #define VMX_BASIC_MEM_TYPE_SHIFT 50 812 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 813 #define VMX_BASIC_MEM_TYPE_WB 6LLU 814 #define VMX_BASIC_INOUT 0x0040000000000000LLU 815 816 /* MSR_IA32_VMX_MISC bits */ 817 #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) 818 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 819 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 820 /* AMD-V MSRs */ 821 822 #define MSR_VM_CR 0xc0010114 823 #define MSR_VM_IGNNE 0xc0010115 824 #define MSR_VM_HSAVE_PA 0xc0010117 825 826 #endif /* _ASM_X86_MSR_INDEX_H */ 827