1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2b72e7464SBorislav Petkov #ifndef _ASM_X86_MSR_INDEX_H 3b72e7464SBorislav Petkov #define _ASM_X86_MSR_INDEX_H 4b72e7464SBorislav Petkov 5d8eabc37SThomas Gleixner #include <linux/bits.h> 6d8eabc37SThomas Gleixner 7053080a9SBorislav Petkov /* 8053080a9SBorislav Petkov * CPU model specific register (MSR) numbers. 9053080a9SBorislav Petkov * 10053080a9SBorislav Petkov * Do not add new entries to this file unless the definitions are shared 11053080a9SBorislav Petkov * between multiple compilation units. 12053080a9SBorislav Petkov */ 13b72e7464SBorislav Petkov 14b72e7464SBorislav Petkov /* x86-64 specific MSRs */ 15b72e7464SBorislav Petkov #define MSR_EFER 0xc0000080 /* extended feature register */ 16b72e7464SBorislav Petkov #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 17b72e7464SBorislav Petkov #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 18b72e7464SBorislav Petkov #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 19b72e7464SBorislav Petkov #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 20b72e7464SBorislav Petkov #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 21b72e7464SBorislav Petkov #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 22b72e7464SBorislav Petkov #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 23b72e7464SBorislav Petkov #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 24b72e7464SBorislav Petkov 25b72e7464SBorislav Petkov /* EFER bits: */ 26b72e7464SBorislav Petkov #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 27b72e7464SBorislav Petkov #define _EFER_LME 8 /* Long mode enable */ 28b72e7464SBorislav Petkov #define _EFER_LMA 10 /* Long mode active (read-only) */ 29b72e7464SBorislav Petkov #define _EFER_NX 11 /* No execute enable */ 30b72e7464SBorislav Petkov #define _EFER_SVME 12 /* Enable virtualization */ 31b72e7464SBorislav Petkov #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 32b72e7464SBorislav Petkov #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 33b72e7464SBorislav Petkov 34b72e7464SBorislav Petkov #define EFER_SCE (1<<_EFER_SCE) 35b72e7464SBorislav Petkov #define EFER_LME (1<<_EFER_LME) 36b72e7464SBorislav Petkov #define EFER_LMA (1<<_EFER_LMA) 37b72e7464SBorislav Petkov #define EFER_NX (1<<_EFER_NX) 38b72e7464SBorislav Petkov #define EFER_SVME (1<<_EFER_SVME) 39b72e7464SBorislav Petkov #define EFER_LMSLE (1<<_EFER_LMSLE) 40b72e7464SBorislav Petkov #define EFER_FFXSR (1<<_EFER_FFXSR) 41b72e7464SBorislav Petkov 42b72e7464SBorislav Petkov /* Intel MSRs. Some also available on other CPUs */ 433f5a7896STony Luck 446650cdd9SPeter Zijlstra (Intel) #define MSR_TEST_CTRL 0x00000033 456650cdd9SPeter Zijlstra (Intel) #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 466650cdd9SPeter Zijlstra (Intel) #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) 476650cdd9SPeter Zijlstra (Intel) 481e340c60SDavid Woodhouse #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 49d8eabc37SThomas Gleixner #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ 505bfbe3adSTim Chen #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ 51d8eabc37SThomas Gleixner #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ 529f65fb29SKonrad Rzeszutek Wilk #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ 53d8eabc37SThomas Gleixner #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ 541e340c60SDavid Woodhouse 551e340c60SDavid Woodhouse #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 56d8eabc37SThomas Gleixner #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ 571e340c60SDavid Woodhouse 583f5a7896STony Luck #define MSR_PPIN_CTL 0x0000004e 593f5a7896STony Luck #define MSR_PPIN 0x0000004f 603f5a7896STony Luck 61b72e7464SBorislav Petkov #define MSR_IA32_PERFCTR0 0x000000c1 62b72e7464SBorislav Petkov #define MSR_IA32_PERFCTR1 0x000000c2 63b72e7464SBorislav Petkov #define MSR_FSB_FREQ 0x000000cd 645369a21eSLen Brown #define MSR_PLATFORM_INFO 0x000000ce 6590218ac7SKyle Huey #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 6690218ac7SKyle Huey #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) 67b72e7464SBorislav Petkov 68bd688c69SFenghua Yu #define MSR_IA32_UMWAIT_CONTROL 0xe1 69bd688c69SFenghua Yu #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0) 70bd688c69SFenghua Yu #define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1) 71bd688c69SFenghua Yu /* 72bd688c69SFenghua Yu * The time field is bit[31:2], but representing a 32bit value with 73bd688c69SFenghua Yu * bit[1:0] zero. 74bd688c69SFenghua Yu */ 75bd688c69SFenghua Yu #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U) 76bd688c69SFenghua Yu 776650cdd9SPeter Zijlstra (Intel) /* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */ 786650cdd9SPeter Zijlstra (Intel) #define MSR_IA32_CORE_CAPS 0x000000cf 796650cdd9SPeter Zijlstra (Intel) #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5 806650cdd9SPeter Zijlstra (Intel) #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT) 816650cdd9SPeter Zijlstra (Intel) 8240496c8eSLen Brown #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 83b72e7464SBorislav Petkov #define NHM_C3_AUTO_DEMOTE (1UL << 25) 84b72e7464SBorislav Petkov #define NHM_C1_AUTO_DEMOTE (1UL << 26) 85b72e7464SBorislav Petkov #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 86a00072a2SMatt Turner #define SNB_C3_AUTO_UNDEMOTE (1UL << 27) 87a00072a2SMatt Turner #define SNB_C1_AUTO_UNDEMOTE (1UL << 28) 88b72e7464SBorislav Petkov 89b72e7464SBorislav Petkov #define MSR_MTRRcap 0x000000fe 901e340c60SDavid Woodhouse 911e340c60SDavid Woodhouse #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 92d8eabc37SThomas Gleixner #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ 93d8eabc37SThomas Gleixner #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ 94d8eabc37SThomas Gleixner #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ 95d8eabc37SThomas Gleixner #define ARCH_CAP_SSB_NO BIT(4) /* 9677243971SKonrad Rzeszutek Wilk * Not susceptible to Speculative Store Bypass 979f65fb29SKonrad Rzeszutek Wilk * attack, so no Speculative Store Bypass 989f65fb29SKonrad Rzeszutek Wilk * control required. 9977243971SKonrad Rzeszutek Wilk */ 100ed5194c2SAndi Kleen #define ARCH_CAP_MDS_NO BIT(5) /* 101ed5194c2SAndi Kleen * Not susceptible to 102ed5194c2SAndi Kleen * Microarchitectural Data 103ed5194c2SAndi Kleen * Sampling (MDS) vulnerabilities. 104ed5194c2SAndi Kleen */ 105db4d30fbSVineela Tummalapalli #define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* 106db4d30fbSVineela Tummalapalli * The processor is not susceptible to a 107db4d30fbSVineela Tummalapalli * machine check error due to modifying the 108db4d30fbSVineela Tummalapalli * code page size along with either the 109db4d30fbSVineela Tummalapalli * physical address or cache type 110db4d30fbSVineela Tummalapalli * without TLB invalidation. 111db4d30fbSVineela Tummalapalli */ 112c2955f27SPawan Gupta #define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ 1131b42f017SPawan Gupta #define ARCH_CAP_TAA_NO BIT(8) /* 1141b42f017SPawan Gupta * Not susceptible to 1151b42f017SPawan Gupta * TSX Async Abort (TAA) vulnerabilities. 1161b42f017SPawan Gupta */ 1171e340c60SDavid Woodhouse 1183fa045beSPaolo Bonzini #define MSR_IA32_FLUSH_CMD 0x0000010b 119d8eabc37SThomas Gleixner #define L1D_FLUSH BIT(0) /* 1203fa045beSPaolo Bonzini * Writeback and invalidate the 1213fa045beSPaolo Bonzini * L1 data cache. 1223fa045beSPaolo Bonzini */ 1233fa045beSPaolo Bonzini 124b72e7464SBorislav Petkov #define MSR_IA32_BBL_CR_CTL 0x00000119 125b72e7464SBorislav Petkov #define MSR_IA32_BBL_CR_CTL3 0x0000011e 126b72e7464SBorislav Petkov 127c2955f27SPawan Gupta #define MSR_IA32_TSX_CTRL 0x00000122 128c2955f27SPawan Gupta #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ 129c2955f27SPawan Gupta #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ 130c2955f27SPawan Gupta 1317e5b3c26SMark Gross /* SRBDS support */ 1327e5b3c26SMark Gross #define MSR_IA32_MCU_OPT_CTRL 0x00000123 1337e5b3c26SMark Gross #define RNGDS_MITG_DIS BIT(0) 1347e5b3c26SMark Gross 135b72e7464SBorislav Petkov #define MSR_IA32_SYSENTER_CS 0x00000174 136b72e7464SBorislav Petkov #define MSR_IA32_SYSENTER_ESP 0x00000175 137b72e7464SBorislav Petkov #define MSR_IA32_SYSENTER_EIP 0x00000176 138b72e7464SBorislav Petkov 139b72e7464SBorislav Petkov #define MSR_IA32_MCG_CAP 0x00000179 140b72e7464SBorislav Petkov #define MSR_IA32_MCG_STATUS 0x0000017a 141b72e7464SBorislav Petkov #define MSR_IA32_MCG_CTL 0x0000017b 14268299a42STony Luck #define MSR_ERROR_CONTROL 0x0000017f 143b72e7464SBorislav Petkov #define MSR_IA32_MCG_EXT_CTL 0x000004d0 144b72e7464SBorislav Petkov 145b72e7464SBorislav Petkov #define MSR_OFFCORE_RSP_0 0x000001a6 146b72e7464SBorislav Petkov #define MSR_OFFCORE_RSP_1 0x000001a7 147b72e7464SBorislav Petkov #define MSR_TURBO_RATIO_LIMIT 0x000001ad 148b72e7464SBorislav Petkov #define MSR_TURBO_RATIO_LIMIT1 0x000001ae 149b72e7464SBorislav Petkov #define MSR_TURBO_RATIO_LIMIT2 0x000001af 150b72e7464SBorislav Petkov 151b72e7464SBorislav Petkov #define MSR_LBR_SELECT 0x000001c8 152b72e7464SBorislav Petkov #define MSR_LBR_TOS 0x000001c9 153ed7bde7aSSrinivas Pandruvada 154ed7bde7aSSrinivas Pandruvada #define MSR_IA32_POWER_CTL 0x000001fc 155ed7bde7aSSrinivas Pandruvada #define MSR_IA32_POWER_CTL_BIT_EE 19 156ed7bde7aSSrinivas Pandruvada 157b72e7464SBorislav Petkov #define MSR_LBR_NHM_FROM 0x00000680 158b72e7464SBorislav Petkov #define MSR_LBR_NHM_TO 0x000006c0 159b72e7464SBorislav Petkov #define MSR_LBR_CORE_FROM 0x00000040 160b72e7464SBorislav Petkov #define MSR_LBR_CORE_TO 0x00000060 161b72e7464SBorislav Petkov 162b83ff1c8SAndi Kleen #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 163b83ff1c8SAndi Kleen #define LBR_INFO_MISPRED BIT_ULL(63) 164b83ff1c8SAndi Kleen #define LBR_INFO_IN_TX BIT_ULL(62) 165b83ff1c8SAndi Kleen #define LBR_INFO_ABORT BIT_ULL(61) 166d6a162a4SKan Liang #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60) 167b83ff1c8SAndi Kleen #define LBR_INFO_CYCLES 0xffff 168d6a162a4SKan Liang #define LBR_INFO_BR_TYPE_OFFSET 56 169d6a162a4SKan Liang #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) 170d6a162a4SKan Liang 171d6a162a4SKan Liang #define MSR_ARCH_LBR_CTL 0x000014ce 172d6a162a4SKan Liang #define ARCH_LBR_CTL_LBREN BIT(0) 173d6a162a4SKan Liang #define ARCH_LBR_CTL_CPL_OFFSET 1 174d6a162a4SKan Liang #define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET) 175d6a162a4SKan Liang #define ARCH_LBR_CTL_STACK_OFFSET 3 176d6a162a4SKan Liang #define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET) 177d6a162a4SKan Liang #define ARCH_LBR_CTL_FILTER_OFFSET 16 178d6a162a4SKan Liang #define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET) 179d6a162a4SKan Liang #define MSR_ARCH_LBR_DEPTH 0x000014cf 180d6a162a4SKan Liang #define MSR_ARCH_LBR_FROM_0 0x00001500 181d6a162a4SKan Liang #define MSR_ARCH_LBR_TO_0 0x00001600 182d6a162a4SKan Liang #define MSR_ARCH_LBR_INFO_0 0x00001200 183b83ff1c8SAndi Kleen 184b72e7464SBorislav Petkov #define MSR_IA32_PEBS_ENABLE 0x000003f1 185c22497f5SKan Liang #define MSR_PEBS_DATA_CFG 0x000003f2 186b72e7464SBorislav Petkov #define MSR_IA32_DS_AREA 0x00000600 187b72e7464SBorislav Petkov #define MSR_IA32_PERF_CAPABILITIES 0x00000345 188d0946a88SKan Liang #define PERF_CAP_METRICS_IDX 15 189d0946a88SKan Liang #define PERF_CAP_PT_IDX 16 190d0946a88SKan Liang 191b72e7464SBorislav Petkov #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 192b72e7464SBorislav Petkov 193b72e7464SBorislav Petkov #define MSR_IA32_RTIT_CTL 0x00000570 194887eda13SChao Peng #define RTIT_CTL_TRACEEN BIT(0) 195887eda13SChao Peng #define RTIT_CTL_CYCLEACC BIT(1) 196887eda13SChao Peng #define RTIT_CTL_OS BIT(2) 197887eda13SChao Peng #define RTIT_CTL_USR BIT(3) 198887eda13SChao Peng #define RTIT_CTL_PWR_EVT_EN BIT(4) 199887eda13SChao Peng #define RTIT_CTL_FUP_ON_PTW BIT(5) 20069843a91SLuwei Kang #define RTIT_CTL_FABRIC_EN BIT(6) 201887eda13SChao Peng #define RTIT_CTL_CR3EN BIT(7) 202887eda13SChao Peng #define RTIT_CTL_TOPA BIT(8) 203887eda13SChao Peng #define RTIT_CTL_MTC_EN BIT(9) 204887eda13SChao Peng #define RTIT_CTL_TSC_EN BIT(10) 205887eda13SChao Peng #define RTIT_CTL_DISRETC BIT(11) 206887eda13SChao Peng #define RTIT_CTL_PTW_EN BIT(12) 207887eda13SChao Peng #define RTIT_CTL_BRANCH_EN BIT(13) 20828c24dedSAlexander Shishkin #define RTIT_CTL_EVENT_EN BIT(31) 209161a9a33SAlexander Shishkin #define RTIT_CTL_NOTNT BIT_ULL(55) 210887eda13SChao Peng #define RTIT_CTL_MTC_RANGE_OFFSET 14 211887eda13SChao Peng #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 212887eda13SChao Peng #define RTIT_CTL_CYC_THRESH_OFFSET 19 213887eda13SChao Peng #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 214887eda13SChao Peng #define RTIT_CTL_PSB_FREQ_OFFSET 24 215887eda13SChao Peng #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 216887eda13SChao Peng #define RTIT_CTL_ADDR0_OFFSET 32 217887eda13SChao Peng #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) 218887eda13SChao Peng #define RTIT_CTL_ADDR1_OFFSET 36 219887eda13SChao Peng #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) 220887eda13SChao Peng #define RTIT_CTL_ADDR2_OFFSET 40 221887eda13SChao Peng #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) 222887eda13SChao Peng #define RTIT_CTL_ADDR3_OFFSET 44 223887eda13SChao Peng #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) 224b72e7464SBorislav Petkov #define MSR_IA32_RTIT_STATUS 0x00000571 225887eda13SChao Peng #define RTIT_STATUS_FILTEREN BIT(0) 226887eda13SChao Peng #define RTIT_STATUS_CONTEXTEN BIT(1) 227887eda13SChao Peng #define RTIT_STATUS_TRIGGEREN BIT(2) 228887eda13SChao Peng #define RTIT_STATUS_BUFFOVF BIT(3) 229887eda13SChao Peng #define RTIT_STATUS_ERROR BIT(4) 230887eda13SChao Peng #define RTIT_STATUS_STOPPED BIT(5) 23169843a91SLuwei Kang #define RTIT_STATUS_BYTECNT_OFFSET 32 23269843a91SLuwei Kang #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) 233f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR0_A 0x00000580 234f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR0_B 0x00000581 235f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR1_A 0x00000582 236f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR1_B 0x00000583 237f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR2_A 0x00000584 238f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR2_B 0x00000585 239f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR3_A 0x00000586 240f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR3_B 0x00000587 241b72e7464SBorislav Petkov #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 242b72e7464SBorislav Petkov #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 243b72e7464SBorislav Petkov #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 244b72e7464SBorislav Petkov 245b72e7464SBorislav Petkov #define MSR_MTRRfix64K_00000 0x00000250 246b72e7464SBorislav Petkov #define MSR_MTRRfix16K_80000 0x00000258 247b72e7464SBorislav Petkov #define MSR_MTRRfix16K_A0000 0x00000259 248b72e7464SBorislav Petkov #define MSR_MTRRfix4K_C0000 0x00000268 249b72e7464SBorislav Petkov #define MSR_MTRRfix4K_C8000 0x00000269 250b72e7464SBorislav Petkov #define MSR_MTRRfix4K_D0000 0x0000026a 251b72e7464SBorislav Petkov #define MSR_MTRRfix4K_D8000 0x0000026b 252b72e7464SBorislav Petkov #define MSR_MTRRfix4K_E0000 0x0000026c 253b72e7464SBorislav Petkov #define MSR_MTRRfix4K_E8000 0x0000026d 254b72e7464SBorislav Petkov #define MSR_MTRRfix4K_F0000 0x0000026e 255b72e7464SBorislav Petkov #define MSR_MTRRfix4K_F8000 0x0000026f 256b72e7464SBorislav Petkov #define MSR_MTRRdefType 0x000002ff 257b72e7464SBorislav Petkov 258b72e7464SBorislav Petkov #define MSR_IA32_CR_PAT 0x00000277 259b72e7464SBorislav Petkov 260b72e7464SBorislav Petkov #define MSR_IA32_DEBUGCTLMSR 0x000001d9 261b72e7464SBorislav Petkov #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 262b72e7464SBorislav Petkov #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 263b72e7464SBorislav Petkov #define MSR_IA32_LASTINTFROMIP 0x000001dd 264b72e7464SBorislav Petkov #define MSR_IA32_LASTINTTOIP 0x000001de 265b72e7464SBorislav Petkov 266f0f2f9feSFenghua Yu #define MSR_IA32_PASID 0x00000d93 267f0f2f9feSFenghua Yu #define MSR_IA32_PASID_VALID BIT_ULL(31) 268f0f2f9feSFenghua Yu 269b72e7464SBorislav Petkov /* DEBUGCTLMSR bits (others vary by model): */ 270b72e7464SBorislav Petkov #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 271b9894a2fSKyle Huey #define DEBUGCTLMSR_BTF_SHIFT 1 272b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 273ebb1064eSFenghua Yu #define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2) 274b72e7464SBorislav Petkov #define DEBUGCTLMSR_TR (1UL << 6) 275b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTS (1UL << 7) 276b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTINT (1UL << 8) 277b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 278b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 279b72e7464SBorislav Petkov #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 280af3bdb99SAndi Kleen #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) 2816089327fSKan Liang #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 2826089327fSKan Liang #define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 283b72e7464SBorislav Petkov 284d0dc8494SAndi Kleen #define MSR_PEBS_FRONTEND 0x000003f7 285d0dc8494SAndi Kleen 286b72e7464SBorislav Petkov #define MSR_IA32_MC0_CTL 0x00000400 287b72e7464SBorislav Petkov #define MSR_IA32_MC0_STATUS 0x00000401 288b72e7464SBorislav Petkov #define MSR_IA32_MC0_ADDR 0x00000402 289b72e7464SBorislav Petkov #define MSR_IA32_MC0_MISC 0x00000403 290b72e7464SBorislav Petkov 291b72e7464SBorislav Petkov /* C-state Residency Counters */ 292b72e7464SBorislav Petkov #define MSR_PKG_C3_RESIDENCY 0x000003f8 293b72e7464SBorislav Petkov #define MSR_PKG_C6_RESIDENCY 0x000003f9 2940539ba11SLen Brown #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 295b72e7464SBorislav Petkov #define MSR_PKG_C7_RESIDENCY 0x000003fa 296b72e7464SBorislav Petkov #define MSR_CORE_C3_RESIDENCY 0x000003fc 297b72e7464SBorislav Petkov #define MSR_CORE_C6_RESIDENCY 0x000003fd 298b72e7464SBorislav Petkov #define MSR_CORE_C7_RESIDENCY 0x000003fe 299b72e7464SBorislav Petkov #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 300b72e7464SBorislav Petkov #define MSR_PKG_C2_RESIDENCY 0x0000060d 301b72e7464SBorislav Petkov #define MSR_PKG_C8_RESIDENCY 0x00000630 302b72e7464SBorislav Petkov #define MSR_PKG_C9_RESIDENCY 0x00000631 303b72e7464SBorislav Petkov #define MSR_PKG_C10_RESIDENCY 0x00000632 304b72e7464SBorislav Petkov 3055a63426eSLen Brown /* Interrupt Response Limit */ 3065a63426eSLen Brown #define MSR_PKGC3_IRTL 0x0000060a 3075a63426eSLen Brown #define MSR_PKGC6_IRTL 0x0000060b 3085a63426eSLen Brown #define MSR_PKGC7_IRTL 0x0000060c 3095a63426eSLen Brown #define MSR_PKGC8_IRTL 0x00000633 3105a63426eSLen Brown #define MSR_PKGC9_IRTL 0x00000634 3115a63426eSLen Brown #define MSR_PKGC10_IRTL 0x00000635 3125a63426eSLen Brown 313b72e7464SBorislav Petkov /* Run Time Average Power Limiting (RAPL) Interface */ 314b72e7464SBorislav Petkov 315b72e7464SBorislav Petkov #define MSR_RAPL_POWER_UNIT 0x00000606 316b72e7464SBorislav Petkov 317b72e7464SBorislav Petkov #define MSR_PKG_POWER_LIMIT 0x00000610 318b72e7464SBorislav Petkov #define MSR_PKG_ENERGY_STATUS 0x00000611 319b72e7464SBorislav Petkov #define MSR_PKG_PERF_STATUS 0x00000613 320b72e7464SBorislav Petkov #define MSR_PKG_POWER_INFO 0x00000614 321b72e7464SBorislav Petkov 322b72e7464SBorislav Petkov #define MSR_DRAM_POWER_LIMIT 0x00000618 323b72e7464SBorislav Petkov #define MSR_DRAM_ENERGY_STATUS 0x00000619 324b72e7464SBorislav Petkov #define MSR_DRAM_PERF_STATUS 0x0000061b 325b72e7464SBorislav Petkov #define MSR_DRAM_POWER_INFO 0x0000061c 326b72e7464SBorislav Petkov 327b72e7464SBorislav Petkov #define MSR_PP0_POWER_LIMIT 0x00000638 328b72e7464SBorislav Petkov #define MSR_PP0_ENERGY_STATUS 0x00000639 329b72e7464SBorislav Petkov #define MSR_PP0_POLICY 0x0000063a 330b72e7464SBorislav Petkov #define MSR_PP0_PERF_STATUS 0x0000063b 331b72e7464SBorislav Petkov 332b72e7464SBorislav Petkov #define MSR_PP1_POWER_LIMIT 0x00000640 333b72e7464SBorislav Petkov #define MSR_PP1_ENERGY_STATUS 0x00000641 334b72e7464SBorislav Petkov #define MSR_PP1_POLICY 0x00000642 335b72e7464SBorislav Petkov 3365cde2653SStephane Eranian #define MSR_AMD_RAPL_POWER_UNIT 0xc0010299 33743756a29SVictor Ding #define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a 338298ed2b3SVictor Ding #define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b 3395cde2653SStephane Eranian 3404a6772f5SVladimir Zapolskiy /* Config TDP MSRs */ 34182bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_NOMINAL 0x00000648 34282bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 34382bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 34482bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_CONTROL 0x0000064B 34582bb70c5SRafael J. Wysocki #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 34682bb70c5SRafael J. Wysocki 347dcee75b3SSrinivas Pandruvada #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 348dcee75b3SSrinivas Pandruvada 349b72e7464SBorislav Petkov #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 350b72e7464SBorislav Petkov #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 351b72e7464SBorislav Petkov #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 352b72e7464SBorislav Petkov #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 353b72e7464SBorislav Petkov 354b72e7464SBorislav Petkov #define MSR_CORE_C1_RES 0x00000660 3550539ba11SLen Brown #define MSR_MODULE_C6_RES_MS 0x00000664 356b72e7464SBorislav Petkov 357b72e7464SBorislav Petkov #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 358b72e7464SBorislav Petkov #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 359b72e7464SBorislav Petkov 3608a34fd02SLen Brown #define MSR_ATOM_CORE_RATIOS 0x0000066a 3618a34fd02SLen Brown #define MSR_ATOM_CORE_VIDS 0x0000066b 3628a34fd02SLen Brown #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 3638a34fd02SLen Brown #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 3648a34fd02SLen Brown 365b72e7464SBorislav Petkov #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 366b72e7464SBorislav Petkov #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 367b72e7464SBorislav Petkov #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 368b72e7464SBorislav Petkov 369991625f3SPeter Zijlstra /* Control-flow Enforcement Technology MSRs */ 370991625f3SPeter Zijlstra #define MSR_IA32_U_CET 0x000006a0 /* user mode cet */ 371991625f3SPeter Zijlstra #define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */ 372991625f3SPeter Zijlstra #define CET_SHSTK_EN BIT_ULL(0) 373991625f3SPeter Zijlstra #define CET_WRSS_EN BIT_ULL(1) 374991625f3SPeter Zijlstra #define CET_ENDBR_EN BIT_ULL(2) 375991625f3SPeter Zijlstra #define CET_LEG_IW_EN BIT_ULL(3) 376991625f3SPeter Zijlstra #define CET_NO_TRACK_EN BIT_ULL(4) 377991625f3SPeter Zijlstra #define CET_SUPPRESS_DISABLE BIT_ULL(5) 378991625f3SPeter Zijlstra #define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9)) 379991625f3SPeter Zijlstra #define CET_SUPPRESS BIT_ULL(10) 380991625f3SPeter Zijlstra #define CET_WAIT_ENDBR BIT_ULL(11) 381991625f3SPeter Zijlstra 382991625f3SPeter Zijlstra #define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */ 383991625f3SPeter Zijlstra #define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */ 384991625f3SPeter Zijlstra #define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */ 385991625f3SPeter Zijlstra #define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */ 386991625f3SPeter Zijlstra #define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */ 387991625f3SPeter Zijlstra 388b72e7464SBorislav Petkov /* Hardware P state interface */ 389b72e7464SBorislav Petkov #define MSR_PPERF 0x0000064e 390b72e7464SBorislav Petkov #define MSR_PERF_LIMIT_REASONS 0x0000064f 391b72e7464SBorislav Petkov #define MSR_PM_ENABLE 0x00000770 392b72e7464SBorislav Petkov #define MSR_HWP_CAPABILITIES 0x00000771 393b72e7464SBorislav Petkov #define MSR_HWP_REQUEST_PKG 0x00000772 394b72e7464SBorislav Petkov #define MSR_HWP_INTERRUPT 0x00000773 395b72e7464SBorislav Petkov #define MSR_HWP_REQUEST 0x00000774 396b72e7464SBorislav Petkov #define MSR_HWP_STATUS 0x00000777 397b72e7464SBorislav Petkov 398b72e7464SBorislav Petkov /* CPUID.6.EAX */ 399b72e7464SBorislav Petkov #define HWP_BASE_BIT (1<<7) 400b72e7464SBorislav Petkov #define HWP_NOTIFICATIONS_BIT (1<<8) 401b72e7464SBorislav Petkov #define HWP_ACTIVITY_WINDOW_BIT (1<<9) 402b72e7464SBorislav Petkov #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 403b72e7464SBorislav Petkov #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 404b72e7464SBorislav Petkov 405b72e7464SBorislav Petkov /* IA32_HWP_CAPABILITIES */ 406670e27d8SLen Brown #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 407670e27d8SLen Brown #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 408670e27d8SLen Brown #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 409670e27d8SLen Brown #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 410b72e7464SBorislav Petkov 411b72e7464SBorislav Petkov /* IA32_HWP_REQUEST */ 412b72e7464SBorislav Petkov #define HWP_MIN_PERF(x) (x & 0xff) 413b72e7464SBorislav Petkov #define HWP_MAX_PERF(x) ((x & 0xff) << 8) 414b72e7464SBorislav Petkov #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 4152fc49cb0SLen Brown #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) 4168d84e906SLen Brown #define HWP_EPP_PERFORMANCE 0x00 4178d84e906SLen Brown #define HWP_EPP_BALANCE_PERFORMANCE 0x80 4188d84e906SLen Brown #define HWP_EPP_BALANCE_POWERSAVE 0xC0 4198d84e906SLen Brown #define HWP_EPP_POWERSAVE 0xFF 4202fc49cb0SLen Brown #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) 4212fc49cb0SLen Brown #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) 422b72e7464SBorislav Petkov 423b72e7464SBorislav Petkov /* IA32_HWP_STATUS */ 424b72e7464SBorislav Petkov #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 425b72e7464SBorislav Petkov #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 426b72e7464SBorislav Petkov 427b72e7464SBorislav Petkov /* IA32_HWP_INTERRUPT */ 428b72e7464SBorislav Petkov #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 429b72e7464SBorislav Petkov #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 430b72e7464SBorislav Petkov 431b72e7464SBorislav Petkov #define MSR_AMD64_MC0_MASK 0xc0010044 432b72e7464SBorislav Petkov 433b72e7464SBorislav Petkov #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 434b72e7464SBorislav Petkov #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 435b72e7464SBorislav Petkov #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 436b72e7464SBorislav Petkov #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 437b72e7464SBorislav Petkov 438b72e7464SBorislav Petkov #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 439b72e7464SBorislav Petkov 440b72e7464SBorislav Petkov /* These are consecutive and not in the normal 4er MCE bank block */ 441b72e7464SBorislav Petkov #define MSR_IA32_MC0_CTL2 0x00000280 442b72e7464SBorislav Petkov #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 443b72e7464SBorislav Petkov 444b72e7464SBorislav Petkov #define MSR_P6_PERFCTR0 0x000000c1 445b72e7464SBorislav Petkov #define MSR_P6_PERFCTR1 0x000000c2 446b72e7464SBorislav Petkov #define MSR_P6_EVNTSEL0 0x00000186 447b72e7464SBorislav Petkov #define MSR_P6_EVNTSEL1 0x00000187 448b72e7464SBorislav Petkov 449b72e7464SBorislav Petkov #define MSR_KNC_PERFCTR0 0x00000020 450b72e7464SBorislav Petkov #define MSR_KNC_PERFCTR1 0x00000021 451b72e7464SBorislav Petkov #define MSR_KNC_EVNTSEL0 0x00000028 452b72e7464SBorislav Petkov #define MSR_KNC_EVNTSEL1 0x00000029 453b72e7464SBorislav Petkov 454b72e7464SBorislav Petkov /* Alternative perfctr range with full access. */ 455b72e7464SBorislav Petkov #define MSR_IA32_PMC0 0x000004c1 456b72e7464SBorislav Petkov 45742880f72SAlexander Shishkin /* Auto-reload via MSR instead of DS area */ 45842880f72SAlexander Shishkin #define MSR_RELOAD_PMC0 0x000014c1 45942880f72SAlexander Shishkin #define MSR_RELOAD_FIXED_CTR0 0x00001309 46042880f72SAlexander Shishkin 461342061c5SBorislav Petkov /* 462342061c5SBorislav Petkov * AMD64 MSRs. Not complete. See the architecture manual for a more 463342061c5SBorislav Petkov * complete list. 464342061c5SBorislav Petkov */ 465b72e7464SBorislav Petkov #define MSR_AMD64_PATCH_LEVEL 0x0000008b 466b72e7464SBorislav Petkov #define MSR_AMD64_TSC_RATIO 0xc0000104 467b72e7464SBorislav Petkov #define MSR_AMD64_NB_CFG 0xc001001f 468b72e7464SBorislav Petkov #define MSR_AMD64_PATCH_LOADER 0xc0010020 469342061c5SBorislav Petkov #define MSR_AMD_PERF_CTL 0xc0010062 470342061c5SBorislav Petkov #define MSR_AMD_PERF_STATUS 0xc0010063 471342061c5SBorislav Petkov #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 472b72e7464SBorislav Petkov #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 473b72e7464SBorislav Petkov #define MSR_AMD64_OSVW_STATUS 0xc0010141 4744e3f77d8SJan Beulich #define MSR_AMD_PPIN_CTL 0xc00102f0 4754e3f77d8SJan Beulich #define MSR_AMD_PPIN 0xc00102f1 4761068ed45SBorislav Petkov #define MSR_AMD64_CPUID_FN_1 0xc0011004 477b72e7464SBorislav Petkov #define MSR_AMD64_LS_CFG 0xc0011020 478b72e7464SBorislav Petkov #define MSR_AMD64_DC_CFG 0xc0011022 479b72e7464SBorislav Petkov #define MSR_AMD64_BU_CFG2 0xc001102a 480b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCHCTL 0xc0011030 481b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 482b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 483b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCH_REG_COUNT 3 484b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 485b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPCTL 0xc0011033 486b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPRIP 0xc0011034 487b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA 0xc0011035 488b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA2 0xc0011036 489b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA3 0xc0011037 490b72e7464SBorislav Petkov #define MSR_AMD64_IBSDCLINAD 0xc0011038 491b72e7464SBorislav Petkov #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 492b72e7464SBorislav Petkov #define MSR_AMD64_IBSOP_REG_COUNT 7 493b72e7464SBorislav Petkov #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 494b72e7464SBorislav Petkov #define MSR_AMD64_IBSCTL 0xc001103a 495b72e7464SBorislav Petkov #define MSR_AMD64_IBSBRTARGET 0xc001103b 49636e1be8aSKim Phillips #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c 497b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA4 0xc001103d 498b72e7464SBorislav Petkov #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 49939150352SMaxim Levitsky #define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b 50069372cf0STom Lendacky #define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e 50129dcc60fSJoerg Roedel #define MSR_AMD64_SEV_ES_GHCB 0xc0010130 5021958b5fcSTom Lendacky #define MSR_AMD64_SEV 0xc0010131 5031958b5fcSTom Lendacky #define MSR_AMD64_SEV_ENABLED_BIT 0 504b57de6cdSJoerg Roedel #define MSR_AMD64_SEV_ES_ENABLED_BIT 1 505*f742b90eSBrijesh Singh #define MSR_AMD64_SEV_SNP_ENABLED_BIT 2 5061958b5fcSTom Lendacky #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) 507b57de6cdSJoerg Roedel #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) 508*f742b90eSBrijesh Singh #define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) 509b72e7464SBorislav Petkov 51011fb0683STom Lendacky #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f 51111fb0683STom Lendacky 51289aa94b4SHuang Rui /* AMD Collaborative Processor Performance Control MSRs */ 51389aa94b4SHuang Rui #define MSR_AMD_CPPC_CAP1 0xc00102b0 51489aa94b4SHuang Rui #define MSR_AMD_CPPC_ENABLE 0xc00102b1 51589aa94b4SHuang Rui #define MSR_AMD_CPPC_CAP2 0xc00102b2 51689aa94b4SHuang Rui #define MSR_AMD_CPPC_REQ 0xc00102b3 51789aa94b4SHuang Rui #define MSR_AMD_CPPC_STATUS 0xc00102b4 51889aa94b4SHuang Rui 51989aa94b4SHuang Rui #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) 52089aa94b4SHuang Rui #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) 52189aa94b4SHuang Rui #define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff) 52289aa94b4SHuang Rui #define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff) 52389aa94b4SHuang Rui 52489aa94b4SHuang Rui #define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0) 52589aa94b4SHuang Rui #define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) 52689aa94b4SHuang Rui #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) 52789aa94b4SHuang Rui #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) 52889aa94b4SHuang Rui 529aaf24884SHuang Rui /* Fam 17h MSRs */ 530aaf24884SHuang Rui #define MSR_F17H_IRPERF 0xc00000e9 531aaf24884SHuang Rui 532b72e7464SBorislav Petkov /* Fam 16h MSRs */ 533b72e7464SBorislav Petkov #define MSR_F16H_L2I_PERF_CTL 0xc0010230 534b72e7464SBorislav Petkov #define MSR_F16H_L2I_PERF_CTR 0xc0010231 535b72e7464SBorislav Petkov #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 536b72e7464SBorislav Petkov #define MSR_F16H_DR2_ADDR_MASK 0xc001101a 537b72e7464SBorislav Petkov #define MSR_F16H_DR3_ADDR_MASK 0xc001101b 538b72e7464SBorislav Petkov #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 539b72e7464SBorislav Petkov 540b72e7464SBorislav Petkov /* Fam 15h MSRs */ 54199e40204SBorislav Petkov #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a 54299e40204SBorislav Petkov #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b 543b72e7464SBorislav Petkov #define MSR_F15H_PERF_CTL 0xc0010200 544e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 545e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 546e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 547e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 548e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 549e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 550e84b7119SJanakarajan Natarajan 551b72e7464SBorislav Petkov #define MSR_F15H_PERF_CTR 0xc0010201 552e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 553e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 554e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 555e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 556e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 557e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 558e84b7119SJanakarajan Natarajan 559b72e7464SBorislav Petkov #define MSR_F15H_NB_PERF_CTL 0xc0010240 560b72e7464SBorislav Petkov #define MSR_F15H_NB_PERF_CTR 0xc0010241 5618a224261SHuang Rui #define MSR_F15H_PTSC 0xc0010280 562ae8b7875SBorislav Petkov #define MSR_F15H_IC_CFG 0xc0011021 5630e1b869fSEduardo Habkost #define MSR_F15H_EX_CFG 0xc001102c 564b72e7464SBorislav Petkov 565b72e7464SBorislav Petkov /* Fam 10h MSRs */ 566b72e7464SBorislav Petkov #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 567b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_ENABLE (1<<0) 568b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 569b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 570b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 571b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BASE_SHIFT 20 572b72e7464SBorislav Petkov #define MSR_FAM10H_NODE_ID 0xc001100c 573e4d0e84eSTom Lendacky #define MSR_F10H_DECFG 0xc0011029 574e4d0e84eSTom Lendacky #define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1 5759c6a73c7STom Lendacky #define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT) 576b72e7464SBorislav Petkov 577b72e7464SBorislav Petkov /* K8 MSRs */ 578b72e7464SBorislav Petkov #define MSR_K8_TOP_MEM1 0xc001001a 579b72e7464SBorislav Petkov #define MSR_K8_TOP_MEM2 0xc001001d 580059e5c32SBrijesh Singh #define MSR_AMD64_SYSCFG 0xc0010010 581059e5c32SBrijesh Singh #define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23 582059e5c32SBrijesh Singh #define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT) 583b72e7464SBorislav Petkov #define MSR_K8_INT_PENDING_MSG 0xc0010055 584b72e7464SBorislav Petkov /* C1E active bits in int pending message */ 585b72e7464SBorislav Petkov #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 586b72e7464SBorislav Petkov #define MSR_K8_TSEG_ADDR 0xc0010112 5873afb1121SPaolo Bonzini #define MSR_K8_TSEG_MASK 0xc0010113 588b72e7464SBorislav Petkov #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 589b72e7464SBorislav Petkov #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 590b72e7464SBorislav Petkov #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 591b72e7464SBorislav Petkov 592b72e7464SBorislav Petkov /* K7 MSRs */ 593b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL0 0xc0010000 594b72e7464SBorislav Petkov #define MSR_K7_PERFCTR0 0xc0010004 595b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL1 0xc0010001 596b72e7464SBorislav Petkov #define MSR_K7_PERFCTR1 0xc0010005 597b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL2 0xc0010002 598b72e7464SBorislav Petkov #define MSR_K7_PERFCTR2 0xc0010006 599b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL3 0xc0010003 600b72e7464SBorislav Petkov #define MSR_K7_PERFCTR3 0xc0010007 601b72e7464SBorislav Petkov #define MSR_K7_CLK_CTL 0xc001001b 602b72e7464SBorislav Petkov #define MSR_K7_HWCR 0xc0010015 60318c71ce9STom Lendacky #define MSR_K7_HWCR_SMMLOCK_BIT 0 60418c71ce9STom Lendacky #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) 60521b5ee59SKim Phillips #define MSR_K7_HWCR_IRPERF_EN_BIT 30 60621b5ee59SKim Phillips #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) 607b72e7464SBorislav Petkov #define MSR_K7_FID_VID_CTL 0xc0010041 608b72e7464SBorislav Petkov #define MSR_K7_FID_VID_STATUS 0xc0010042 609b72e7464SBorislav Petkov 610b72e7464SBorislav Petkov /* K6 MSRs */ 611b72e7464SBorislav Petkov #define MSR_K6_WHCR 0xc0000082 612b72e7464SBorislav Petkov #define MSR_K6_UWCCR 0xc0000085 613b72e7464SBorislav Petkov #define MSR_K6_EPMR 0xc0000086 614b72e7464SBorislav Petkov #define MSR_K6_PSOR 0xc0000087 615b72e7464SBorislav Petkov #define MSR_K6_PFIR 0xc0000088 616b72e7464SBorislav Petkov 617b72e7464SBorislav Petkov /* Centaur-Hauls/IDT defined MSRs. */ 618b72e7464SBorislav Petkov #define MSR_IDT_FCR1 0x00000107 619b72e7464SBorislav Petkov #define MSR_IDT_FCR2 0x00000108 620b72e7464SBorislav Petkov #define MSR_IDT_FCR3 0x00000109 621b72e7464SBorislav Petkov #define MSR_IDT_FCR4 0x0000010a 622b72e7464SBorislav Petkov 623b72e7464SBorislav Petkov #define MSR_IDT_MCR0 0x00000110 624b72e7464SBorislav Petkov #define MSR_IDT_MCR1 0x00000111 625b72e7464SBorislav Petkov #define MSR_IDT_MCR2 0x00000112 626b72e7464SBorislav Petkov #define MSR_IDT_MCR3 0x00000113 627b72e7464SBorislav Petkov #define MSR_IDT_MCR4 0x00000114 628b72e7464SBorislav Petkov #define MSR_IDT_MCR5 0x00000115 629b72e7464SBorislav Petkov #define MSR_IDT_MCR6 0x00000116 630b72e7464SBorislav Petkov #define MSR_IDT_MCR7 0x00000117 631b72e7464SBorislav Petkov #define MSR_IDT_MCR_CTRL 0x00000120 632b72e7464SBorislav Petkov 633b72e7464SBorislav Petkov /* VIA Cyrix defined MSRs*/ 634b72e7464SBorislav Petkov #define MSR_VIA_FCR 0x00001107 635b72e7464SBorislav Petkov #define MSR_VIA_LONGHAUL 0x0000110a 636b72e7464SBorislav Petkov #define MSR_VIA_RNG 0x0000110b 637b72e7464SBorislav Petkov #define MSR_VIA_BCR2 0x00001147 638b72e7464SBorislav Petkov 639b72e7464SBorislav Petkov /* Transmeta defined MSRs */ 640b72e7464SBorislav Petkov #define MSR_TMTA_LONGRUN_CTRL 0x80868010 641b72e7464SBorislav Petkov #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 642b72e7464SBorislav Petkov #define MSR_TMTA_LRTI_READOUT 0x80868018 643b72e7464SBorislav Petkov #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 644b72e7464SBorislav Petkov 645b72e7464SBorislav Petkov /* Intel defined MSRs. */ 646b72e7464SBorislav Petkov #define MSR_IA32_P5_MC_ADDR 0x00000000 647b72e7464SBorislav Petkov #define MSR_IA32_P5_MC_TYPE 0x00000001 648b72e7464SBorislav Petkov #define MSR_IA32_TSC 0x00000010 649b72e7464SBorislav Petkov #define MSR_IA32_PLATFORM_ID 0x00000017 650b72e7464SBorislav Petkov #define MSR_IA32_EBL_CR_POWERON 0x0000002a 651b72e7464SBorislav Petkov #define MSR_EBC_FREQUENCY_ID 0x0000002c 652b72e7464SBorislav Petkov #define MSR_SMI_COUNT 0x00000034 65332ad73dbSSean Christopherson 65432ad73dbSSean Christopherson /* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */ 65532ad73dbSSean Christopherson #define MSR_IA32_FEAT_CTL 0x0000003a 65632ad73dbSSean Christopherson #define FEAT_CTL_LOCKED BIT(0) 65732ad73dbSSean Christopherson #define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1) 65832ad73dbSSean Christopherson #define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2) 659d205e0f1SSean Christopherson #define FEAT_CTL_SGX_LC_ENABLED BIT(17) 660e7b6385bSSean Christopherson #define FEAT_CTL_SGX_ENABLED BIT(18) 66132ad73dbSSean Christopherson #define FEAT_CTL_LMCE_ENABLED BIT(20) 66232ad73dbSSean Christopherson 663b72e7464SBorislav Petkov #define MSR_IA32_TSC_ADJUST 0x0000003b 664b72e7464SBorislav Petkov #define MSR_IA32_BNDCFGS 0x00000d90 665b72e7464SBorislav Petkov 6664531662dSJim Mattson #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 6674531662dSJim Mattson 668dae1bd58SChang S. Bae #define MSR_IA32_XFD 0x000001c4 669dae1bd58SChang S. Bae #define MSR_IA32_XFD_ERR 0x000001c5 670b72e7464SBorislav Petkov #define MSR_IA32_XSS 0x00000da0 671b72e7464SBorislav Petkov 672b72e7464SBorislav Petkov #define MSR_IA32_APICBASE 0x0000001b 673b72e7464SBorislav Petkov #define MSR_IA32_APICBASE_BSP (1<<8) 674b72e7464SBorislav Petkov #define MSR_IA32_APICBASE_ENABLE (1<<11) 675b72e7464SBorislav Petkov #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 676b72e7464SBorislav Petkov 677b72e7464SBorislav Petkov #define MSR_IA32_UCODE_WRITE 0x00000079 678b72e7464SBorislav Petkov #define MSR_IA32_UCODE_REV 0x0000008b 679b72e7464SBorislav Petkov 680d205e0f1SSean Christopherson /* Intel SGX Launch Enclave Public Key Hash MSRs */ 681d205e0f1SSean Christopherson #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C 682d205e0f1SSean Christopherson #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D 683d205e0f1SSean Christopherson #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E 684d205e0f1SSean Christopherson #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F 685d205e0f1SSean Christopherson 686b72e7464SBorislav Petkov #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 687b72e7464SBorislav Petkov #define MSR_IA32_SMBASE 0x0000009e 688b72e7464SBorislav Petkov 689b72e7464SBorislav Petkov #define MSR_IA32_PERF_STATUS 0x00000198 690b72e7464SBorislav Petkov #define MSR_IA32_PERF_CTL 0x00000199 691b72e7464SBorislav Petkov #define INTEL_PERF_CTL_MASK 0xffff 692b72e7464SBorislav Petkov 693b72e7464SBorislav Petkov #define MSR_IA32_MPERF 0x000000e7 694b72e7464SBorislav Petkov #define MSR_IA32_APERF 0x000000e8 695b72e7464SBorislav Petkov 696b72e7464SBorislav Petkov #define MSR_IA32_THERM_CONTROL 0x0000019a 697b72e7464SBorislav Petkov #define MSR_IA32_THERM_INTERRUPT 0x0000019b 698b72e7464SBorislav Petkov 699b72e7464SBorislav Petkov #define THERM_INT_HIGH_ENABLE (1 << 0) 700b72e7464SBorislav Petkov #define THERM_INT_LOW_ENABLE (1 << 1) 701b72e7464SBorislav Petkov #define THERM_INT_PLN_ENABLE (1 << 24) 702b72e7464SBorislav Petkov 703b72e7464SBorislav Petkov #define MSR_IA32_THERM_STATUS 0x0000019c 704b72e7464SBorislav Petkov 705b72e7464SBorislav Petkov #define THERM_STATUS_PROCHOT (1 << 0) 706b72e7464SBorislav Petkov #define THERM_STATUS_POWER_LIMIT (1 << 10) 707b72e7464SBorislav Petkov 708b72e7464SBorislav Petkov #define MSR_THERM2_CTL 0x0000019d 709b72e7464SBorislav Petkov 710b72e7464SBorislav Petkov #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 711b72e7464SBorislav Petkov 712b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE 0x000001a0 713b72e7464SBorislav Petkov 714b72e7464SBorislav Petkov #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 715b72e7464SBorislav Petkov 71698af7459SLen Brown #define MSR_MISC_FEATURE_CONTROL 0x000001a4 717b72e7464SBorislav Petkov #define MSR_MISC_PWR_MGMT 0x000001aa 718b72e7464SBorislav Petkov 719b72e7464SBorislav Petkov #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 720b72e7464SBorislav Petkov #define ENERGY_PERF_BIAS_PERFORMANCE 0 721d0117a0eSLen Brown #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 722b72e7464SBorislav Petkov #define ENERGY_PERF_BIAS_NORMAL 6 723d0117a0eSLen Brown #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 724b72e7464SBorislav Petkov #define ENERGY_PERF_BIAS_POWERSAVE 15 725b72e7464SBorislav Petkov 726b72e7464SBorislav Petkov #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 727b72e7464SBorislav Petkov 728b72e7464SBorislav Petkov #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 729b72e7464SBorislav Petkov #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 7307b8f40b3SRicardo Neri #define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26) 731b72e7464SBorislav Petkov 732b72e7464SBorislav Petkov #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 733b72e7464SBorislav Petkov 734b72e7464SBorislav Petkov #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 735b72e7464SBorislav Petkov #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 736b72e7464SBorislav Petkov #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 7377b8f40b3SRicardo Neri #define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25) 738b72e7464SBorislav Petkov 739b72e7464SBorislav Petkov /* Thermal Thresholds Support */ 740b72e7464SBorislav Petkov #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 741b72e7464SBorislav Petkov #define THERM_SHIFT_THRESHOLD0 8 742b72e7464SBorislav Petkov #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 743b72e7464SBorislav Petkov #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 744b72e7464SBorislav Petkov #define THERM_SHIFT_THRESHOLD1 16 745b72e7464SBorislav Petkov #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 746b72e7464SBorislav Petkov #define THERM_STATUS_THRESHOLD0 (1 << 6) 747b72e7464SBorislav Petkov #define THERM_LOG_THRESHOLD0 (1 << 7) 748b72e7464SBorislav Petkov #define THERM_STATUS_THRESHOLD1 (1 << 8) 749b72e7464SBorislav Petkov #define THERM_LOG_THRESHOLD1 (1 << 9) 750b72e7464SBorislav Petkov 751b72e7464SBorislav Petkov /* MISC_ENABLE bits: architectural */ 752b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 753b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 754b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 755b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 756b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 757b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 758b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 759b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 760b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 761b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 762b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 763b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 764b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 765b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 766b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 767b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 768b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 769b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 770b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 771b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 772b72e7464SBorislav Petkov 773b72e7464SBorislav Petkov /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 774b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 775b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 776b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 777b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 778b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 779b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 780b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 781b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 782b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 783b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 784b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 785b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 786b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 787b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 788b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 789b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 790b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 791b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 792b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 793b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 794b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 795b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 796b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 797b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 798b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 799b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 800b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 801b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 802b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 803b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 804b72e7464SBorislav Petkov 805ab6d9468SKyle Huey /* MISC_FEATURES_ENABLES non-architectural features */ 806ab6d9468SKyle Huey #define MSR_MISC_FEATURES_ENABLES 0x00000140 807ae47eda9SGrzegorz Andrejczuk 808e9ea1e7fSKyle Huey #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 809e9ea1e7fSKyle Huey #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) 810ab6d9468SKyle Huey #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 811ae47eda9SGrzegorz Andrejczuk 812b72e7464SBorislav Petkov #define MSR_IA32_TSC_DEADLINE 0x000006E0 813b72e7464SBorislav Petkov 81452f64909SPeter Zijlstra (Intel) 81552f64909SPeter Zijlstra (Intel) #define MSR_TSX_FORCE_ABORT 0x0000010F 81652f64909SPeter Zijlstra (Intel) 81752f64909SPeter Zijlstra (Intel) #define MSR_TFA_RTM_FORCE_ABORT_BIT 0 81852f64909SPeter Zijlstra (Intel) #define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) 8191348924bSPawan Gupta #define MSR_TFA_TSX_CPUID_CLEAR_BIT 1 8201348924bSPawan Gupta #define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT) 8211348924bSPawan Gupta #define MSR_TFA_SDV_ENABLE_RTM_BIT 2 8221348924bSPawan Gupta #define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT) 82352f64909SPeter Zijlstra (Intel) 824b72e7464SBorislav Petkov /* P4/Xeon+ specific */ 825b72e7464SBorislav Petkov #define MSR_IA32_MCG_EAX 0x00000180 826b72e7464SBorislav Petkov #define MSR_IA32_MCG_EBX 0x00000181 827b72e7464SBorislav Petkov #define MSR_IA32_MCG_ECX 0x00000182 828b72e7464SBorislav Petkov #define MSR_IA32_MCG_EDX 0x00000183 829b72e7464SBorislav Petkov #define MSR_IA32_MCG_ESI 0x00000184 830b72e7464SBorislav Petkov #define MSR_IA32_MCG_EDI 0x00000185 831b72e7464SBorislav Petkov #define MSR_IA32_MCG_EBP 0x00000186 832b72e7464SBorislav Petkov #define MSR_IA32_MCG_ESP 0x00000187 833b72e7464SBorislav Petkov #define MSR_IA32_MCG_EFLAGS 0x00000188 834b72e7464SBorislav Petkov #define MSR_IA32_MCG_EIP 0x00000189 835b72e7464SBorislav Petkov #define MSR_IA32_MCG_RESERVED 0x0000018a 836b72e7464SBorislav Petkov 837b72e7464SBorislav Petkov /* Pentium IV performance counter MSRs */ 838b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR0 0x00000300 839b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR1 0x00000301 840b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR2 0x00000302 841b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR3 0x00000303 842b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR0 0x00000304 843b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR1 0x00000305 844b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR2 0x00000306 845b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR3 0x00000307 846b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR0 0x00000308 847b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR1 0x00000309 848b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR2 0x0000030a 849b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR3 0x0000030b 850b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR0 0x0000030c 851b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR1 0x0000030d 852b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR2 0x0000030e 853b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR3 0x0000030f 854b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR4 0x00000310 855b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR5 0x00000311 856b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR0 0x00000360 857b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR1 0x00000361 858b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR2 0x00000362 859b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR3 0x00000363 860b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR0 0x00000364 861b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR1 0x00000365 862b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR2 0x00000366 863b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR3 0x00000367 864b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR0 0x00000368 865b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR1 0x00000369 866b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR2 0x0000036a 867b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR3 0x0000036b 868b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR0 0x0000036c 869b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR1 0x0000036d 870b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR2 0x0000036e 871b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR3 0x0000036f 872b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR4 0x00000370 873b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR5 0x00000371 874b72e7464SBorislav Petkov #define MSR_P4_ALF_ESCR0 0x000003ca 875b72e7464SBorislav Petkov #define MSR_P4_ALF_ESCR1 0x000003cb 876b72e7464SBorislav Petkov #define MSR_P4_BPU_ESCR0 0x000003b2 877b72e7464SBorislav Petkov #define MSR_P4_BPU_ESCR1 0x000003b3 878b72e7464SBorislav Petkov #define MSR_P4_BSU_ESCR0 0x000003a0 879b72e7464SBorislav Petkov #define MSR_P4_BSU_ESCR1 0x000003a1 880b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR0 0x000003b8 881b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR1 0x000003b9 882b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR2 0x000003cc 883b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR3 0x000003cd 884b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR4 0x000003e0 885b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR5 0x000003e1 886b72e7464SBorislav Petkov #define MSR_P4_DAC_ESCR0 0x000003a8 887b72e7464SBorislav Petkov #define MSR_P4_DAC_ESCR1 0x000003a9 888b72e7464SBorislav Petkov #define MSR_P4_FIRM_ESCR0 0x000003a4 889b72e7464SBorislav Petkov #define MSR_P4_FIRM_ESCR1 0x000003a5 890b72e7464SBorislav Petkov #define MSR_P4_FLAME_ESCR0 0x000003a6 891b72e7464SBorislav Petkov #define MSR_P4_FLAME_ESCR1 0x000003a7 892b72e7464SBorislav Petkov #define MSR_P4_FSB_ESCR0 0x000003a2 893b72e7464SBorislav Petkov #define MSR_P4_FSB_ESCR1 0x000003a3 894b72e7464SBorislav Petkov #define MSR_P4_IQ_ESCR0 0x000003ba 895b72e7464SBorislav Petkov #define MSR_P4_IQ_ESCR1 0x000003bb 896b72e7464SBorislav Petkov #define MSR_P4_IS_ESCR0 0x000003b4 897b72e7464SBorislav Petkov #define MSR_P4_IS_ESCR1 0x000003b5 898b72e7464SBorislav Petkov #define MSR_P4_ITLB_ESCR0 0x000003b6 899b72e7464SBorislav Petkov #define MSR_P4_ITLB_ESCR1 0x000003b7 900b72e7464SBorislav Petkov #define MSR_P4_IX_ESCR0 0x000003c8 901b72e7464SBorislav Petkov #define MSR_P4_IX_ESCR1 0x000003c9 902b72e7464SBorislav Petkov #define MSR_P4_MOB_ESCR0 0x000003aa 903b72e7464SBorislav Petkov #define MSR_P4_MOB_ESCR1 0x000003ab 904b72e7464SBorislav Petkov #define MSR_P4_MS_ESCR0 0x000003c0 905b72e7464SBorislav Petkov #define MSR_P4_MS_ESCR1 0x000003c1 906b72e7464SBorislav Petkov #define MSR_P4_PMH_ESCR0 0x000003ac 907b72e7464SBorislav Petkov #define MSR_P4_PMH_ESCR1 0x000003ad 908b72e7464SBorislav Petkov #define MSR_P4_RAT_ESCR0 0x000003bc 909b72e7464SBorislav Petkov #define MSR_P4_RAT_ESCR1 0x000003bd 910b72e7464SBorislav Petkov #define MSR_P4_SAAT_ESCR0 0x000003ae 911b72e7464SBorislav Petkov #define MSR_P4_SAAT_ESCR1 0x000003af 912b72e7464SBorislav Petkov #define MSR_P4_SSU_ESCR0 0x000003be 913b72e7464SBorislav Petkov #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 914b72e7464SBorislav Petkov 915b72e7464SBorislav Petkov #define MSR_P4_TBPU_ESCR0 0x000003c2 916b72e7464SBorislav Petkov #define MSR_P4_TBPU_ESCR1 0x000003c3 917b72e7464SBorislav Petkov #define MSR_P4_TC_ESCR0 0x000003c4 918b72e7464SBorislav Petkov #define MSR_P4_TC_ESCR1 0x000003c5 919b72e7464SBorislav Petkov #define MSR_P4_U2L_ESCR0 0x000003b0 920b72e7464SBorislav Petkov #define MSR_P4_U2L_ESCR1 0x000003b1 921b72e7464SBorislav Petkov 922b72e7464SBorislav Petkov #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 923b72e7464SBorislav Petkov 924b72e7464SBorislav Petkov /* Intel Core-based CPU performance counters */ 925b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 926b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 927b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 9287b2c05a1SKan Liang #define MSR_CORE_PERF_FIXED_CTR3 0x0000030c 929b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 930b72e7464SBorislav Petkov #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 931b72e7464SBorislav Petkov #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 932b72e7464SBorislav Petkov #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 933b72e7464SBorislav Petkov 93459a854e2SKan Liang #define MSR_PERF_METRICS 0x00000329 93559a854e2SKan Liang 9368479e04eSLuwei Kang /* PERF_GLOBAL_OVF_CTL bits */ 9378479e04eSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55 9388479e04eSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT) 939c715eb9fSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62 940c715eb9fSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT) 941c715eb9fSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 942c715eb9fSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) 9438479e04eSLuwei Kang 944b72e7464SBorislav Petkov /* Geode defined MSRs */ 945b72e7464SBorislav Petkov #define MSR_GEODE_BUSCONT_CONF0 0x00001900 946b72e7464SBorislav Petkov 947b72e7464SBorislav Petkov /* Intel VT MSRs */ 948b72e7464SBorislav Petkov #define MSR_IA32_VMX_BASIC 0x00000480 949b72e7464SBorislav Petkov #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 950b72e7464SBorislav Petkov #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 951b72e7464SBorislav Petkov #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 952b72e7464SBorislav Petkov #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 953b72e7464SBorislav Petkov #define MSR_IA32_VMX_MISC 0x00000485 954b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 955b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 956b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 957b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 958b72e7464SBorislav Petkov #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 959b72e7464SBorislav Petkov #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 960b72e7464SBorislav Petkov #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 961b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 962b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 963b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 964b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 965b72e7464SBorislav Petkov #define MSR_IA32_VMX_VMFUNC 0x00000491 966b72e7464SBorislav Petkov 967b72e7464SBorislav Petkov /* VMX_BASIC bits and bitmasks */ 968b72e7464SBorislav Petkov #define VMX_BASIC_VMCS_SIZE_SHIFT 32 969b72e7464SBorislav Petkov #define VMX_BASIC_TRUE_CTLS (1ULL << 55) 970b72e7464SBorislav Petkov #define VMX_BASIC_64 0x0001000000000000LLU 971b72e7464SBorislav Petkov #define VMX_BASIC_MEM_TYPE_SHIFT 50 972b72e7464SBorislav Petkov #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 973b72e7464SBorislav Petkov #define VMX_BASIC_MEM_TYPE_WB 6LLU 974b72e7464SBorislav Petkov #define VMX_BASIC_INOUT 0x0040000000000000LLU 975b72e7464SBorislav Petkov 976b72e7464SBorislav Petkov /* MSR_IA32_VMX_MISC bits */ 977f99e3dafSChao Peng #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) 978b72e7464SBorislav Petkov #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 979b72e7464SBorislav Petkov #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 980b72e7464SBorislav Petkov /* AMD-V MSRs */ 981b72e7464SBorislav Petkov 982b72e7464SBorislav Petkov #define MSR_VM_CR 0xc0010114 983b72e7464SBorislav Petkov #define MSR_VM_IGNNE 0xc0010115 984b72e7464SBorislav Petkov #define MSR_VM_HSAVE_PA 0xc0010117 985b72e7464SBorislav Petkov 9867b8f40b3SRicardo Neri /* Hardware Feedback Interface */ 9877b8f40b3SRicardo Neri #define MSR_IA32_HW_FEEDBACK_PTR 0x17d0 9887b8f40b3SRicardo Neri #define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1 9897b8f40b3SRicardo Neri 990b72e7464SBorislav Petkov #endif /* _ASM_X86_MSR_INDEX_H */ 991