1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2b72e7464SBorislav Petkov #ifndef _ASM_X86_MSR_INDEX_H 3b72e7464SBorislav Petkov #define _ASM_X86_MSR_INDEX_H 4b72e7464SBorislav Petkov 5d8eabc37SThomas Gleixner #include <linux/bits.h> 6d8eabc37SThomas Gleixner 7053080a9SBorislav Petkov /* 8053080a9SBorislav Petkov * CPU model specific register (MSR) numbers. 9053080a9SBorislav Petkov * 10053080a9SBorislav Petkov * Do not add new entries to this file unless the definitions are shared 11053080a9SBorislav Petkov * between multiple compilation units. 12053080a9SBorislav Petkov */ 13b72e7464SBorislav Petkov 14b72e7464SBorislav Petkov /* x86-64 specific MSRs */ 15b72e7464SBorislav Petkov #define MSR_EFER 0xc0000080 /* extended feature register */ 16b72e7464SBorislav Petkov #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 17b72e7464SBorislav Petkov #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 18b72e7464SBorislav Petkov #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 19b72e7464SBorislav Petkov #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 20b72e7464SBorislav Petkov #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 21b72e7464SBorislav Petkov #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 22b72e7464SBorislav Petkov #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 23b72e7464SBorislav Petkov #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 24b72e7464SBorislav Petkov 25b72e7464SBorislav Petkov /* EFER bits: */ 26b72e7464SBorislav Petkov #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 27b72e7464SBorislav Petkov #define _EFER_LME 8 /* Long mode enable */ 28b72e7464SBorislav Petkov #define _EFER_LMA 10 /* Long mode active (read-only) */ 29b72e7464SBorislav Petkov #define _EFER_NX 11 /* No execute enable */ 30b72e7464SBorislav Petkov #define _EFER_SVME 12 /* Enable virtualization */ 31b72e7464SBorislav Petkov #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 32b72e7464SBorislav Petkov #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 33b72e7464SBorislav Petkov 34b72e7464SBorislav Petkov #define EFER_SCE (1<<_EFER_SCE) 35b72e7464SBorislav Petkov #define EFER_LME (1<<_EFER_LME) 36b72e7464SBorislav Petkov #define EFER_LMA (1<<_EFER_LMA) 37b72e7464SBorislav Petkov #define EFER_NX (1<<_EFER_NX) 38b72e7464SBorislav Petkov #define EFER_SVME (1<<_EFER_SVME) 39b72e7464SBorislav Petkov #define EFER_LMSLE (1<<_EFER_LMSLE) 40b72e7464SBorislav Petkov #define EFER_FFXSR (1<<_EFER_FFXSR) 41b72e7464SBorislav Petkov 42b72e7464SBorislav Petkov /* Intel MSRs. Some also available on other CPUs */ 433f5a7896STony Luck 446650cdd9SPeter Zijlstra (Intel) #define MSR_TEST_CTRL 0x00000033 456650cdd9SPeter Zijlstra (Intel) #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 466650cdd9SPeter Zijlstra (Intel) #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) 476650cdd9SPeter Zijlstra (Intel) 481e340c60SDavid Woodhouse #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 49d8eabc37SThomas Gleixner #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ 505bfbe3adSTim Chen #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ 51d8eabc37SThomas Gleixner #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ 529f65fb29SKonrad Rzeszutek Wilk #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ 53d8eabc37SThomas Gleixner #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ 544ad3278dSPawan Gupta #define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */ 554ad3278dSPawan Gupta #define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT) 561e340c60SDavid Woodhouse 571e340c60SDavid Woodhouse #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 58d8eabc37SThomas Gleixner #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ 591e340c60SDavid Woodhouse 603f5a7896STony Luck #define MSR_PPIN_CTL 0x0000004e 613f5a7896STony Luck #define MSR_PPIN 0x0000004f 623f5a7896STony Luck 63b72e7464SBorislav Petkov #define MSR_IA32_PERFCTR0 0x000000c1 64b72e7464SBorislav Petkov #define MSR_IA32_PERFCTR1 0x000000c2 65b72e7464SBorislav Petkov #define MSR_FSB_FREQ 0x000000cd 665369a21eSLen Brown #define MSR_PLATFORM_INFO 0x000000ce 6790218ac7SKyle Huey #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 6890218ac7SKyle Huey #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) 69b72e7464SBorislav Petkov 70bd688c69SFenghua Yu #define MSR_IA32_UMWAIT_CONTROL 0xe1 71bd688c69SFenghua Yu #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0) 72bd688c69SFenghua Yu #define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1) 73bd688c69SFenghua Yu /* 74bd688c69SFenghua Yu * The time field is bit[31:2], but representing a 32bit value with 75bd688c69SFenghua Yu * bit[1:0] zero. 76bd688c69SFenghua Yu */ 77bd688c69SFenghua Yu #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U) 78bd688c69SFenghua Yu 796650cdd9SPeter Zijlstra (Intel) /* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */ 806650cdd9SPeter Zijlstra (Intel) #define MSR_IA32_CORE_CAPS 0x000000cf 81db1af129STony Luck #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT 2 82db1af129STony Luck #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT) 836650cdd9SPeter Zijlstra (Intel) #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5 846650cdd9SPeter Zijlstra (Intel) #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT) 856650cdd9SPeter Zijlstra (Intel) 8640496c8eSLen Brown #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 87b72e7464SBorislav Petkov #define NHM_C3_AUTO_DEMOTE (1UL << 25) 88b72e7464SBorislav Petkov #define NHM_C1_AUTO_DEMOTE (1UL << 26) 89b72e7464SBorislav Petkov #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 90a00072a2SMatt Turner #define SNB_C3_AUTO_UNDEMOTE (1UL << 27) 91a00072a2SMatt Turner #define SNB_C1_AUTO_UNDEMOTE (1UL << 28) 92b72e7464SBorislav Petkov 93b72e7464SBorislav Petkov #define MSR_MTRRcap 0x000000fe 941e340c60SDavid Woodhouse 951e340c60SDavid Woodhouse #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 96d8eabc37SThomas Gleixner #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ 97d8eabc37SThomas Gleixner #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ 986ad0ad2bSPeter Zijlstra #define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */ 99d8eabc37SThomas Gleixner #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ 100d8eabc37SThomas Gleixner #define ARCH_CAP_SSB_NO BIT(4) /* 10177243971SKonrad Rzeszutek Wilk * Not susceptible to Speculative Store Bypass 1029f65fb29SKonrad Rzeszutek Wilk * attack, so no Speculative Store Bypass 1039f65fb29SKonrad Rzeszutek Wilk * control required. 10477243971SKonrad Rzeszutek Wilk */ 105ed5194c2SAndi Kleen #define ARCH_CAP_MDS_NO BIT(5) /* 106ed5194c2SAndi Kleen * Not susceptible to 107ed5194c2SAndi Kleen * Microarchitectural Data 108ed5194c2SAndi Kleen * Sampling (MDS) vulnerabilities. 109ed5194c2SAndi Kleen */ 110db4d30fbSVineela Tummalapalli #define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* 111db4d30fbSVineela Tummalapalli * The processor is not susceptible to a 112db4d30fbSVineela Tummalapalli * machine check error due to modifying the 113db4d30fbSVineela Tummalapalli * code page size along with either the 114db4d30fbSVineela Tummalapalli * physical address or cache type 115db4d30fbSVineela Tummalapalli * without TLB invalidation. 116db4d30fbSVineela Tummalapalli */ 117c2955f27SPawan Gupta #define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ 1181b42f017SPawan Gupta #define ARCH_CAP_TAA_NO BIT(8) /* 1191b42f017SPawan Gupta * Not susceptible to 1201b42f017SPawan Gupta * TSX Async Abort (TAA) vulnerabilities. 1211b42f017SPawan Gupta */ 12251802186SPawan Gupta #define ARCH_CAP_SBDR_SSDP_NO BIT(13) /* 12351802186SPawan Gupta * Not susceptible to SBDR and SSDP 12451802186SPawan Gupta * variants of Processor MMIO stale data 12551802186SPawan Gupta * vulnerabilities. 12651802186SPawan Gupta */ 12751802186SPawan Gupta #define ARCH_CAP_FBSDP_NO BIT(14) /* 12851802186SPawan Gupta * Not susceptible to FBSDP variant of 12951802186SPawan Gupta * Processor MMIO stale data 13051802186SPawan Gupta * vulnerabilities. 13151802186SPawan Gupta */ 13251802186SPawan Gupta #define ARCH_CAP_PSDP_NO BIT(15) /* 13351802186SPawan Gupta * Not susceptible to PSDP variant of 13451802186SPawan Gupta * Processor MMIO stale data 13551802186SPawan Gupta * vulnerabilities. 13651802186SPawan Gupta */ 13751802186SPawan Gupta #define ARCH_CAP_FB_CLEAR BIT(17) /* 13851802186SPawan Gupta * VERW clears CPU fill buffer 13951802186SPawan Gupta * even on MDS_NO CPUs. 14051802186SPawan Gupta */ 141027bbb88SPawan Gupta #define ARCH_CAP_FB_CLEAR_CTRL BIT(18) /* 142027bbb88SPawan Gupta * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS] 143027bbb88SPawan Gupta * bit available to control VERW 144027bbb88SPawan Gupta * behavior. 145027bbb88SPawan Gupta */ 1464ad3278dSPawan Gupta #define ARCH_CAP_RRSBA BIT(19) /* 1474ad3278dSPawan Gupta * Indicates RET may use predictors 1484ad3278dSPawan Gupta * other than the RSB. With eIBRS 1494ad3278dSPawan Gupta * enabled predictions in kernel mode 1504ad3278dSPawan Gupta * are restricted to targets in 1514ad3278dSPawan Gupta * kernel. 1524ad3278dSPawan Gupta */ 1532b129932SDaniel Sneddon #define ARCH_CAP_PBRSB_NO BIT(24) /* 1542b129932SDaniel Sneddon * Not susceptible to Post-Barrier 1552b129932SDaniel Sneddon * Return Stack Buffer Predictions. 1562b129932SDaniel Sneddon */ 1571e340c60SDavid Woodhouse 1583fa045beSPaolo Bonzini #define MSR_IA32_FLUSH_CMD 0x0000010b 159d8eabc37SThomas Gleixner #define L1D_FLUSH BIT(0) /* 1603fa045beSPaolo Bonzini * Writeback and invalidate the 1613fa045beSPaolo Bonzini * L1 data cache. 1623fa045beSPaolo Bonzini */ 1633fa045beSPaolo Bonzini 164b72e7464SBorislav Petkov #define MSR_IA32_BBL_CR_CTL 0x00000119 165b72e7464SBorislav Petkov #define MSR_IA32_BBL_CR_CTL3 0x0000011e 166b72e7464SBorislav Petkov 167c2955f27SPawan Gupta #define MSR_IA32_TSX_CTRL 0x00000122 168c2955f27SPawan Gupta #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ 169c2955f27SPawan Gupta #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ 170c2955f27SPawan Gupta 1717e5b3c26SMark Gross #define MSR_IA32_MCU_OPT_CTRL 0x00000123 172400331f8SPawan Gupta #define RNGDS_MITG_DIS BIT(0) /* SRBDS support */ 173400331f8SPawan Gupta #define RTM_ALLOW BIT(1) /* TSX development mode */ 174027bbb88SPawan Gupta #define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */ 1757e5b3c26SMark Gross 176b72e7464SBorislav Petkov #define MSR_IA32_SYSENTER_CS 0x00000174 177b72e7464SBorislav Petkov #define MSR_IA32_SYSENTER_ESP 0x00000175 178b72e7464SBorislav Petkov #define MSR_IA32_SYSENTER_EIP 0x00000176 179b72e7464SBorislav Petkov 180b72e7464SBorislav Petkov #define MSR_IA32_MCG_CAP 0x00000179 181b72e7464SBorislav Petkov #define MSR_IA32_MCG_STATUS 0x0000017a 182b72e7464SBorislav Petkov #define MSR_IA32_MCG_CTL 0x0000017b 18368299a42STony Luck #define MSR_ERROR_CONTROL 0x0000017f 184b72e7464SBorislav Petkov #define MSR_IA32_MCG_EXT_CTL 0x000004d0 185b72e7464SBorislav Petkov 186b72e7464SBorislav Petkov #define MSR_OFFCORE_RSP_0 0x000001a6 187b72e7464SBorislav Petkov #define MSR_OFFCORE_RSP_1 0x000001a7 188b72e7464SBorislav Petkov #define MSR_TURBO_RATIO_LIMIT 0x000001ad 189b72e7464SBorislav Petkov #define MSR_TURBO_RATIO_LIMIT1 0x000001ae 190b72e7464SBorislav Petkov #define MSR_TURBO_RATIO_LIMIT2 0x000001af 191b72e7464SBorislav Petkov 192b72e7464SBorislav Petkov #define MSR_LBR_SELECT 0x000001c8 193b72e7464SBorislav Petkov #define MSR_LBR_TOS 0x000001c9 194ed7bde7aSSrinivas Pandruvada 195ed7bde7aSSrinivas Pandruvada #define MSR_IA32_POWER_CTL 0x000001fc 196ed7bde7aSSrinivas Pandruvada #define MSR_IA32_POWER_CTL_BIT_EE 19 197ed7bde7aSSrinivas Pandruvada 198db1af129STony Luck /* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */ 199db1af129STony Luck #define MSR_INTEGRITY_CAPS 0x000002d9 200db1af129STony Luck #define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4 201db1af129STony Luck #define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT) 202db1af129STony Luck 203b72e7464SBorislav Petkov #define MSR_LBR_NHM_FROM 0x00000680 204b72e7464SBorislav Petkov #define MSR_LBR_NHM_TO 0x000006c0 205b72e7464SBorislav Petkov #define MSR_LBR_CORE_FROM 0x00000040 206b72e7464SBorislav Petkov #define MSR_LBR_CORE_TO 0x00000060 207b72e7464SBorislav Petkov 208b83ff1c8SAndi Kleen #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 209b83ff1c8SAndi Kleen #define LBR_INFO_MISPRED BIT_ULL(63) 210b83ff1c8SAndi Kleen #define LBR_INFO_IN_TX BIT_ULL(62) 211b83ff1c8SAndi Kleen #define LBR_INFO_ABORT BIT_ULL(61) 212d6a162a4SKan Liang #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60) 213b83ff1c8SAndi Kleen #define LBR_INFO_CYCLES 0xffff 214d6a162a4SKan Liang #define LBR_INFO_BR_TYPE_OFFSET 56 215d6a162a4SKan Liang #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) 216d6a162a4SKan Liang 217d6a162a4SKan Liang #define MSR_ARCH_LBR_CTL 0x000014ce 218d6a162a4SKan Liang #define ARCH_LBR_CTL_LBREN BIT(0) 219d6a162a4SKan Liang #define ARCH_LBR_CTL_CPL_OFFSET 1 220d6a162a4SKan Liang #define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET) 221d6a162a4SKan Liang #define ARCH_LBR_CTL_STACK_OFFSET 3 222d6a162a4SKan Liang #define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET) 223d6a162a4SKan Liang #define ARCH_LBR_CTL_FILTER_OFFSET 16 224d6a162a4SKan Liang #define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET) 225d6a162a4SKan Liang #define MSR_ARCH_LBR_DEPTH 0x000014cf 226d6a162a4SKan Liang #define MSR_ARCH_LBR_FROM_0 0x00001500 227d6a162a4SKan Liang #define MSR_ARCH_LBR_TO_0 0x00001600 228d6a162a4SKan Liang #define MSR_ARCH_LBR_INFO_0 0x00001200 229b83ff1c8SAndi Kleen 230b72e7464SBorislav Petkov #define MSR_IA32_PEBS_ENABLE 0x000003f1 231c22497f5SKan Liang #define MSR_PEBS_DATA_CFG 0x000003f2 232b72e7464SBorislav Petkov #define MSR_IA32_DS_AREA 0x00000600 233b72e7464SBorislav Petkov #define MSR_IA32_PERF_CAPABILITIES 0x00000345 234d0946a88SKan Liang #define PERF_CAP_METRICS_IDX 15 235d0946a88SKan Liang #define PERF_CAP_PT_IDX 16 236d0946a88SKan Liang 237b72e7464SBorislav Petkov #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 238c59a1f10SLike Xu #define PERF_CAP_PEBS_TRAP BIT_ULL(6) 239c59a1f10SLike Xu #define PERF_CAP_ARCH_REG BIT_ULL(7) 240c59a1f10SLike Xu #define PERF_CAP_PEBS_FORMAT 0xf00 241c59a1f10SLike Xu #define PERF_CAP_PEBS_BASELINE BIT_ULL(14) 242c59a1f10SLike Xu #define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ 243c59a1f10SLike Xu PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE) 244b72e7464SBorislav Petkov 245b72e7464SBorislav Petkov #define MSR_IA32_RTIT_CTL 0x00000570 246887eda13SChao Peng #define RTIT_CTL_TRACEEN BIT(0) 247887eda13SChao Peng #define RTIT_CTL_CYCLEACC BIT(1) 248887eda13SChao Peng #define RTIT_CTL_OS BIT(2) 249887eda13SChao Peng #define RTIT_CTL_USR BIT(3) 250887eda13SChao Peng #define RTIT_CTL_PWR_EVT_EN BIT(4) 251887eda13SChao Peng #define RTIT_CTL_FUP_ON_PTW BIT(5) 25269843a91SLuwei Kang #define RTIT_CTL_FABRIC_EN BIT(6) 253887eda13SChao Peng #define RTIT_CTL_CR3EN BIT(7) 254887eda13SChao Peng #define RTIT_CTL_TOPA BIT(8) 255887eda13SChao Peng #define RTIT_CTL_MTC_EN BIT(9) 256887eda13SChao Peng #define RTIT_CTL_TSC_EN BIT(10) 257887eda13SChao Peng #define RTIT_CTL_DISRETC BIT(11) 258887eda13SChao Peng #define RTIT_CTL_PTW_EN BIT(12) 259887eda13SChao Peng #define RTIT_CTL_BRANCH_EN BIT(13) 26028c24dedSAlexander Shishkin #define RTIT_CTL_EVENT_EN BIT(31) 261161a9a33SAlexander Shishkin #define RTIT_CTL_NOTNT BIT_ULL(55) 262887eda13SChao Peng #define RTIT_CTL_MTC_RANGE_OFFSET 14 263887eda13SChao Peng #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 264887eda13SChao Peng #define RTIT_CTL_CYC_THRESH_OFFSET 19 265887eda13SChao Peng #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 266887eda13SChao Peng #define RTIT_CTL_PSB_FREQ_OFFSET 24 267887eda13SChao Peng #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 268887eda13SChao Peng #define RTIT_CTL_ADDR0_OFFSET 32 269887eda13SChao Peng #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) 270887eda13SChao Peng #define RTIT_CTL_ADDR1_OFFSET 36 271887eda13SChao Peng #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) 272887eda13SChao Peng #define RTIT_CTL_ADDR2_OFFSET 40 273887eda13SChao Peng #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) 274887eda13SChao Peng #define RTIT_CTL_ADDR3_OFFSET 44 275887eda13SChao Peng #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) 276b72e7464SBorislav Petkov #define MSR_IA32_RTIT_STATUS 0x00000571 277887eda13SChao Peng #define RTIT_STATUS_FILTEREN BIT(0) 278887eda13SChao Peng #define RTIT_STATUS_CONTEXTEN BIT(1) 279887eda13SChao Peng #define RTIT_STATUS_TRIGGEREN BIT(2) 280887eda13SChao Peng #define RTIT_STATUS_BUFFOVF BIT(3) 281887eda13SChao Peng #define RTIT_STATUS_ERROR BIT(4) 282887eda13SChao Peng #define RTIT_STATUS_STOPPED BIT(5) 28369843a91SLuwei Kang #define RTIT_STATUS_BYTECNT_OFFSET 32 28469843a91SLuwei Kang #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) 285f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR0_A 0x00000580 286f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR0_B 0x00000581 287f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR1_A 0x00000582 288f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR1_B 0x00000583 289f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR2_A 0x00000584 290f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR2_B 0x00000585 291f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR3_A 0x00000586 292f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR3_B 0x00000587 293b72e7464SBorislav Petkov #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 294b72e7464SBorislav Petkov #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 295b72e7464SBorislav Petkov #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 296b72e7464SBorislav Petkov 297b72e7464SBorislav Petkov #define MSR_MTRRfix64K_00000 0x00000250 298b72e7464SBorislav Petkov #define MSR_MTRRfix16K_80000 0x00000258 299b72e7464SBorislav Petkov #define MSR_MTRRfix16K_A0000 0x00000259 300b72e7464SBorislav Petkov #define MSR_MTRRfix4K_C0000 0x00000268 301b72e7464SBorislav Petkov #define MSR_MTRRfix4K_C8000 0x00000269 302b72e7464SBorislav Petkov #define MSR_MTRRfix4K_D0000 0x0000026a 303b72e7464SBorislav Petkov #define MSR_MTRRfix4K_D8000 0x0000026b 304b72e7464SBorislav Petkov #define MSR_MTRRfix4K_E0000 0x0000026c 305b72e7464SBorislav Petkov #define MSR_MTRRfix4K_E8000 0x0000026d 306b72e7464SBorislav Petkov #define MSR_MTRRfix4K_F0000 0x0000026e 307b72e7464SBorislav Petkov #define MSR_MTRRfix4K_F8000 0x0000026f 308b72e7464SBorislav Petkov #define MSR_MTRRdefType 0x000002ff 309b72e7464SBorislav Petkov 310b72e7464SBorislav Petkov #define MSR_IA32_CR_PAT 0x00000277 311b72e7464SBorislav Petkov 312b72e7464SBorislav Petkov #define MSR_IA32_DEBUGCTLMSR 0x000001d9 313b72e7464SBorislav Petkov #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 314b72e7464SBorislav Petkov #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 315b72e7464SBorislav Petkov #define MSR_IA32_LASTINTFROMIP 0x000001dd 316b72e7464SBorislav Petkov #define MSR_IA32_LASTINTTOIP 0x000001de 317b72e7464SBorislav Petkov 318f0f2f9feSFenghua Yu #define MSR_IA32_PASID 0x00000d93 319f0f2f9feSFenghua Yu #define MSR_IA32_PASID_VALID BIT_ULL(31) 320f0f2f9feSFenghua Yu 321b72e7464SBorislav Petkov /* DEBUGCTLMSR bits (others vary by model): */ 322b72e7464SBorislav Petkov #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 323b9894a2fSKyle Huey #define DEBUGCTLMSR_BTF_SHIFT 1 324b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 325ebb1064eSFenghua Yu #define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2) 326b72e7464SBorislav Petkov #define DEBUGCTLMSR_TR (1UL << 6) 327b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTS (1UL << 7) 328b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTINT (1UL << 8) 329b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 330b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 331b72e7464SBorislav Petkov #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 332af3bdb99SAndi Kleen #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) 3336089327fSKan Liang #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 3346089327fSKan Liang #define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 335b72e7464SBorislav Petkov 336d0dc8494SAndi Kleen #define MSR_PEBS_FRONTEND 0x000003f7 337d0dc8494SAndi Kleen 338b72e7464SBorislav Petkov #define MSR_IA32_MC0_CTL 0x00000400 339b72e7464SBorislav Petkov #define MSR_IA32_MC0_STATUS 0x00000401 340b72e7464SBorislav Petkov #define MSR_IA32_MC0_ADDR 0x00000402 341b72e7464SBorislav Petkov #define MSR_IA32_MC0_MISC 0x00000403 342b72e7464SBorislav Petkov 343b72e7464SBorislav Petkov /* C-state Residency Counters */ 344b72e7464SBorislav Petkov #define MSR_PKG_C3_RESIDENCY 0x000003f8 345b72e7464SBorislav Petkov #define MSR_PKG_C6_RESIDENCY 0x000003f9 3460539ba11SLen Brown #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 347b72e7464SBorislav Petkov #define MSR_PKG_C7_RESIDENCY 0x000003fa 348b72e7464SBorislav Petkov #define MSR_CORE_C3_RESIDENCY 0x000003fc 349b72e7464SBorislav Petkov #define MSR_CORE_C6_RESIDENCY 0x000003fd 350b72e7464SBorislav Petkov #define MSR_CORE_C7_RESIDENCY 0x000003fe 351b72e7464SBorislav Petkov #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 352b72e7464SBorislav Petkov #define MSR_PKG_C2_RESIDENCY 0x0000060d 353b72e7464SBorislav Petkov #define MSR_PKG_C8_RESIDENCY 0x00000630 354b72e7464SBorislav Petkov #define MSR_PKG_C9_RESIDENCY 0x00000631 355b72e7464SBorislav Petkov #define MSR_PKG_C10_RESIDENCY 0x00000632 356b72e7464SBorislav Petkov 3575a63426eSLen Brown /* Interrupt Response Limit */ 3585a63426eSLen Brown #define MSR_PKGC3_IRTL 0x0000060a 3595a63426eSLen Brown #define MSR_PKGC6_IRTL 0x0000060b 3605a63426eSLen Brown #define MSR_PKGC7_IRTL 0x0000060c 3615a63426eSLen Brown #define MSR_PKGC8_IRTL 0x00000633 3625a63426eSLen Brown #define MSR_PKGC9_IRTL 0x00000634 3635a63426eSLen Brown #define MSR_PKGC10_IRTL 0x00000635 3645a63426eSLen Brown 365b72e7464SBorislav Petkov /* Run Time Average Power Limiting (RAPL) Interface */ 366b72e7464SBorislav Petkov 367f52ba931SSumeet Pawnikar #define MSR_VR_CURRENT_CONFIG 0x00000601 368b72e7464SBorislav Petkov #define MSR_RAPL_POWER_UNIT 0x00000606 369b72e7464SBorislav Petkov 370b72e7464SBorislav Petkov #define MSR_PKG_POWER_LIMIT 0x00000610 371b72e7464SBorislav Petkov #define MSR_PKG_ENERGY_STATUS 0x00000611 372b72e7464SBorislav Petkov #define MSR_PKG_PERF_STATUS 0x00000613 373b72e7464SBorislav Petkov #define MSR_PKG_POWER_INFO 0x00000614 374b72e7464SBorislav Petkov 375b72e7464SBorislav Petkov #define MSR_DRAM_POWER_LIMIT 0x00000618 376b72e7464SBorislav Petkov #define MSR_DRAM_ENERGY_STATUS 0x00000619 377b72e7464SBorislav Petkov #define MSR_DRAM_PERF_STATUS 0x0000061b 378b72e7464SBorislav Petkov #define MSR_DRAM_POWER_INFO 0x0000061c 379b72e7464SBorislav Petkov 380b72e7464SBorislav Petkov #define MSR_PP0_POWER_LIMIT 0x00000638 381b72e7464SBorislav Petkov #define MSR_PP0_ENERGY_STATUS 0x00000639 382b72e7464SBorislav Petkov #define MSR_PP0_POLICY 0x0000063a 383b72e7464SBorislav Petkov #define MSR_PP0_PERF_STATUS 0x0000063b 384b72e7464SBorislav Petkov 385b72e7464SBorislav Petkov #define MSR_PP1_POWER_LIMIT 0x00000640 386b72e7464SBorislav Petkov #define MSR_PP1_ENERGY_STATUS 0x00000641 387b72e7464SBorislav Petkov #define MSR_PP1_POLICY 0x00000642 388b72e7464SBorislav Petkov 3895cde2653SStephane Eranian #define MSR_AMD_RAPL_POWER_UNIT 0xc0010299 39043756a29SVictor Ding #define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a 391298ed2b3SVictor Ding #define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b 3925cde2653SStephane Eranian 3934a6772f5SVladimir Zapolskiy /* Config TDP MSRs */ 39482bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_NOMINAL 0x00000648 39582bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 39682bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 39782bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_CONTROL 0x0000064B 39882bb70c5SRafael J. Wysocki #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 39982bb70c5SRafael J. Wysocki 400dcee75b3SSrinivas Pandruvada #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 4014af184eeSLen Brown #define MSR_SECONDARY_TURBO_RATIO_LIMIT 0x00000650 402dcee75b3SSrinivas Pandruvada 403b72e7464SBorislav Petkov #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 404b72e7464SBorislav Petkov #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 405b72e7464SBorislav Petkov #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 406b72e7464SBorislav Petkov #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 407b72e7464SBorislav Petkov 408b72e7464SBorislav Petkov #define MSR_CORE_C1_RES 0x00000660 4090539ba11SLen Brown #define MSR_MODULE_C6_RES_MS 0x00000664 410b72e7464SBorislav Petkov 411b72e7464SBorislav Petkov #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 412b72e7464SBorislav Petkov #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 413b72e7464SBorislav Petkov 4148a34fd02SLen Brown #define MSR_ATOM_CORE_RATIOS 0x0000066a 4158a34fd02SLen Brown #define MSR_ATOM_CORE_VIDS 0x0000066b 4168a34fd02SLen Brown #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 4178a34fd02SLen Brown #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 4188a34fd02SLen Brown 419b72e7464SBorislav Petkov #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 420b72e7464SBorislav Petkov #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 421b72e7464SBorislav Petkov #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 422b72e7464SBorislav Petkov 423991625f3SPeter Zijlstra /* Control-flow Enforcement Technology MSRs */ 424991625f3SPeter Zijlstra #define MSR_IA32_U_CET 0x000006a0 /* user mode cet */ 425991625f3SPeter Zijlstra #define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */ 426991625f3SPeter Zijlstra #define CET_SHSTK_EN BIT_ULL(0) 427991625f3SPeter Zijlstra #define CET_WRSS_EN BIT_ULL(1) 428991625f3SPeter Zijlstra #define CET_ENDBR_EN BIT_ULL(2) 429991625f3SPeter Zijlstra #define CET_LEG_IW_EN BIT_ULL(3) 430991625f3SPeter Zijlstra #define CET_NO_TRACK_EN BIT_ULL(4) 431991625f3SPeter Zijlstra #define CET_SUPPRESS_DISABLE BIT_ULL(5) 432991625f3SPeter Zijlstra #define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9)) 433991625f3SPeter Zijlstra #define CET_SUPPRESS BIT_ULL(10) 434991625f3SPeter Zijlstra #define CET_WAIT_ENDBR BIT_ULL(11) 435991625f3SPeter Zijlstra 436991625f3SPeter Zijlstra #define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */ 437991625f3SPeter Zijlstra #define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */ 438991625f3SPeter Zijlstra #define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */ 439991625f3SPeter Zijlstra #define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */ 440991625f3SPeter Zijlstra #define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */ 441991625f3SPeter Zijlstra 442b72e7464SBorislav Petkov /* Hardware P state interface */ 443b72e7464SBorislav Petkov #define MSR_PPERF 0x0000064e 444b72e7464SBorislav Petkov #define MSR_PERF_LIMIT_REASONS 0x0000064f 445b72e7464SBorislav Petkov #define MSR_PM_ENABLE 0x00000770 446b72e7464SBorislav Petkov #define MSR_HWP_CAPABILITIES 0x00000771 447b72e7464SBorislav Petkov #define MSR_HWP_REQUEST_PKG 0x00000772 448b72e7464SBorislav Petkov #define MSR_HWP_INTERRUPT 0x00000773 449b72e7464SBorislav Petkov #define MSR_HWP_REQUEST 0x00000774 450b72e7464SBorislav Petkov #define MSR_HWP_STATUS 0x00000777 451b72e7464SBorislav Petkov 452b72e7464SBorislav Petkov /* CPUID.6.EAX */ 453b72e7464SBorislav Petkov #define HWP_BASE_BIT (1<<7) 454b72e7464SBorislav Petkov #define HWP_NOTIFICATIONS_BIT (1<<8) 455b72e7464SBorislav Petkov #define HWP_ACTIVITY_WINDOW_BIT (1<<9) 456b72e7464SBorislav Petkov #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 457b72e7464SBorislav Petkov #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 458b72e7464SBorislav Petkov 459b72e7464SBorislav Petkov /* IA32_HWP_CAPABILITIES */ 460670e27d8SLen Brown #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 461670e27d8SLen Brown #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 462670e27d8SLen Brown #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 463670e27d8SLen Brown #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 464b72e7464SBorislav Petkov 465b72e7464SBorislav Petkov /* IA32_HWP_REQUEST */ 466b72e7464SBorislav Petkov #define HWP_MIN_PERF(x) (x & 0xff) 467b72e7464SBorislav Petkov #define HWP_MAX_PERF(x) ((x & 0xff) << 8) 468b72e7464SBorislav Petkov #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 4692fc49cb0SLen Brown #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) 4708d84e906SLen Brown #define HWP_EPP_PERFORMANCE 0x00 4718d84e906SLen Brown #define HWP_EPP_BALANCE_PERFORMANCE 0x80 4728d84e906SLen Brown #define HWP_EPP_BALANCE_POWERSAVE 0xC0 4738d84e906SLen Brown #define HWP_EPP_POWERSAVE 0xFF 4742fc49cb0SLen Brown #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) 4752fc49cb0SLen Brown #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) 476b72e7464SBorislav Petkov 477b72e7464SBorislav Petkov /* IA32_HWP_STATUS */ 478b72e7464SBorislav Petkov #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 479b72e7464SBorislav Petkov #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 480b72e7464SBorislav Petkov 481b72e7464SBorislav Petkov /* IA32_HWP_INTERRUPT */ 482b72e7464SBorislav Petkov #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 483b72e7464SBorislav Petkov #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 484b72e7464SBorislav Petkov 485b72e7464SBorislav Petkov #define MSR_AMD64_MC0_MASK 0xc0010044 486b72e7464SBorislav Petkov 487b72e7464SBorislav Petkov #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 488b72e7464SBorislav Petkov #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 489b72e7464SBorislav Petkov #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 490b72e7464SBorislav Petkov #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 491b72e7464SBorislav Petkov 492b72e7464SBorislav Petkov #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 493b72e7464SBorislav Petkov 494b72e7464SBorislav Petkov /* These are consecutive and not in the normal 4er MCE bank block */ 495b72e7464SBorislav Petkov #define MSR_IA32_MC0_CTL2 0x00000280 496b72e7464SBorislav Petkov #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 497b72e7464SBorislav Petkov 498b72e7464SBorislav Petkov #define MSR_P6_PERFCTR0 0x000000c1 499b72e7464SBorislav Petkov #define MSR_P6_PERFCTR1 0x000000c2 500b72e7464SBorislav Petkov #define MSR_P6_EVNTSEL0 0x00000186 501b72e7464SBorislav Petkov #define MSR_P6_EVNTSEL1 0x00000187 502b72e7464SBorislav Petkov 503b72e7464SBorislav Petkov #define MSR_KNC_PERFCTR0 0x00000020 504b72e7464SBorislav Petkov #define MSR_KNC_PERFCTR1 0x00000021 505b72e7464SBorislav Petkov #define MSR_KNC_EVNTSEL0 0x00000028 506b72e7464SBorislav Petkov #define MSR_KNC_EVNTSEL1 0x00000029 507b72e7464SBorislav Petkov 508b72e7464SBorislav Petkov /* Alternative perfctr range with full access. */ 509b72e7464SBorislav Petkov #define MSR_IA32_PMC0 0x000004c1 510b72e7464SBorislav Petkov 51142880f72SAlexander Shishkin /* Auto-reload via MSR instead of DS area */ 51242880f72SAlexander Shishkin #define MSR_RELOAD_PMC0 0x000014c1 51342880f72SAlexander Shishkin #define MSR_RELOAD_FIXED_CTR0 0x00001309 51442880f72SAlexander Shishkin 515342061c5SBorislav Petkov /* 516342061c5SBorislav Petkov * AMD64 MSRs. Not complete. See the architecture manual for a more 517342061c5SBorislav Petkov * complete list. 518342061c5SBorislav Petkov */ 519b72e7464SBorislav Petkov #define MSR_AMD64_PATCH_LEVEL 0x0000008b 520b72e7464SBorislav Petkov #define MSR_AMD64_TSC_RATIO 0xc0000104 521b72e7464SBorislav Petkov #define MSR_AMD64_NB_CFG 0xc001001f 522b72e7464SBorislav Petkov #define MSR_AMD64_PATCH_LOADER 0xc0010020 523342061c5SBorislav Petkov #define MSR_AMD_PERF_CTL 0xc0010062 524342061c5SBorislav Petkov #define MSR_AMD_PERF_STATUS 0xc0010063 525342061c5SBorislav Petkov #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 526b72e7464SBorislav Petkov #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 527b72e7464SBorislav Petkov #define MSR_AMD64_OSVW_STATUS 0xc0010141 5284e3f77d8SJan Beulich #define MSR_AMD_PPIN_CTL 0xc00102f0 5294e3f77d8SJan Beulich #define MSR_AMD_PPIN 0xc00102f1 5301068ed45SBorislav Petkov #define MSR_AMD64_CPUID_FN_1 0xc0011004 531b72e7464SBorislav Petkov #define MSR_AMD64_LS_CFG 0xc0011020 532b72e7464SBorislav Petkov #define MSR_AMD64_DC_CFG 0xc0011022 533b72e7464SBorislav Petkov #define MSR_AMD64_BU_CFG2 0xc001102a 534b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCHCTL 0xc0011030 535b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 536b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 537b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCH_REG_COUNT 3 538b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 539b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPCTL 0xc0011033 540b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPRIP 0xc0011034 541b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA 0xc0011035 542b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA2 0xc0011036 543b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA3 0xc0011037 544b72e7464SBorislav Petkov #define MSR_AMD64_IBSDCLINAD 0xc0011038 545b72e7464SBorislav Petkov #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 546b72e7464SBorislav Petkov #define MSR_AMD64_IBSOP_REG_COUNT 7 547b72e7464SBorislav Petkov #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 548b72e7464SBorislav Petkov #define MSR_AMD64_IBSCTL 0xc001103a 549b72e7464SBorislav Petkov #define MSR_AMD64_IBSBRTARGET 0xc001103b 55036e1be8aSKim Phillips #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c 551b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA4 0xc001103d 552b72e7464SBorislav Petkov #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 55339150352SMaxim Levitsky #define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b 55469372cf0STom Lendacky #define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e 55529dcc60fSJoerg Roedel #define MSR_AMD64_SEV_ES_GHCB 0xc0010130 5561958b5fcSTom Lendacky #define MSR_AMD64_SEV 0xc0010131 5571958b5fcSTom Lendacky #define MSR_AMD64_SEV_ENABLED_BIT 0 558b57de6cdSJoerg Roedel #define MSR_AMD64_SEV_ES_ENABLED_BIT 1 559f742b90eSBrijesh Singh #define MSR_AMD64_SEV_SNP_ENABLED_BIT 2 5601958b5fcSTom Lendacky #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) 561b57de6cdSJoerg Roedel #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) 562f742b90eSBrijesh Singh #define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) 563b72e7464SBorislav Petkov 56411fb0683STom Lendacky #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f 56511fb0683STom Lendacky 56689aa94b4SHuang Rui /* AMD Collaborative Processor Performance Control MSRs */ 56789aa94b4SHuang Rui #define MSR_AMD_CPPC_CAP1 0xc00102b0 56889aa94b4SHuang Rui #define MSR_AMD_CPPC_ENABLE 0xc00102b1 56989aa94b4SHuang Rui #define MSR_AMD_CPPC_CAP2 0xc00102b2 57089aa94b4SHuang Rui #define MSR_AMD_CPPC_REQ 0xc00102b3 57189aa94b4SHuang Rui #define MSR_AMD_CPPC_STATUS 0xc00102b4 57289aa94b4SHuang Rui 57389aa94b4SHuang Rui #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) 57489aa94b4SHuang Rui #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) 57589aa94b4SHuang Rui #define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff) 57689aa94b4SHuang Rui #define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff) 57789aa94b4SHuang Rui 57889aa94b4SHuang Rui #define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0) 57989aa94b4SHuang Rui #define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) 58089aa94b4SHuang Rui #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) 58189aa94b4SHuang Rui #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) 58289aa94b4SHuang Rui 583089be16dSSandipan Das /* AMD Performance Counter Global Status and Control MSRs */ 584089be16dSSandipan Das #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 585089be16dSSandipan Das #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 586089be16dSSandipan Das #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 587089be16dSSandipan Das 588*ca5b7c0dSSandipan Das /* AMD Last Branch Record MSRs */ 589*ca5b7c0dSSandipan Das #define MSR_AMD64_LBR_SELECT 0xc000010e 590*ca5b7c0dSSandipan Das 591aaf24884SHuang Rui /* Fam 17h MSRs */ 592aaf24884SHuang Rui #define MSR_F17H_IRPERF 0xc00000e9 593aaf24884SHuang Rui 594d7caac99SPeter Zijlstra #define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3 595d7caac99SPeter Zijlstra #define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1) 596d7caac99SPeter Zijlstra 597b72e7464SBorislav Petkov /* Fam 16h MSRs */ 598b72e7464SBorislav Petkov #define MSR_F16H_L2I_PERF_CTL 0xc0010230 599b72e7464SBorislav Petkov #define MSR_F16H_L2I_PERF_CTR 0xc0010231 600b72e7464SBorislav Petkov #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 601b72e7464SBorislav Petkov #define MSR_F16H_DR2_ADDR_MASK 0xc001101a 602b72e7464SBorislav Petkov #define MSR_F16H_DR3_ADDR_MASK 0xc001101b 603b72e7464SBorislav Petkov #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 604b72e7464SBorislav Petkov 605b72e7464SBorislav Petkov /* Fam 15h MSRs */ 60699e40204SBorislav Petkov #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a 60799e40204SBorislav Petkov #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b 608b72e7464SBorislav Petkov #define MSR_F15H_PERF_CTL 0xc0010200 609e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 610e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 611e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 612e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 613e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 614e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 615e84b7119SJanakarajan Natarajan 616b72e7464SBorislav Petkov #define MSR_F15H_PERF_CTR 0xc0010201 617e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 618e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 619e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 620e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 621e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 622e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 623e84b7119SJanakarajan Natarajan 624b72e7464SBorislav Petkov #define MSR_F15H_NB_PERF_CTL 0xc0010240 625b72e7464SBorislav Petkov #define MSR_F15H_NB_PERF_CTR 0xc0010241 6268a224261SHuang Rui #define MSR_F15H_PTSC 0xc0010280 627ae8b7875SBorislav Petkov #define MSR_F15H_IC_CFG 0xc0011021 6280e1b869fSEduardo Habkost #define MSR_F15H_EX_CFG 0xc001102c 629b72e7464SBorislav Petkov 630b72e7464SBorislav Petkov /* Fam 10h MSRs */ 631b72e7464SBorislav Petkov #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 632b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_ENABLE (1<<0) 633b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 634b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 635b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 636b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BASE_SHIFT 20 637b72e7464SBorislav Petkov #define MSR_FAM10H_NODE_ID 0xc001100c 638e4d0e84eSTom Lendacky #define MSR_F10H_DECFG 0xc0011029 639e4d0e84eSTom Lendacky #define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1 6409c6a73c7STom Lendacky #define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT) 641b72e7464SBorislav Petkov 642b72e7464SBorislav Petkov /* K8 MSRs */ 643b72e7464SBorislav Petkov #define MSR_K8_TOP_MEM1 0xc001001a 644b72e7464SBorislav Petkov #define MSR_K8_TOP_MEM2 0xc001001d 645059e5c32SBrijesh Singh #define MSR_AMD64_SYSCFG 0xc0010010 646059e5c32SBrijesh Singh #define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23 647059e5c32SBrijesh Singh #define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT) 648b72e7464SBorislav Petkov #define MSR_K8_INT_PENDING_MSG 0xc0010055 649b72e7464SBorislav Petkov /* C1E active bits in int pending message */ 650b72e7464SBorislav Petkov #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 651b72e7464SBorislav Petkov #define MSR_K8_TSEG_ADDR 0xc0010112 6523afb1121SPaolo Bonzini #define MSR_K8_TSEG_MASK 0xc0010113 653b72e7464SBorislav Petkov #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 654b72e7464SBorislav Petkov #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 655b72e7464SBorislav Petkov #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 656b72e7464SBorislav Petkov 657b72e7464SBorislav Petkov /* K7 MSRs */ 658b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL0 0xc0010000 659b72e7464SBorislav Petkov #define MSR_K7_PERFCTR0 0xc0010004 660b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL1 0xc0010001 661b72e7464SBorislav Petkov #define MSR_K7_PERFCTR1 0xc0010005 662b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL2 0xc0010002 663b72e7464SBorislav Petkov #define MSR_K7_PERFCTR2 0xc0010006 664b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL3 0xc0010003 665b72e7464SBorislav Petkov #define MSR_K7_PERFCTR3 0xc0010007 666b72e7464SBorislav Petkov #define MSR_K7_CLK_CTL 0xc001001b 667b72e7464SBorislav Petkov #define MSR_K7_HWCR 0xc0010015 66818c71ce9STom Lendacky #define MSR_K7_HWCR_SMMLOCK_BIT 0 66918c71ce9STom Lendacky #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) 67021b5ee59SKim Phillips #define MSR_K7_HWCR_IRPERF_EN_BIT 30 67121b5ee59SKim Phillips #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) 672b72e7464SBorislav Petkov #define MSR_K7_FID_VID_CTL 0xc0010041 673b72e7464SBorislav Petkov #define MSR_K7_FID_VID_STATUS 0xc0010042 674b72e7464SBorislav Petkov 675b72e7464SBorislav Petkov /* K6 MSRs */ 676b72e7464SBorislav Petkov #define MSR_K6_WHCR 0xc0000082 677b72e7464SBorislav Petkov #define MSR_K6_UWCCR 0xc0000085 678b72e7464SBorislav Petkov #define MSR_K6_EPMR 0xc0000086 679b72e7464SBorislav Petkov #define MSR_K6_PSOR 0xc0000087 680b72e7464SBorislav Petkov #define MSR_K6_PFIR 0xc0000088 681b72e7464SBorislav Petkov 682b72e7464SBorislav Petkov /* Centaur-Hauls/IDT defined MSRs. */ 683b72e7464SBorislav Petkov #define MSR_IDT_FCR1 0x00000107 684b72e7464SBorislav Petkov #define MSR_IDT_FCR2 0x00000108 685b72e7464SBorislav Petkov #define MSR_IDT_FCR3 0x00000109 686b72e7464SBorislav Petkov #define MSR_IDT_FCR4 0x0000010a 687b72e7464SBorislav Petkov 688b72e7464SBorislav Petkov #define MSR_IDT_MCR0 0x00000110 689b72e7464SBorislav Petkov #define MSR_IDT_MCR1 0x00000111 690b72e7464SBorislav Petkov #define MSR_IDT_MCR2 0x00000112 691b72e7464SBorislav Petkov #define MSR_IDT_MCR3 0x00000113 692b72e7464SBorislav Petkov #define MSR_IDT_MCR4 0x00000114 693b72e7464SBorislav Petkov #define MSR_IDT_MCR5 0x00000115 694b72e7464SBorislav Petkov #define MSR_IDT_MCR6 0x00000116 695b72e7464SBorislav Petkov #define MSR_IDT_MCR7 0x00000117 696b72e7464SBorislav Petkov #define MSR_IDT_MCR_CTRL 0x00000120 697b72e7464SBorislav Petkov 698b72e7464SBorislav Petkov /* VIA Cyrix defined MSRs*/ 699b72e7464SBorislav Petkov #define MSR_VIA_FCR 0x00001107 700b72e7464SBorislav Petkov #define MSR_VIA_LONGHAUL 0x0000110a 701b72e7464SBorislav Petkov #define MSR_VIA_RNG 0x0000110b 702b72e7464SBorislav Petkov #define MSR_VIA_BCR2 0x00001147 703b72e7464SBorislav Petkov 704b72e7464SBorislav Petkov /* Transmeta defined MSRs */ 705b72e7464SBorislav Petkov #define MSR_TMTA_LONGRUN_CTRL 0x80868010 706b72e7464SBorislav Petkov #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 707b72e7464SBorislav Petkov #define MSR_TMTA_LRTI_READOUT 0x80868018 708b72e7464SBorislav Petkov #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 709b72e7464SBorislav Petkov 710b72e7464SBorislav Petkov /* Intel defined MSRs. */ 711b72e7464SBorislav Petkov #define MSR_IA32_P5_MC_ADDR 0x00000000 712b72e7464SBorislav Petkov #define MSR_IA32_P5_MC_TYPE 0x00000001 713b72e7464SBorislav Petkov #define MSR_IA32_TSC 0x00000010 714b72e7464SBorislav Petkov #define MSR_IA32_PLATFORM_ID 0x00000017 715b72e7464SBorislav Petkov #define MSR_IA32_EBL_CR_POWERON 0x0000002a 716b72e7464SBorislav Petkov #define MSR_EBC_FREQUENCY_ID 0x0000002c 717b72e7464SBorislav Petkov #define MSR_SMI_COUNT 0x00000034 71832ad73dbSSean Christopherson 71932ad73dbSSean Christopherson /* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */ 72032ad73dbSSean Christopherson #define MSR_IA32_FEAT_CTL 0x0000003a 72132ad73dbSSean Christopherson #define FEAT_CTL_LOCKED BIT(0) 72232ad73dbSSean Christopherson #define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1) 72332ad73dbSSean Christopherson #define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2) 724d205e0f1SSean Christopherson #define FEAT_CTL_SGX_LC_ENABLED BIT(17) 725e7b6385bSSean Christopherson #define FEAT_CTL_SGX_ENABLED BIT(18) 72632ad73dbSSean Christopherson #define FEAT_CTL_LMCE_ENABLED BIT(20) 72732ad73dbSSean Christopherson 728b72e7464SBorislav Petkov #define MSR_IA32_TSC_ADJUST 0x0000003b 729b72e7464SBorislav Petkov #define MSR_IA32_BNDCFGS 0x00000d90 730b72e7464SBorislav Petkov 7314531662dSJim Mattson #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 7324531662dSJim Mattson 733dae1bd58SChang S. Bae #define MSR_IA32_XFD 0x000001c4 734dae1bd58SChang S. Bae #define MSR_IA32_XFD_ERR 0x000001c5 735b72e7464SBorislav Petkov #define MSR_IA32_XSS 0x00000da0 736b72e7464SBorislav Petkov 737b72e7464SBorislav Petkov #define MSR_IA32_APICBASE 0x0000001b 738b72e7464SBorislav Petkov #define MSR_IA32_APICBASE_BSP (1<<8) 739b72e7464SBorislav Petkov #define MSR_IA32_APICBASE_ENABLE (1<<11) 740b72e7464SBorislav Petkov #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 741b72e7464SBorislav Petkov 742b72e7464SBorislav Petkov #define MSR_IA32_UCODE_WRITE 0x00000079 743b72e7464SBorislav Petkov #define MSR_IA32_UCODE_REV 0x0000008b 744b72e7464SBorislav Petkov 745d205e0f1SSean Christopherson /* Intel SGX Launch Enclave Public Key Hash MSRs */ 746d205e0f1SSean Christopherson #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C 747d205e0f1SSean Christopherson #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D 748d205e0f1SSean Christopherson #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E 749d205e0f1SSean Christopherson #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F 750d205e0f1SSean Christopherson 751b72e7464SBorislav Petkov #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 752b72e7464SBorislav Petkov #define MSR_IA32_SMBASE 0x0000009e 753b72e7464SBorislav Petkov 754b72e7464SBorislav Petkov #define MSR_IA32_PERF_STATUS 0x00000198 755b72e7464SBorislav Petkov #define MSR_IA32_PERF_CTL 0x00000199 756b72e7464SBorislav Petkov #define INTEL_PERF_CTL_MASK 0xffff 757b72e7464SBorislav Petkov 758ada54345SStephane Eranian /* AMD Branch Sampling configuration */ 759ada54345SStephane Eranian #define MSR_AMD_DBG_EXTN_CFG 0xc000010f 760ada54345SStephane Eranian #define MSR_AMD_SAMP_BR_FROM 0xc0010300 761ada54345SStephane Eranian 762*ca5b7c0dSSandipan Das #define DBG_EXTN_CFG_LBRV2EN BIT_ULL(6) 763*ca5b7c0dSSandipan Das 764b72e7464SBorislav Petkov #define MSR_IA32_MPERF 0x000000e7 765b72e7464SBorislav Petkov #define MSR_IA32_APERF 0x000000e8 766b72e7464SBorislav Petkov 767b72e7464SBorislav Petkov #define MSR_IA32_THERM_CONTROL 0x0000019a 768b72e7464SBorislav Petkov #define MSR_IA32_THERM_INTERRUPT 0x0000019b 769b72e7464SBorislav Petkov 770b72e7464SBorislav Petkov #define THERM_INT_HIGH_ENABLE (1 << 0) 771b72e7464SBorislav Petkov #define THERM_INT_LOW_ENABLE (1 << 1) 772b72e7464SBorislav Petkov #define THERM_INT_PLN_ENABLE (1 << 24) 773b72e7464SBorislav Petkov 774b72e7464SBorislav Petkov #define MSR_IA32_THERM_STATUS 0x0000019c 775b72e7464SBorislav Petkov 776b72e7464SBorislav Petkov #define THERM_STATUS_PROCHOT (1 << 0) 777b72e7464SBorislav Petkov #define THERM_STATUS_POWER_LIMIT (1 << 10) 778b72e7464SBorislav Petkov 779b72e7464SBorislav Petkov #define MSR_THERM2_CTL 0x0000019d 780b72e7464SBorislav Petkov 781b72e7464SBorislav Petkov #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 782b72e7464SBorislav Petkov 783b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE 0x000001a0 784b72e7464SBorislav Petkov 785b72e7464SBorislav Petkov #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 786b72e7464SBorislav Petkov 78798af7459SLen Brown #define MSR_MISC_FEATURE_CONTROL 0x000001a4 788b72e7464SBorislav Petkov #define MSR_MISC_PWR_MGMT 0x000001aa 789b72e7464SBorislav Petkov 790b72e7464SBorislav Petkov #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 791b72e7464SBorislav Petkov #define ENERGY_PERF_BIAS_PERFORMANCE 0 792d0117a0eSLen Brown #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 793b72e7464SBorislav Petkov #define ENERGY_PERF_BIAS_NORMAL 6 794d0117a0eSLen Brown #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 795b72e7464SBorislav Petkov #define ENERGY_PERF_BIAS_POWERSAVE 15 796b72e7464SBorislav Petkov 797b72e7464SBorislav Petkov #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 798b72e7464SBorislav Petkov 799b72e7464SBorislav Petkov #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 800b72e7464SBorislav Petkov #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 8017b8f40b3SRicardo Neri #define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26) 802b72e7464SBorislav Petkov 803b72e7464SBorislav Petkov #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 804b72e7464SBorislav Petkov 805b72e7464SBorislav Petkov #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 806b72e7464SBorislav Petkov #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 807b72e7464SBorislav Petkov #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 8087b8f40b3SRicardo Neri #define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25) 809b72e7464SBorislav Petkov 810b72e7464SBorislav Petkov /* Thermal Thresholds Support */ 811b72e7464SBorislav Petkov #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 812b72e7464SBorislav Petkov #define THERM_SHIFT_THRESHOLD0 8 813b72e7464SBorislav Petkov #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 814b72e7464SBorislav Petkov #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 815b72e7464SBorislav Petkov #define THERM_SHIFT_THRESHOLD1 16 816b72e7464SBorislav Petkov #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 817b72e7464SBorislav Petkov #define THERM_STATUS_THRESHOLD0 (1 << 6) 818b72e7464SBorislav Petkov #define THERM_LOG_THRESHOLD0 (1 << 7) 819b72e7464SBorislav Petkov #define THERM_STATUS_THRESHOLD1 (1 << 8) 820b72e7464SBorislav Petkov #define THERM_LOG_THRESHOLD1 (1 << 9) 821b72e7464SBorislav Petkov 822b72e7464SBorislav Petkov /* MISC_ENABLE bits: architectural */ 823b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 824b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 825b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 826b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 827b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 828b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 829b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 830b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 831b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 832b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 833b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 834b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 835b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 836b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 837b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 838b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 839b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 840b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 841b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 842b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 843b72e7464SBorislav Petkov 844b72e7464SBorislav Petkov /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 845b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 846b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 847b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 848b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 849b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 850b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 851b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 852b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 853b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 854b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 855b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 856b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 857b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 858b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 859b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 860b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 861b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 862b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 863b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 864b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 865b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 866b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 867b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 868b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 869b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 870b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 871b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 872b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 873b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 874b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 875b72e7464SBorislav Petkov 876ab6d9468SKyle Huey /* MISC_FEATURES_ENABLES non-architectural features */ 877ab6d9468SKyle Huey #define MSR_MISC_FEATURES_ENABLES 0x00000140 878ae47eda9SGrzegorz Andrejczuk 879e9ea1e7fSKyle Huey #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 880e9ea1e7fSKyle Huey #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) 881ab6d9468SKyle Huey #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 882ae47eda9SGrzegorz Andrejczuk 883b72e7464SBorislav Petkov #define MSR_IA32_TSC_DEADLINE 0x000006E0 884b72e7464SBorislav Petkov 88552f64909SPeter Zijlstra (Intel) 88652f64909SPeter Zijlstra (Intel) #define MSR_TSX_FORCE_ABORT 0x0000010F 88752f64909SPeter Zijlstra (Intel) 88852f64909SPeter Zijlstra (Intel) #define MSR_TFA_RTM_FORCE_ABORT_BIT 0 88952f64909SPeter Zijlstra (Intel) #define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) 8901348924bSPawan Gupta #define MSR_TFA_TSX_CPUID_CLEAR_BIT 1 8911348924bSPawan Gupta #define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT) 8921348924bSPawan Gupta #define MSR_TFA_SDV_ENABLE_RTM_BIT 2 8931348924bSPawan Gupta #define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT) 89452f64909SPeter Zijlstra (Intel) 895b72e7464SBorislav Petkov /* P4/Xeon+ specific */ 896b72e7464SBorislav Petkov #define MSR_IA32_MCG_EAX 0x00000180 897b72e7464SBorislav Petkov #define MSR_IA32_MCG_EBX 0x00000181 898b72e7464SBorislav Petkov #define MSR_IA32_MCG_ECX 0x00000182 899b72e7464SBorislav Petkov #define MSR_IA32_MCG_EDX 0x00000183 900b72e7464SBorislav Petkov #define MSR_IA32_MCG_ESI 0x00000184 901b72e7464SBorislav Petkov #define MSR_IA32_MCG_EDI 0x00000185 902b72e7464SBorislav Petkov #define MSR_IA32_MCG_EBP 0x00000186 903b72e7464SBorislav Petkov #define MSR_IA32_MCG_ESP 0x00000187 904b72e7464SBorislav Petkov #define MSR_IA32_MCG_EFLAGS 0x00000188 905b72e7464SBorislav Petkov #define MSR_IA32_MCG_EIP 0x00000189 906b72e7464SBorislav Petkov #define MSR_IA32_MCG_RESERVED 0x0000018a 907b72e7464SBorislav Petkov 908b72e7464SBorislav Petkov /* Pentium IV performance counter MSRs */ 909b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR0 0x00000300 910b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR1 0x00000301 911b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR2 0x00000302 912b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR3 0x00000303 913b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR0 0x00000304 914b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR1 0x00000305 915b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR2 0x00000306 916b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR3 0x00000307 917b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR0 0x00000308 918b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR1 0x00000309 919b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR2 0x0000030a 920b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR3 0x0000030b 921b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR0 0x0000030c 922b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR1 0x0000030d 923b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR2 0x0000030e 924b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR3 0x0000030f 925b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR4 0x00000310 926b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR5 0x00000311 927b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR0 0x00000360 928b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR1 0x00000361 929b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR2 0x00000362 930b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR3 0x00000363 931b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR0 0x00000364 932b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR1 0x00000365 933b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR2 0x00000366 934b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR3 0x00000367 935b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR0 0x00000368 936b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR1 0x00000369 937b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR2 0x0000036a 938b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR3 0x0000036b 939b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR0 0x0000036c 940b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR1 0x0000036d 941b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR2 0x0000036e 942b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR3 0x0000036f 943b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR4 0x00000370 944b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR5 0x00000371 945b72e7464SBorislav Petkov #define MSR_P4_ALF_ESCR0 0x000003ca 946b72e7464SBorislav Petkov #define MSR_P4_ALF_ESCR1 0x000003cb 947b72e7464SBorislav Petkov #define MSR_P4_BPU_ESCR0 0x000003b2 948b72e7464SBorislav Petkov #define MSR_P4_BPU_ESCR1 0x000003b3 949b72e7464SBorislav Petkov #define MSR_P4_BSU_ESCR0 0x000003a0 950b72e7464SBorislav Petkov #define MSR_P4_BSU_ESCR1 0x000003a1 951b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR0 0x000003b8 952b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR1 0x000003b9 953b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR2 0x000003cc 954b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR3 0x000003cd 955b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR4 0x000003e0 956b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR5 0x000003e1 957b72e7464SBorislav Petkov #define MSR_P4_DAC_ESCR0 0x000003a8 958b72e7464SBorislav Petkov #define MSR_P4_DAC_ESCR1 0x000003a9 959b72e7464SBorislav Petkov #define MSR_P4_FIRM_ESCR0 0x000003a4 960b72e7464SBorislav Petkov #define MSR_P4_FIRM_ESCR1 0x000003a5 961b72e7464SBorislav Petkov #define MSR_P4_FLAME_ESCR0 0x000003a6 962b72e7464SBorislav Petkov #define MSR_P4_FLAME_ESCR1 0x000003a7 963b72e7464SBorislav Petkov #define MSR_P4_FSB_ESCR0 0x000003a2 964b72e7464SBorislav Petkov #define MSR_P4_FSB_ESCR1 0x000003a3 965b72e7464SBorislav Petkov #define MSR_P4_IQ_ESCR0 0x000003ba 966b72e7464SBorislav Petkov #define MSR_P4_IQ_ESCR1 0x000003bb 967b72e7464SBorislav Petkov #define MSR_P4_IS_ESCR0 0x000003b4 968b72e7464SBorislav Petkov #define MSR_P4_IS_ESCR1 0x000003b5 969b72e7464SBorislav Petkov #define MSR_P4_ITLB_ESCR0 0x000003b6 970b72e7464SBorislav Petkov #define MSR_P4_ITLB_ESCR1 0x000003b7 971b72e7464SBorislav Petkov #define MSR_P4_IX_ESCR0 0x000003c8 972b72e7464SBorislav Petkov #define MSR_P4_IX_ESCR1 0x000003c9 973b72e7464SBorislav Petkov #define MSR_P4_MOB_ESCR0 0x000003aa 974b72e7464SBorislav Petkov #define MSR_P4_MOB_ESCR1 0x000003ab 975b72e7464SBorislav Petkov #define MSR_P4_MS_ESCR0 0x000003c0 976b72e7464SBorislav Petkov #define MSR_P4_MS_ESCR1 0x000003c1 977b72e7464SBorislav Petkov #define MSR_P4_PMH_ESCR0 0x000003ac 978b72e7464SBorislav Petkov #define MSR_P4_PMH_ESCR1 0x000003ad 979b72e7464SBorislav Petkov #define MSR_P4_RAT_ESCR0 0x000003bc 980b72e7464SBorislav Petkov #define MSR_P4_RAT_ESCR1 0x000003bd 981b72e7464SBorislav Petkov #define MSR_P4_SAAT_ESCR0 0x000003ae 982b72e7464SBorislav Petkov #define MSR_P4_SAAT_ESCR1 0x000003af 983b72e7464SBorislav Petkov #define MSR_P4_SSU_ESCR0 0x000003be 984b72e7464SBorislav Petkov #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 985b72e7464SBorislav Petkov 986b72e7464SBorislav Petkov #define MSR_P4_TBPU_ESCR0 0x000003c2 987b72e7464SBorislav Petkov #define MSR_P4_TBPU_ESCR1 0x000003c3 988b72e7464SBorislav Petkov #define MSR_P4_TC_ESCR0 0x000003c4 989b72e7464SBorislav Petkov #define MSR_P4_TC_ESCR1 0x000003c5 990b72e7464SBorislav Petkov #define MSR_P4_U2L_ESCR0 0x000003b0 991b72e7464SBorislav Petkov #define MSR_P4_U2L_ESCR1 0x000003b1 992b72e7464SBorislav Petkov 993b72e7464SBorislav Petkov #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 994b72e7464SBorislav Petkov 995b72e7464SBorislav Petkov /* Intel Core-based CPU performance counters */ 996b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 997b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 998b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 9997b2c05a1SKan Liang #define MSR_CORE_PERF_FIXED_CTR3 0x0000030c 1000b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 1001b72e7464SBorislav Petkov #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 1002b72e7464SBorislav Petkov #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 1003b72e7464SBorislav Petkov #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 1004b72e7464SBorislav Petkov 100559a854e2SKan Liang #define MSR_PERF_METRICS 0x00000329 100659a854e2SKan Liang 10078479e04eSLuwei Kang /* PERF_GLOBAL_OVF_CTL bits */ 10088479e04eSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55 10098479e04eSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT) 1010c715eb9fSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62 1011c715eb9fSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT) 1012c715eb9fSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 1013c715eb9fSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) 10148479e04eSLuwei Kang 1015b72e7464SBorislav Petkov /* Geode defined MSRs */ 1016b72e7464SBorislav Petkov #define MSR_GEODE_BUSCONT_CONF0 0x00001900 1017b72e7464SBorislav Petkov 1018b72e7464SBorislav Petkov /* Intel VT MSRs */ 1019b72e7464SBorislav Petkov #define MSR_IA32_VMX_BASIC 0x00000480 1020b72e7464SBorislav Petkov #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 1021b72e7464SBorislav Petkov #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 1022b72e7464SBorislav Petkov #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 1023b72e7464SBorislav Petkov #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 1024b72e7464SBorislav Petkov #define MSR_IA32_VMX_MISC 0x00000485 1025b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 1026b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 1027b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 1028b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 1029b72e7464SBorislav Petkov #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 1030b72e7464SBorislav Petkov #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 1031b72e7464SBorislav Petkov #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 1032b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 1033b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 1034b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 1035b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 1036b72e7464SBorislav Petkov #define MSR_IA32_VMX_VMFUNC 0x00000491 1037465932dbSRobert Hoo #define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492 1038b72e7464SBorislav Petkov 1039b72e7464SBorislav Petkov /* VMX_BASIC bits and bitmasks */ 1040b72e7464SBorislav Petkov #define VMX_BASIC_VMCS_SIZE_SHIFT 32 1041b72e7464SBorislav Petkov #define VMX_BASIC_TRUE_CTLS (1ULL << 55) 1042b72e7464SBorislav Petkov #define VMX_BASIC_64 0x0001000000000000LLU 1043b72e7464SBorislav Petkov #define VMX_BASIC_MEM_TYPE_SHIFT 50 1044b72e7464SBorislav Petkov #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 1045b72e7464SBorislav Petkov #define VMX_BASIC_MEM_TYPE_WB 6LLU 1046b72e7464SBorislav Petkov #define VMX_BASIC_INOUT 0x0040000000000000LLU 1047b72e7464SBorislav Petkov 1048b72e7464SBorislav Petkov /* MSR_IA32_VMX_MISC bits */ 1049f99e3dafSChao Peng #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) 1050b72e7464SBorislav Petkov #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 1051b72e7464SBorislav Petkov #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 1052b72e7464SBorislav Petkov /* AMD-V MSRs */ 1053b72e7464SBorislav Petkov 1054b72e7464SBorislav Petkov #define MSR_VM_CR 0xc0010114 1055b72e7464SBorislav Petkov #define MSR_VM_IGNNE 0xc0010115 1056b72e7464SBorislav Petkov #define MSR_VM_HSAVE_PA 0xc0010117 1057b72e7464SBorislav Petkov 10587b8f40b3SRicardo Neri /* Hardware Feedback Interface */ 10597b8f40b3SRicardo Neri #define MSR_IA32_HW_FEEDBACK_PTR 0x17d0 10607b8f40b3SRicardo Neri #define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1 10617b8f40b3SRicardo Neri 1062b72e7464SBorislav Petkov #endif /* _ASM_X86_MSR_INDEX_H */ 1063