1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2b72e7464SBorislav Petkov #ifndef _ASM_X86_MSR_INDEX_H 3b72e7464SBorislav Petkov #define _ASM_X86_MSR_INDEX_H 4b72e7464SBorislav Petkov 5053080a9SBorislav Petkov /* 6053080a9SBorislav Petkov * CPU model specific register (MSR) numbers. 7053080a9SBorislav Petkov * 8053080a9SBorislav Petkov * Do not add new entries to this file unless the definitions are shared 9053080a9SBorislav Petkov * between multiple compilation units. 10053080a9SBorislav Petkov */ 11b72e7464SBorislav Petkov 12b72e7464SBorislav Petkov /* x86-64 specific MSRs */ 13b72e7464SBorislav Petkov #define MSR_EFER 0xc0000080 /* extended feature register */ 14b72e7464SBorislav Petkov #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 15b72e7464SBorislav Petkov #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 16b72e7464SBorislav Petkov #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 17b72e7464SBorislav Petkov #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 18b72e7464SBorislav Petkov #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 19b72e7464SBorislav Petkov #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 20b72e7464SBorislav Petkov #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 21b72e7464SBorislav Petkov #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 22b72e7464SBorislav Petkov 23b72e7464SBorislav Petkov /* EFER bits: */ 24b72e7464SBorislav Petkov #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 25b72e7464SBorislav Petkov #define _EFER_LME 8 /* Long mode enable */ 26b72e7464SBorislav Petkov #define _EFER_LMA 10 /* Long mode active (read-only) */ 27b72e7464SBorislav Petkov #define _EFER_NX 11 /* No execute enable */ 28b72e7464SBorislav Petkov #define _EFER_SVME 12 /* Enable virtualization */ 29b72e7464SBorislav Petkov #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 30b72e7464SBorislav Petkov #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 31b72e7464SBorislav Petkov 32b72e7464SBorislav Petkov #define EFER_SCE (1<<_EFER_SCE) 33b72e7464SBorislav Petkov #define EFER_LME (1<<_EFER_LME) 34b72e7464SBorislav Petkov #define EFER_LMA (1<<_EFER_LMA) 35b72e7464SBorislav Petkov #define EFER_NX (1<<_EFER_NX) 36b72e7464SBorislav Petkov #define EFER_SVME (1<<_EFER_SVME) 37b72e7464SBorislav Petkov #define EFER_LMSLE (1<<_EFER_LMSLE) 38b72e7464SBorislav Petkov #define EFER_FFXSR (1<<_EFER_FFXSR) 39b72e7464SBorislav Petkov 40b72e7464SBorislav Petkov /* Intel MSRs. Some also available on other CPUs */ 413f5a7896STony Luck 421e340c60SDavid Woodhouse #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 431e340c60SDavid Woodhouse #define SPEC_CTRL_IBRS (1 << 0) /* Indirect Branch Restricted Speculation */ 445bfbe3adSTim Chen #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ 455bfbe3adSTim Chen #define SPEC_CTRL_STIBP (1 << SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ 469f65fb29SKonrad Rzeszutek Wilk #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ 479f65fb29SKonrad Rzeszutek Wilk #define SPEC_CTRL_SSBD (1 << SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ 481e340c60SDavid Woodhouse 491e340c60SDavid Woodhouse #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 501e340c60SDavid Woodhouse #define PRED_CMD_IBPB (1 << 0) /* Indirect Branch Prediction Barrier */ 511e340c60SDavid Woodhouse 523f5a7896STony Luck #define MSR_PPIN_CTL 0x0000004e 533f5a7896STony Luck #define MSR_PPIN 0x0000004f 543f5a7896STony Luck 55b72e7464SBorislav Petkov #define MSR_IA32_PERFCTR0 0x000000c1 56b72e7464SBorislav Petkov #define MSR_IA32_PERFCTR1 0x000000c2 57b72e7464SBorislav Petkov #define MSR_FSB_FREQ 0x000000cd 585369a21eSLen Brown #define MSR_PLATFORM_INFO 0x000000ce 5990218ac7SKyle Huey #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 6090218ac7SKyle Huey #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) 61b72e7464SBorislav Petkov 6240496c8eSLen Brown #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 63b72e7464SBorislav Petkov #define NHM_C3_AUTO_DEMOTE (1UL << 25) 64b72e7464SBorislav Petkov #define NHM_C1_AUTO_DEMOTE (1UL << 26) 65b72e7464SBorislav Petkov #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 66a00072a2SMatt Turner #define SNB_C3_AUTO_UNDEMOTE (1UL << 27) 67a00072a2SMatt Turner #define SNB_C1_AUTO_UNDEMOTE (1UL << 28) 68b72e7464SBorislav Petkov 69b72e7464SBorislav Petkov #define MSR_MTRRcap 0x000000fe 701e340c60SDavid Woodhouse 711e340c60SDavid Woodhouse #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 721e340c60SDavid Woodhouse #define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to Meltdown */ 731e340c60SDavid Woodhouse #define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */ 748e0b2b91SPaolo Bonzini #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH (1 << 3) /* Skip L1D flush on vmentry */ 75240da953SKonrad Rzeszutek Wilk #define ARCH_CAP_SSB_NO (1 << 4) /* 7677243971SKonrad Rzeszutek Wilk * Not susceptible to Speculative Store Bypass 779f65fb29SKonrad Rzeszutek Wilk * attack, so no Speculative Store Bypass 789f65fb29SKonrad Rzeszutek Wilk * control required. 7977243971SKonrad Rzeszutek Wilk */ 801e340c60SDavid Woodhouse 813fa045beSPaolo Bonzini #define MSR_IA32_FLUSH_CMD 0x0000010b 823fa045beSPaolo Bonzini #define L1D_FLUSH (1 << 0) /* 833fa045beSPaolo Bonzini * Writeback and invalidate the 843fa045beSPaolo Bonzini * L1 data cache. 853fa045beSPaolo Bonzini */ 863fa045beSPaolo Bonzini 87b72e7464SBorislav Petkov #define MSR_IA32_BBL_CR_CTL 0x00000119 88b72e7464SBorislav Petkov #define MSR_IA32_BBL_CR_CTL3 0x0000011e 89b72e7464SBorislav Petkov 90b72e7464SBorislav Petkov #define MSR_IA32_SYSENTER_CS 0x00000174 91b72e7464SBorislav Petkov #define MSR_IA32_SYSENTER_ESP 0x00000175 92b72e7464SBorislav Petkov #define MSR_IA32_SYSENTER_EIP 0x00000176 93b72e7464SBorislav Petkov 94b72e7464SBorislav Petkov #define MSR_IA32_MCG_CAP 0x00000179 95b72e7464SBorislav Petkov #define MSR_IA32_MCG_STATUS 0x0000017a 96b72e7464SBorislav Petkov #define MSR_IA32_MCG_CTL 0x0000017b 97b72e7464SBorislav Petkov #define MSR_IA32_MCG_EXT_CTL 0x000004d0 98b72e7464SBorislav Petkov 99b72e7464SBorislav Petkov #define MSR_OFFCORE_RSP_0 0x000001a6 100b72e7464SBorislav Petkov #define MSR_OFFCORE_RSP_1 0x000001a7 101b72e7464SBorislav Petkov #define MSR_TURBO_RATIO_LIMIT 0x000001ad 102b72e7464SBorislav Petkov #define MSR_TURBO_RATIO_LIMIT1 0x000001ae 103b72e7464SBorislav Petkov #define MSR_TURBO_RATIO_LIMIT2 0x000001af 104b72e7464SBorislav Petkov 105b72e7464SBorislav Petkov #define MSR_LBR_SELECT 0x000001c8 106b72e7464SBorislav Petkov #define MSR_LBR_TOS 0x000001c9 107b72e7464SBorislav Petkov #define MSR_LBR_NHM_FROM 0x00000680 108b72e7464SBorislav Petkov #define MSR_LBR_NHM_TO 0x000006c0 109b72e7464SBorislav Petkov #define MSR_LBR_CORE_FROM 0x00000040 110b72e7464SBorislav Petkov #define MSR_LBR_CORE_TO 0x00000060 111b72e7464SBorislav Petkov 112b83ff1c8SAndi Kleen #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 113b83ff1c8SAndi Kleen #define LBR_INFO_MISPRED BIT_ULL(63) 114b83ff1c8SAndi Kleen #define LBR_INFO_IN_TX BIT_ULL(62) 115b83ff1c8SAndi Kleen #define LBR_INFO_ABORT BIT_ULL(61) 116b83ff1c8SAndi Kleen #define LBR_INFO_CYCLES 0xffff 117b83ff1c8SAndi Kleen 118b72e7464SBorislav Petkov #define MSR_IA32_PEBS_ENABLE 0x000003f1 119b72e7464SBorislav Petkov #define MSR_IA32_DS_AREA 0x00000600 120b72e7464SBorislav Petkov #define MSR_IA32_PERF_CAPABILITIES 0x00000345 121b72e7464SBorislav Petkov #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 122b72e7464SBorislav Petkov 123b72e7464SBorislav Petkov #define MSR_IA32_RTIT_CTL 0x00000570 124887eda13SChao Peng #define RTIT_CTL_TRACEEN BIT(0) 125887eda13SChao Peng #define RTIT_CTL_CYCLEACC BIT(1) 126887eda13SChao Peng #define RTIT_CTL_OS BIT(2) 127887eda13SChao Peng #define RTIT_CTL_USR BIT(3) 128887eda13SChao Peng #define RTIT_CTL_PWR_EVT_EN BIT(4) 129887eda13SChao Peng #define RTIT_CTL_FUP_ON_PTW BIT(5) 13069843a91SLuwei Kang #define RTIT_CTL_FABRIC_EN BIT(6) 131887eda13SChao Peng #define RTIT_CTL_CR3EN BIT(7) 132887eda13SChao Peng #define RTIT_CTL_TOPA BIT(8) 133887eda13SChao Peng #define RTIT_CTL_MTC_EN BIT(9) 134887eda13SChao Peng #define RTIT_CTL_TSC_EN BIT(10) 135887eda13SChao Peng #define RTIT_CTL_DISRETC BIT(11) 136887eda13SChao Peng #define RTIT_CTL_PTW_EN BIT(12) 137887eda13SChao Peng #define RTIT_CTL_BRANCH_EN BIT(13) 138887eda13SChao Peng #define RTIT_CTL_MTC_RANGE_OFFSET 14 139887eda13SChao Peng #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 140887eda13SChao Peng #define RTIT_CTL_CYC_THRESH_OFFSET 19 141887eda13SChao Peng #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 142887eda13SChao Peng #define RTIT_CTL_PSB_FREQ_OFFSET 24 143887eda13SChao Peng #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 144887eda13SChao Peng #define RTIT_CTL_ADDR0_OFFSET 32 145887eda13SChao Peng #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) 146887eda13SChao Peng #define RTIT_CTL_ADDR1_OFFSET 36 147887eda13SChao Peng #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) 148887eda13SChao Peng #define RTIT_CTL_ADDR2_OFFSET 40 149887eda13SChao Peng #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) 150887eda13SChao Peng #define RTIT_CTL_ADDR3_OFFSET 44 151887eda13SChao Peng #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) 152b72e7464SBorislav Petkov #define MSR_IA32_RTIT_STATUS 0x00000571 153887eda13SChao Peng #define RTIT_STATUS_FILTEREN BIT(0) 154887eda13SChao Peng #define RTIT_STATUS_CONTEXTEN BIT(1) 155887eda13SChao Peng #define RTIT_STATUS_TRIGGEREN BIT(2) 156887eda13SChao Peng #define RTIT_STATUS_BUFFOVF BIT(3) 157887eda13SChao Peng #define RTIT_STATUS_ERROR BIT(4) 158887eda13SChao Peng #define RTIT_STATUS_STOPPED BIT(5) 15969843a91SLuwei Kang #define RTIT_STATUS_BYTECNT_OFFSET 32 16069843a91SLuwei Kang #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) 161f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR0_A 0x00000580 162f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR0_B 0x00000581 163f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR1_A 0x00000582 164f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR1_B 0x00000583 165f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR2_A 0x00000584 166f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR2_B 0x00000585 167f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR3_A 0x00000586 168f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR3_B 0x00000587 169b72e7464SBorislav Petkov #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 170b72e7464SBorislav Petkov #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 171b72e7464SBorislav Petkov #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 172b72e7464SBorislav Petkov 173b72e7464SBorislav Petkov #define MSR_MTRRfix64K_00000 0x00000250 174b72e7464SBorislav Petkov #define MSR_MTRRfix16K_80000 0x00000258 175b72e7464SBorislav Petkov #define MSR_MTRRfix16K_A0000 0x00000259 176b72e7464SBorislav Petkov #define MSR_MTRRfix4K_C0000 0x00000268 177b72e7464SBorislav Petkov #define MSR_MTRRfix4K_C8000 0x00000269 178b72e7464SBorislav Petkov #define MSR_MTRRfix4K_D0000 0x0000026a 179b72e7464SBorislav Petkov #define MSR_MTRRfix4K_D8000 0x0000026b 180b72e7464SBorislav Petkov #define MSR_MTRRfix4K_E0000 0x0000026c 181b72e7464SBorislav Petkov #define MSR_MTRRfix4K_E8000 0x0000026d 182b72e7464SBorislav Petkov #define MSR_MTRRfix4K_F0000 0x0000026e 183b72e7464SBorislav Petkov #define MSR_MTRRfix4K_F8000 0x0000026f 184b72e7464SBorislav Petkov #define MSR_MTRRdefType 0x000002ff 185b72e7464SBorislav Petkov 186b72e7464SBorislav Petkov #define MSR_IA32_CR_PAT 0x00000277 187b72e7464SBorislav Petkov 188b72e7464SBorislav Petkov #define MSR_IA32_DEBUGCTLMSR 0x000001d9 189b72e7464SBorislav Petkov #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 190b72e7464SBorislav Petkov #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 191b72e7464SBorislav Petkov #define MSR_IA32_LASTINTFROMIP 0x000001dd 192b72e7464SBorislav Petkov #define MSR_IA32_LASTINTTOIP 0x000001de 193b72e7464SBorislav Petkov 194b72e7464SBorislav Petkov /* DEBUGCTLMSR bits (others vary by model): */ 195b72e7464SBorislav Petkov #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 196b9894a2fSKyle Huey #define DEBUGCTLMSR_BTF_SHIFT 1 197b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 198b72e7464SBorislav Petkov #define DEBUGCTLMSR_TR (1UL << 6) 199b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTS (1UL << 7) 200b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTINT (1UL << 8) 201b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 202b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 203b72e7464SBorislav Petkov #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 204af3bdb99SAndi Kleen #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) 2056089327fSKan Liang #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 2066089327fSKan Liang #define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 207b72e7464SBorislav Petkov 208d0dc8494SAndi Kleen #define MSR_PEBS_FRONTEND 0x000003f7 209d0dc8494SAndi Kleen 210b72e7464SBorislav Petkov #define MSR_IA32_POWER_CTL 0x000001fc 211b72e7464SBorislav Petkov 212b72e7464SBorislav Petkov #define MSR_IA32_MC0_CTL 0x00000400 213b72e7464SBorislav Petkov #define MSR_IA32_MC0_STATUS 0x00000401 214b72e7464SBorislav Petkov #define MSR_IA32_MC0_ADDR 0x00000402 215b72e7464SBorislav Petkov #define MSR_IA32_MC0_MISC 0x00000403 216b72e7464SBorislav Petkov 217b72e7464SBorislav Petkov /* C-state Residency Counters */ 218b72e7464SBorislav Petkov #define MSR_PKG_C3_RESIDENCY 0x000003f8 219b72e7464SBorislav Petkov #define MSR_PKG_C6_RESIDENCY 0x000003f9 2200539ba11SLen Brown #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 221b72e7464SBorislav Petkov #define MSR_PKG_C7_RESIDENCY 0x000003fa 222b72e7464SBorislav Petkov #define MSR_CORE_C3_RESIDENCY 0x000003fc 223b72e7464SBorislav Petkov #define MSR_CORE_C6_RESIDENCY 0x000003fd 224b72e7464SBorislav Petkov #define MSR_CORE_C7_RESIDENCY 0x000003fe 225b72e7464SBorislav Petkov #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 226b72e7464SBorislav Petkov #define MSR_PKG_C2_RESIDENCY 0x0000060d 227b72e7464SBorislav Petkov #define MSR_PKG_C8_RESIDENCY 0x00000630 228b72e7464SBorislav Petkov #define MSR_PKG_C9_RESIDENCY 0x00000631 229b72e7464SBorislav Petkov #define MSR_PKG_C10_RESIDENCY 0x00000632 230b72e7464SBorislav Petkov 2315a63426eSLen Brown /* Interrupt Response Limit */ 2325a63426eSLen Brown #define MSR_PKGC3_IRTL 0x0000060a 2335a63426eSLen Brown #define MSR_PKGC6_IRTL 0x0000060b 2345a63426eSLen Brown #define MSR_PKGC7_IRTL 0x0000060c 2355a63426eSLen Brown #define MSR_PKGC8_IRTL 0x00000633 2365a63426eSLen Brown #define MSR_PKGC9_IRTL 0x00000634 2375a63426eSLen Brown #define MSR_PKGC10_IRTL 0x00000635 2385a63426eSLen Brown 239b72e7464SBorislav Petkov /* Run Time Average Power Limiting (RAPL) Interface */ 240b72e7464SBorislav Petkov 241b72e7464SBorislav Petkov #define MSR_RAPL_POWER_UNIT 0x00000606 242b72e7464SBorislav Petkov 243b72e7464SBorislav Petkov #define MSR_PKG_POWER_LIMIT 0x00000610 244b72e7464SBorislav Petkov #define MSR_PKG_ENERGY_STATUS 0x00000611 245b72e7464SBorislav Petkov #define MSR_PKG_PERF_STATUS 0x00000613 246b72e7464SBorislav Petkov #define MSR_PKG_POWER_INFO 0x00000614 247b72e7464SBorislav Petkov 248b72e7464SBorislav Petkov #define MSR_DRAM_POWER_LIMIT 0x00000618 249b72e7464SBorislav Petkov #define MSR_DRAM_ENERGY_STATUS 0x00000619 250b72e7464SBorislav Petkov #define MSR_DRAM_PERF_STATUS 0x0000061b 251b72e7464SBorislav Petkov #define MSR_DRAM_POWER_INFO 0x0000061c 252b72e7464SBorislav Petkov 253b72e7464SBorislav Petkov #define MSR_PP0_POWER_LIMIT 0x00000638 254b72e7464SBorislav Petkov #define MSR_PP0_ENERGY_STATUS 0x00000639 255b72e7464SBorislav Petkov #define MSR_PP0_POLICY 0x0000063a 256b72e7464SBorislav Petkov #define MSR_PP0_PERF_STATUS 0x0000063b 257b72e7464SBorislav Petkov 258b72e7464SBorislav Petkov #define MSR_PP1_POWER_LIMIT 0x00000640 259b72e7464SBorislav Petkov #define MSR_PP1_ENERGY_STATUS 0x00000641 260b72e7464SBorislav Petkov #define MSR_PP1_POLICY 0x00000642 261b72e7464SBorislav Petkov 2624a6772f5SVladimir Zapolskiy /* Config TDP MSRs */ 26382bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_NOMINAL 0x00000648 26482bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 26582bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 26682bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_CONTROL 0x0000064B 26782bb70c5SRafael J. Wysocki #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 26882bb70c5SRafael J. Wysocki 269dcee75b3SSrinivas Pandruvada #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 270dcee75b3SSrinivas Pandruvada 271b72e7464SBorislav Petkov #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 272b72e7464SBorislav Petkov #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 273b72e7464SBorislav Petkov #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 274b72e7464SBorislav Petkov #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 275b72e7464SBorislav Petkov 276b72e7464SBorislav Petkov #define MSR_CORE_C1_RES 0x00000660 2770539ba11SLen Brown #define MSR_MODULE_C6_RES_MS 0x00000664 278b72e7464SBorislav Petkov 279b72e7464SBorislav Petkov #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 280b72e7464SBorislav Petkov #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 281b72e7464SBorislav Petkov 2828a34fd02SLen Brown #define MSR_ATOM_CORE_RATIOS 0x0000066a 2838a34fd02SLen Brown #define MSR_ATOM_CORE_VIDS 0x0000066b 2848a34fd02SLen Brown #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 2858a34fd02SLen Brown #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 2868a34fd02SLen Brown 2878a34fd02SLen Brown 288b72e7464SBorislav Petkov #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 289b72e7464SBorislav Petkov #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 290b72e7464SBorislav Petkov #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 291b72e7464SBorislav Petkov 292b72e7464SBorislav Petkov /* Hardware P state interface */ 293b72e7464SBorislav Petkov #define MSR_PPERF 0x0000064e 294b72e7464SBorislav Petkov #define MSR_PERF_LIMIT_REASONS 0x0000064f 295b72e7464SBorislav Petkov #define MSR_PM_ENABLE 0x00000770 296b72e7464SBorislav Petkov #define MSR_HWP_CAPABILITIES 0x00000771 297b72e7464SBorislav Petkov #define MSR_HWP_REQUEST_PKG 0x00000772 298b72e7464SBorislav Petkov #define MSR_HWP_INTERRUPT 0x00000773 299b72e7464SBorislav Petkov #define MSR_HWP_REQUEST 0x00000774 300b72e7464SBorislav Petkov #define MSR_HWP_STATUS 0x00000777 301b72e7464SBorislav Petkov 302b72e7464SBorislav Petkov /* CPUID.6.EAX */ 303b72e7464SBorislav Petkov #define HWP_BASE_BIT (1<<7) 304b72e7464SBorislav Petkov #define HWP_NOTIFICATIONS_BIT (1<<8) 305b72e7464SBorislav Petkov #define HWP_ACTIVITY_WINDOW_BIT (1<<9) 306b72e7464SBorislav Petkov #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 307b72e7464SBorislav Petkov #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 308b72e7464SBorislav Petkov 309b72e7464SBorislav Petkov /* IA32_HWP_CAPABILITIES */ 310670e27d8SLen Brown #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 311670e27d8SLen Brown #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 312670e27d8SLen Brown #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 313670e27d8SLen Brown #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 314b72e7464SBorislav Petkov 315b72e7464SBorislav Petkov /* IA32_HWP_REQUEST */ 316b72e7464SBorislav Petkov #define HWP_MIN_PERF(x) (x & 0xff) 317b72e7464SBorislav Petkov #define HWP_MAX_PERF(x) ((x & 0xff) << 8) 318b72e7464SBorislav Petkov #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 3192fc49cb0SLen Brown #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) 3208d84e906SLen Brown #define HWP_EPP_PERFORMANCE 0x00 3218d84e906SLen Brown #define HWP_EPP_BALANCE_PERFORMANCE 0x80 3228d84e906SLen Brown #define HWP_EPP_BALANCE_POWERSAVE 0xC0 3238d84e906SLen Brown #define HWP_EPP_POWERSAVE 0xFF 3242fc49cb0SLen Brown #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) 3252fc49cb0SLen Brown #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) 326b72e7464SBorislav Petkov 327b72e7464SBorislav Petkov /* IA32_HWP_STATUS */ 328b72e7464SBorislav Petkov #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 329b72e7464SBorislav Petkov #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 330b72e7464SBorislav Petkov 331b72e7464SBorislav Petkov /* IA32_HWP_INTERRUPT */ 332b72e7464SBorislav Petkov #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 333b72e7464SBorislav Petkov #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 334b72e7464SBorislav Petkov 335b72e7464SBorislav Petkov #define MSR_AMD64_MC0_MASK 0xc0010044 336b72e7464SBorislav Petkov 337b72e7464SBorislav Petkov #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 338b72e7464SBorislav Petkov #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 339b72e7464SBorislav Petkov #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 340b72e7464SBorislav Petkov #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 341b72e7464SBorislav Petkov 342b72e7464SBorislav Petkov #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 343b72e7464SBorislav Petkov 344b72e7464SBorislav Petkov /* These are consecutive and not in the normal 4er MCE bank block */ 345b72e7464SBorislav Petkov #define MSR_IA32_MC0_CTL2 0x00000280 346b72e7464SBorislav Petkov #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 347b72e7464SBorislav Petkov 348b72e7464SBorislav Petkov #define MSR_P6_PERFCTR0 0x000000c1 349b72e7464SBorislav Petkov #define MSR_P6_PERFCTR1 0x000000c2 350b72e7464SBorislav Petkov #define MSR_P6_EVNTSEL0 0x00000186 351b72e7464SBorislav Petkov #define MSR_P6_EVNTSEL1 0x00000187 352b72e7464SBorislav Petkov 353b72e7464SBorislav Petkov #define MSR_KNC_PERFCTR0 0x00000020 354b72e7464SBorislav Petkov #define MSR_KNC_PERFCTR1 0x00000021 355b72e7464SBorislav Petkov #define MSR_KNC_EVNTSEL0 0x00000028 356b72e7464SBorislav Petkov #define MSR_KNC_EVNTSEL1 0x00000029 357b72e7464SBorislav Petkov 358b72e7464SBorislav Petkov /* Alternative perfctr range with full access. */ 359b72e7464SBorislav Petkov #define MSR_IA32_PMC0 0x000004c1 360b72e7464SBorislav Petkov 361b72e7464SBorislav Petkov /* AMD64 MSRs. Not complete. See the architecture manual for a more 362b72e7464SBorislav Petkov complete list. */ 363b72e7464SBorislav Petkov 364b72e7464SBorislav Petkov #define MSR_AMD64_PATCH_LEVEL 0x0000008b 365b72e7464SBorislav Petkov #define MSR_AMD64_TSC_RATIO 0xc0000104 366b72e7464SBorislav Petkov #define MSR_AMD64_NB_CFG 0xc001001f 367b72e7464SBorislav Petkov #define MSR_AMD64_PATCH_LOADER 0xc0010020 368b72e7464SBorislav Petkov #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 369b72e7464SBorislav Petkov #define MSR_AMD64_OSVW_STATUS 0xc0010141 370b72e7464SBorislav Petkov #define MSR_AMD64_LS_CFG 0xc0011020 371b72e7464SBorislav Petkov #define MSR_AMD64_DC_CFG 0xc0011022 372b72e7464SBorislav Petkov #define MSR_AMD64_BU_CFG2 0xc001102a 373b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCHCTL 0xc0011030 374b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 375b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 376b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCH_REG_COUNT 3 377b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 378b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPCTL 0xc0011033 379b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPRIP 0xc0011034 380b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA 0xc0011035 381b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA2 0xc0011036 382b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA3 0xc0011037 383b72e7464SBorislav Petkov #define MSR_AMD64_IBSDCLINAD 0xc0011038 384b72e7464SBorislav Petkov #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 385b72e7464SBorislav Petkov #define MSR_AMD64_IBSOP_REG_COUNT 7 386b72e7464SBorislav Petkov #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 387b72e7464SBorislav Petkov #define MSR_AMD64_IBSCTL 0xc001103a 388b72e7464SBorislav Petkov #define MSR_AMD64_IBSBRTARGET 0xc001103b 389b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA4 0xc001103d 390b72e7464SBorislav Petkov #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 3911958b5fcSTom Lendacky #define MSR_AMD64_SEV 0xc0010131 3921958b5fcSTom Lendacky #define MSR_AMD64_SEV_ENABLED_BIT 0 3931958b5fcSTom Lendacky #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) 394b72e7464SBorislav Petkov 39511fb0683STom Lendacky #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f 39611fb0683STom Lendacky 397aaf24884SHuang Rui /* Fam 17h MSRs */ 398aaf24884SHuang Rui #define MSR_F17H_IRPERF 0xc00000e9 399aaf24884SHuang Rui 400b72e7464SBorislav Petkov /* Fam 16h MSRs */ 401b72e7464SBorislav Petkov #define MSR_F16H_L2I_PERF_CTL 0xc0010230 402b72e7464SBorislav Petkov #define MSR_F16H_L2I_PERF_CTR 0xc0010231 403b72e7464SBorislav Petkov #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 404b72e7464SBorislav Petkov #define MSR_F16H_DR2_ADDR_MASK 0xc001101a 405b72e7464SBorislav Petkov #define MSR_F16H_DR3_ADDR_MASK 0xc001101b 406b72e7464SBorislav Petkov #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 407b72e7464SBorislav Petkov 408b72e7464SBorislav Petkov /* Fam 15h MSRs */ 409b72e7464SBorislav Petkov #define MSR_F15H_PERF_CTL 0xc0010200 410e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 411e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 412e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 413e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 414e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 415e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 416e84b7119SJanakarajan Natarajan 417b72e7464SBorislav Petkov #define MSR_F15H_PERF_CTR 0xc0010201 418e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 419e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 420e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 421e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 422e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 423e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 424e84b7119SJanakarajan Natarajan 425b72e7464SBorislav Petkov #define MSR_F15H_NB_PERF_CTL 0xc0010240 426b72e7464SBorislav Petkov #define MSR_F15H_NB_PERF_CTR 0xc0010241 4278a224261SHuang Rui #define MSR_F15H_PTSC 0xc0010280 428ae8b7875SBorislav Petkov #define MSR_F15H_IC_CFG 0xc0011021 429b72e7464SBorislav Petkov 430b72e7464SBorislav Petkov /* Fam 10h MSRs */ 431b72e7464SBorislav Petkov #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 432b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_ENABLE (1<<0) 433b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 434b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 435b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 436b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BASE_SHIFT 20 437b72e7464SBorislav Petkov #define MSR_FAM10H_NODE_ID 0xc001100c 438e4d0e84eSTom Lendacky #define MSR_F10H_DECFG 0xc0011029 439e4d0e84eSTom Lendacky #define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1 4409c6a73c7STom Lendacky #define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT) 441b72e7464SBorislav Petkov 442b72e7464SBorislav Petkov /* K8 MSRs */ 443b72e7464SBorislav Petkov #define MSR_K8_TOP_MEM1 0xc001001a 444b72e7464SBorislav Petkov #define MSR_K8_TOP_MEM2 0xc001001d 445b72e7464SBorislav Petkov #define MSR_K8_SYSCFG 0xc0010010 446872cbefdSTom Lendacky #define MSR_K8_SYSCFG_MEM_ENCRYPT_BIT 23 447872cbefdSTom Lendacky #define MSR_K8_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_K8_SYSCFG_MEM_ENCRYPT_BIT) 448b72e7464SBorislav Petkov #define MSR_K8_INT_PENDING_MSG 0xc0010055 449b72e7464SBorislav Petkov /* C1E active bits in int pending message */ 450b72e7464SBorislav Petkov #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 451b72e7464SBorislav Petkov #define MSR_K8_TSEG_ADDR 0xc0010112 4523afb1121SPaolo Bonzini #define MSR_K8_TSEG_MASK 0xc0010113 453b72e7464SBorislav Petkov #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 454b72e7464SBorislav Petkov #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 455b72e7464SBorislav Petkov #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 456b72e7464SBorislav Petkov 457b72e7464SBorislav Petkov /* K7 MSRs */ 458b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL0 0xc0010000 459b72e7464SBorislav Petkov #define MSR_K7_PERFCTR0 0xc0010004 460b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL1 0xc0010001 461b72e7464SBorislav Petkov #define MSR_K7_PERFCTR1 0xc0010005 462b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL2 0xc0010002 463b72e7464SBorislav Petkov #define MSR_K7_PERFCTR2 0xc0010006 464b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL3 0xc0010003 465b72e7464SBorislav Petkov #define MSR_K7_PERFCTR3 0xc0010007 466b72e7464SBorislav Petkov #define MSR_K7_CLK_CTL 0xc001001b 467b72e7464SBorislav Petkov #define MSR_K7_HWCR 0xc0010015 46818c71ce9STom Lendacky #define MSR_K7_HWCR_SMMLOCK_BIT 0 46918c71ce9STom Lendacky #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) 470b72e7464SBorislav Petkov #define MSR_K7_FID_VID_CTL 0xc0010041 471b72e7464SBorislav Petkov #define MSR_K7_FID_VID_STATUS 0xc0010042 472b72e7464SBorislav Petkov 473b72e7464SBorislav Petkov /* K6 MSRs */ 474b72e7464SBorislav Petkov #define MSR_K6_WHCR 0xc0000082 475b72e7464SBorislav Petkov #define MSR_K6_UWCCR 0xc0000085 476b72e7464SBorislav Petkov #define MSR_K6_EPMR 0xc0000086 477b72e7464SBorislav Petkov #define MSR_K6_PSOR 0xc0000087 478b72e7464SBorislav Petkov #define MSR_K6_PFIR 0xc0000088 479b72e7464SBorislav Petkov 480b72e7464SBorislav Petkov /* Centaur-Hauls/IDT defined MSRs. */ 481b72e7464SBorislav Petkov #define MSR_IDT_FCR1 0x00000107 482b72e7464SBorislav Petkov #define MSR_IDT_FCR2 0x00000108 483b72e7464SBorislav Petkov #define MSR_IDT_FCR3 0x00000109 484b72e7464SBorislav Petkov #define MSR_IDT_FCR4 0x0000010a 485b72e7464SBorislav Petkov 486b72e7464SBorislav Petkov #define MSR_IDT_MCR0 0x00000110 487b72e7464SBorislav Petkov #define MSR_IDT_MCR1 0x00000111 488b72e7464SBorislav Petkov #define MSR_IDT_MCR2 0x00000112 489b72e7464SBorislav Petkov #define MSR_IDT_MCR3 0x00000113 490b72e7464SBorislav Petkov #define MSR_IDT_MCR4 0x00000114 491b72e7464SBorislav Petkov #define MSR_IDT_MCR5 0x00000115 492b72e7464SBorislav Petkov #define MSR_IDT_MCR6 0x00000116 493b72e7464SBorislav Petkov #define MSR_IDT_MCR7 0x00000117 494b72e7464SBorislav Petkov #define MSR_IDT_MCR_CTRL 0x00000120 495b72e7464SBorislav Petkov 496b72e7464SBorislav Petkov /* VIA Cyrix defined MSRs*/ 497b72e7464SBorislav Petkov #define MSR_VIA_FCR 0x00001107 498b72e7464SBorislav Petkov #define MSR_VIA_LONGHAUL 0x0000110a 499b72e7464SBorislav Petkov #define MSR_VIA_RNG 0x0000110b 500b72e7464SBorislav Petkov #define MSR_VIA_BCR2 0x00001147 501b72e7464SBorislav Petkov 502b72e7464SBorislav Petkov /* Transmeta defined MSRs */ 503b72e7464SBorislav Petkov #define MSR_TMTA_LONGRUN_CTRL 0x80868010 504b72e7464SBorislav Petkov #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 505b72e7464SBorislav Petkov #define MSR_TMTA_LRTI_READOUT 0x80868018 506b72e7464SBorislav Petkov #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 507b72e7464SBorislav Petkov 508b72e7464SBorislav Petkov /* Intel defined MSRs. */ 509b72e7464SBorislav Petkov #define MSR_IA32_P5_MC_ADDR 0x00000000 510b72e7464SBorislav Petkov #define MSR_IA32_P5_MC_TYPE 0x00000001 511b72e7464SBorislav Petkov #define MSR_IA32_TSC 0x00000010 512b72e7464SBorislav Petkov #define MSR_IA32_PLATFORM_ID 0x00000017 513b72e7464SBorislav Petkov #define MSR_IA32_EBL_CR_POWERON 0x0000002a 514b72e7464SBorislav Petkov #define MSR_EBC_FREQUENCY_ID 0x0000002c 515b72e7464SBorislav Petkov #define MSR_SMI_COUNT 0x00000034 516b72e7464SBorislav Petkov #define MSR_IA32_FEATURE_CONTROL 0x0000003a 517b72e7464SBorislav Petkov #define MSR_IA32_TSC_ADJUST 0x0000003b 518b72e7464SBorislav Petkov #define MSR_IA32_BNDCFGS 0x00000d90 519b72e7464SBorislav Petkov 5204531662dSJim Mattson #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 5214531662dSJim Mattson 522b72e7464SBorislav Petkov #define MSR_IA32_XSS 0x00000da0 523b72e7464SBorislav Petkov 524b72e7464SBorislav Petkov #define FEATURE_CONTROL_LOCKED (1<<0) 525b72e7464SBorislav Petkov #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 526b72e7464SBorislav Petkov #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 527b72e7464SBorislav Petkov #define FEATURE_CONTROL_LMCE (1<<20) 528b72e7464SBorislav Petkov 529b72e7464SBorislav Petkov #define MSR_IA32_APICBASE 0x0000001b 530b72e7464SBorislav Petkov #define MSR_IA32_APICBASE_BSP (1<<8) 531b72e7464SBorislav Petkov #define MSR_IA32_APICBASE_ENABLE (1<<11) 532b72e7464SBorislav Petkov #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 533b72e7464SBorislav Petkov 534b72e7464SBorislav Petkov #define MSR_IA32_TSCDEADLINE 0x000006e0 535b72e7464SBorislav Petkov 536b72e7464SBorislav Petkov #define MSR_IA32_UCODE_WRITE 0x00000079 537b72e7464SBorislav Petkov #define MSR_IA32_UCODE_REV 0x0000008b 538b72e7464SBorislav Petkov 539b72e7464SBorislav Petkov #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 540b72e7464SBorislav Petkov #define MSR_IA32_SMBASE 0x0000009e 541b72e7464SBorislav Petkov 542b72e7464SBorislav Petkov #define MSR_IA32_PERF_STATUS 0x00000198 543b72e7464SBorislav Petkov #define MSR_IA32_PERF_CTL 0x00000199 544b72e7464SBorislav Petkov #define INTEL_PERF_CTL_MASK 0xffff 545b72e7464SBorislav Petkov #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 546b72e7464SBorislav Petkov #define MSR_AMD_PERF_STATUS 0xc0010063 547b72e7464SBorislav Petkov #define MSR_AMD_PERF_CTL 0xc0010062 548b72e7464SBorislav Petkov 549b72e7464SBorislav Petkov #define MSR_IA32_MPERF 0x000000e7 550b72e7464SBorislav Petkov #define MSR_IA32_APERF 0x000000e8 551b72e7464SBorislav Petkov 552b72e7464SBorislav Petkov #define MSR_IA32_THERM_CONTROL 0x0000019a 553b72e7464SBorislav Petkov #define MSR_IA32_THERM_INTERRUPT 0x0000019b 554b72e7464SBorislav Petkov 555b72e7464SBorislav Petkov #define THERM_INT_HIGH_ENABLE (1 << 0) 556b72e7464SBorislav Petkov #define THERM_INT_LOW_ENABLE (1 << 1) 557b72e7464SBorislav Petkov #define THERM_INT_PLN_ENABLE (1 << 24) 558b72e7464SBorislav Petkov 559b72e7464SBorislav Petkov #define MSR_IA32_THERM_STATUS 0x0000019c 560b72e7464SBorislav Petkov 561b72e7464SBorislav Petkov #define THERM_STATUS_PROCHOT (1 << 0) 562b72e7464SBorislav Petkov #define THERM_STATUS_POWER_LIMIT (1 << 10) 563b72e7464SBorislav Petkov 564b72e7464SBorislav Petkov #define MSR_THERM2_CTL 0x0000019d 565b72e7464SBorislav Petkov 566b72e7464SBorislav Petkov #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 567b72e7464SBorislav Petkov 568b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE 0x000001a0 569b72e7464SBorislav Petkov 570b72e7464SBorislav Petkov #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 571b72e7464SBorislav Petkov 57298af7459SLen Brown #define MSR_MISC_FEATURE_CONTROL 0x000001a4 573b72e7464SBorislav Petkov #define MSR_MISC_PWR_MGMT 0x000001aa 574b72e7464SBorislav Petkov 575b72e7464SBorislav Petkov #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 576b72e7464SBorislav Petkov #define ENERGY_PERF_BIAS_PERFORMANCE 0 577d0117a0eSLen Brown #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 578b72e7464SBorislav Petkov #define ENERGY_PERF_BIAS_NORMAL 6 579d0117a0eSLen Brown #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 580b72e7464SBorislav Petkov #define ENERGY_PERF_BIAS_POWERSAVE 15 581b72e7464SBorislav Petkov 582b72e7464SBorislav Petkov #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 583b72e7464SBorislav Petkov 584b72e7464SBorislav Petkov #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 585b72e7464SBorislav Petkov #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 586b72e7464SBorislav Petkov 587b72e7464SBorislav Petkov #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 588b72e7464SBorislav Petkov 589b72e7464SBorislav Petkov #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 590b72e7464SBorislav Petkov #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 591b72e7464SBorislav Petkov #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 592b72e7464SBorislav Petkov 593b72e7464SBorislav Petkov /* Thermal Thresholds Support */ 594b72e7464SBorislav Petkov #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 595b72e7464SBorislav Petkov #define THERM_SHIFT_THRESHOLD0 8 596b72e7464SBorislav Petkov #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 597b72e7464SBorislav Petkov #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 598b72e7464SBorislav Petkov #define THERM_SHIFT_THRESHOLD1 16 599b72e7464SBorislav Petkov #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 600b72e7464SBorislav Petkov #define THERM_STATUS_THRESHOLD0 (1 << 6) 601b72e7464SBorislav Petkov #define THERM_LOG_THRESHOLD0 (1 << 7) 602b72e7464SBorislav Petkov #define THERM_STATUS_THRESHOLD1 (1 << 8) 603b72e7464SBorislav Petkov #define THERM_LOG_THRESHOLD1 (1 << 9) 604b72e7464SBorislav Petkov 605b72e7464SBorislav Petkov /* MISC_ENABLE bits: architectural */ 606b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 607b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 608b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 609b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 610b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 611b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 612b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 613b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 614b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 615b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 616b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 617b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 618b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 619b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 620b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 621b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 622b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 623b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 624b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 625b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 626b72e7464SBorislav Petkov 627b72e7464SBorislav Petkov /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 628b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 629b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 630b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 631b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 632b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 633b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 634b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 635b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 636b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 637b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 638b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 639b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 640b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 641b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 642b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 643b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 644b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 645b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 646b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 647b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 648b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 649b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 650b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 651b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 652b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 653b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 654b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 655b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 656b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 657b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 658b72e7464SBorislav Petkov 659ab6d9468SKyle Huey /* MISC_FEATURES_ENABLES non-architectural features */ 660ab6d9468SKyle Huey #define MSR_MISC_FEATURES_ENABLES 0x00000140 661ae47eda9SGrzegorz Andrejczuk 662e9ea1e7fSKyle Huey #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 663e9ea1e7fSKyle Huey #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) 664ab6d9468SKyle Huey #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 665ae47eda9SGrzegorz Andrejczuk 666b72e7464SBorislav Petkov #define MSR_IA32_TSC_DEADLINE 0x000006E0 667b72e7464SBorislav Petkov 668b72e7464SBorislav Petkov /* P4/Xeon+ specific */ 669b72e7464SBorislav Petkov #define MSR_IA32_MCG_EAX 0x00000180 670b72e7464SBorislav Petkov #define MSR_IA32_MCG_EBX 0x00000181 671b72e7464SBorislav Petkov #define MSR_IA32_MCG_ECX 0x00000182 672b72e7464SBorislav Petkov #define MSR_IA32_MCG_EDX 0x00000183 673b72e7464SBorislav Petkov #define MSR_IA32_MCG_ESI 0x00000184 674b72e7464SBorislav Petkov #define MSR_IA32_MCG_EDI 0x00000185 675b72e7464SBorislav Petkov #define MSR_IA32_MCG_EBP 0x00000186 676b72e7464SBorislav Petkov #define MSR_IA32_MCG_ESP 0x00000187 677b72e7464SBorislav Petkov #define MSR_IA32_MCG_EFLAGS 0x00000188 678b72e7464SBorislav Petkov #define MSR_IA32_MCG_EIP 0x00000189 679b72e7464SBorislav Petkov #define MSR_IA32_MCG_RESERVED 0x0000018a 680b72e7464SBorislav Petkov 681b72e7464SBorislav Petkov /* Pentium IV performance counter MSRs */ 682b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR0 0x00000300 683b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR1 0x00000301 684b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR2 0x00000302 685b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR3 0x00000303 686b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR0 0x00000304 687b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR1 0x00000305 688b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR2 0x00000306 689b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR3 0x00000307 690b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR0 0x00000308 691b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR1 0x00000309 692b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR2 0x0000030a 693b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR3 0x0000030b 694b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR0 0x0000030c 695b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR1 0x0000030d 696b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR2 0x0000030e 697b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR3 0x0000030f 698b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR4 0x00000310 699b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR5 0x00000311 700b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR0 0x00000360 701b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR1 0x00000361 702b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR2 0x00000362 703b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR3 0x00000363 704b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR0 0x00000364 705b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR1 0x00000365 706b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR2 0x00000366 707b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR3 0x00000367 708b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR0 0x00000368 709b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR1 0x00000369 710b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR2 0x0000036a 711b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR3 0x0000036b 712b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR0 0x0000036c 713b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR1 0x0000036d 714b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR2 0x0000036e 715b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR3 0x0000036f 716b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR4 0x00000370 717b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR5 0x00000371 718b72e7464SBorislav Petkov #define MSR_P4_ALF_ESCR0 0x000003ca 719b72e7464SBorislav Petkov #define MSR_P4_ALF_ESCR1 0x000003cb 720b72e7464SBorislav Petkov #define MSR_P4_BPU_ESCR0 0x000003b2 721b72e7464SBorislav Petkov #define MSR_P4_BPU_ESCR1 0x000003b3 722b72e7464SBorislav Petkov #define MSR_P4_BSU_ESCR0 0x000003a0 723b72e7464SBorislav Petkov #define MSR_P4_BSU_ESCR1 0x000003a1 724b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR0 0x000003b8 725b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR1 0x000003b9 726b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR2 0x000003cc 727b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR3 0x000003cd 728b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR4 0x000003e0 729b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR5 0x000003e1 730b72e7464SBorislav Petkov #define MSR_P4_DAC_ESCR0 0x000003a8 731b72e7464SBorislav Petkov #define MSR_P4_DAC_ESCR1 0x000003a9 732b72e7464SBorislav Petkov #define MSR_P4_FIRM_ESCR0 0x000003a4 733b72e7464SBorislav Petkov #define MSR_P4_FIRM_ESCR1 0x000003a5 734b72e7464SBorislav Petkov #define MSR_P4_FLAME_ESCR0 0x000003a6 735b72e7464SBorislav Petkov #define MSR_P4_FLAME_ESCR1 0x000003a7 736b72e7464SBorislav Petkov #define MSR_P4_FSB_ESCR0 0x000003a2 737b72e7464SBorislav Petkov #define MSR_P4_FSB_ESCR1 0x000003a3 738b72e7464SBorislav Petkov #define MSR_P4_IQ_ESCR0 0x000003ba 739b72e7464SBorislav Petkov #define MSR_P4_IQ_ESCR1 0x000003bb 740b72e7464SBorislav Petkov #define MSR_P4_IS_ESCR0 0x000003b4 741b72e7464SBorislav Petkov #define MSR_P4_IS_ESCR1 0x000003b5 742b72e7464SBorislav Petkov #define MSR_P4_ITLB_ESCR0 0x000003b6 743b72e7464SBorislav Petkov #define MSR_P4_ITLB_ESCR1 0x000003b7 744b72e7464SBorislav Petkov #define MSR_P4_IX_ESCR0 0x000003c8 745b72e7464SBorislav Petkov #define MSR_P4_IX_ESCR1 0x000003c9 746b72e7464SBorislav Petkov #define MSR_P4_MOB_ESCR0 0x000003aa 747b72e7464SBorislav Petkov #define MSR_P4_MOB_ESCR1 0x000003ab 748b72e7464SBorislav Petkov #define MSR_P4_MS_ESCR0 0x000003c0 749b72e7464SBorislav Petkov #define MSR_P4_MS_ESCR1 0x000003c1 750b72e7464SBorislav Petkov #define MSR_P4_PMH_ESCR0 0x000003ac 751b72e7464SBorislav Petkov #define MSR_P4_PMH_ESCR1 0x000003ad 752b72e7464SBorislav Petkov #define MSR_P4_RAT_ESCR0 0x000003bc 753b72e7464SBorislav Petkov #define MSR_P4_RAT_ESCR1 0x000003bd 754b72e7464SBorislav Petkov #define MSR_P4_SAAT_ESCR0 0x000003ae 755b72e7464SBorislav Petkov #define MSR_P4_SAAT_ESCR1 0x000003af 756b72e7464SBorislav Petkov #define MSR_P4_SSU_ESCR0 0x000003be 757b72e7464SBorislav Petkov #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 758b72e7464SBorislav Petkov 759b72e7464SBorislav Petkov #define MSR_P4_TBPU_ESCR0 0x000003c2 760b72e7464SBorislav Petkov #define MSR_P4_TBPU_ESCR1 0x000003c3 761b72e7464SBorislav Petkov #define MSR_P4_TC_ESCR0 0x000003c4 762b72e7464SBorislav Petkov #define MSR_P4_TC_ESCR1 0x000003c5 763b72e7464SBorislav Petkov #define MSR_P4_U2L_ESCR0 0x000003b0 764b72e7464SBorislav Petkov #define MSR_P4_U2L_ESCR1 0x000003b1 765b72e7464SBorislav Petkov 766b72e7464SBorislav Petkov #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 767b72e7464SBorislav Petkov 768b72e7464SBorislav Petkov /* Intel Core-based CPU performance counters */ 769b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 770b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 771b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 772b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 773b72e7464SBorislav Petkov #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 774b72e7464SBorislav Petkov #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 775b72e7464SBorislav Petkov #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 776b72e7464SBorislav Petkov 777b72e7464SBorislav Petkov /* Geode defined MSRs */ 778b72e7464SBorislav Petkov #define MSR_GEODE_BUSCONT_CONF0 0x00001900 779b72e7464SBorislav Petkov 780b72e7464SBorislav Petkov /* Intel VT MSRs */ 781b72e7464SBorislav Petkov #define MSR_IA32_VMX_BASIC 0x00000480 782b72e7464SBorislav Petkov #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 783b72e7464SBorislav Petkov #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 784b72e7464SBorislav Petkov #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 785b72e7464SBorislav Petkov #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 786b72e7464SBorislav Petkov #define MSR_IA32_VMX_MISC 0x00000485 787b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 788b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 789b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 790b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 791b72e7464SBorislav Petkov #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 792b72e7464SBorislav Petkov #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 793b72e7464SBorislav Petkov #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 794b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 795b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 796b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 797b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 798b72e7464SBorislav Petkov #define MSR_IA32_VMX_VMFUNC 0x00000491 799b72e7464SBorislav Petkov 800b72e7464SBorislav Petkov /* VMX_BASIC bits and bitmasks */ 801b72e7464SBorislav Petkov #define VMX_BASIC_VMCS_SIZE_SHIFT 32 802b72e7464SBorislav Petkov #define VMX_BASIC_TRUE_CTLS (1ULL << 55) 803b72e7464SBorislav Petkov #define VMX_BASIC_64 0x0001000000000000LLU 804b72e7464SBorislav Petkov #define VMX_BASIC_MEM_TYPE_SHIFT 50 805b72e7464SBorislav Petkov #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 806b72e7464SBorislav Petkov #define VMX_BASIC_MEM_TYPE_WB 6LLU 807b72e7464SBorislav Petkov #define VMX_BASIC_INOUT 0x0040000000000000LLU 808b72e7464SBorislav Petkov 809b72e7464SBorislav Petkov /* MSR_IA32_VMX_MISC bits */ 810b72e7464SBorislav Petkov #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 811b72e7464SBorislav Petkov #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 812b72e7464SBorislav Petkov /* AMD-V MSRs */ 813b72e7464SBorislav Petkov 814b72e7464SBorislav Petkov #define MSR_VM_CR 0xc0010114 815b72e7464SBorislav Petkov #define MSR_VM_IGNNE 0xc0010115 816b72e7464SBorislav Petkov #define MSR_VM_HSAVE_PA 0xc0010117 817b72e7464SBorislav Petkov 818b72e7464SBorislav Petkov #endif /* _ASM_X86_MSR_INDEX_H */ 819