xref: /openbmc/linux/arch/x86/include/asm/msr-index.h (revision 4e3f77d8)
1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
2b72e7464SBorislav Petkov #ifndef _ASM_X86_MSR_INDEX_H
3b72e7464SBorislav Petkov #define _ASM_X86_MSR_INDEX_H
4b72e7464SBorislav Petkov 
5d8eabc37SThomas Gleixner #include <linux/bits.h>
6d8eabc37SThomas Gleixner 
7053080a9SBorislav Petkov /*
8053080a9SBorislav Petkov  * CPU model specific register (MSR) numbers.
9053080a9SBorislav Petkov  *
10053080a9SBorislav Petkov  * Do not add new entries to this file unless the definitions are shared
11053080a9SBorislav Petkov  * between multiple compilation units.
12053080a9SBorislav Petkov  */
13b72e7464SBorislav Petkov 
14b72e7464SBorislav Petkov /* x86-64 specific MSRs */
15b72e7464SBorislav Petkov #define MSR_EFER		0xc0000080 /* extended feature register */
16b72e7464SBorislav Petkov #define MSR_STAR		0xc0000081 /* legacy mode SYSCALL target */
17b72e7464SBorislav Petkov #define MSR_LSTAR		0xc0000082 /* long mode SYSCALL target */
18b72e7464SBorislav Petkov #define MSR_CSTAR		0xc0000083 /* compat mode SYSCALL target */
19b72e7464SBorislav Petkov #define MSR_SYSCALL_MASK	0xc0000084 /* EFLAGS mask for syscall */
20b72e7464SBorislav Petkov #define MSR_FS_BASE		0xc0000100 /* 64bit FS base */
21b72e7464SBorislav Petkov #define MSR_GS_BASE		0xc0000101 /* 64bit GS base */
22b72e7464SBorislav Petkov #define MSR_KERNEL_GS_BASE	0xc0000102 /* SwapGS GS shadow */
23b72e7464SBorislav Petkov #define MSR_TSC_AUX		0xc0000103 /* Auxiliary TSC */
24b72e7464SBorislav Petkov 
25b72e7464SBorislav Petkov /* EFER bits: */
26b72e7464SBorislav Petkov #define _EFER_SCE		0  /* SYSCALL/SYSRET */
27b72e7464SBorislav Petkov #define _EFER_LME		8  /* Long mode enable */
28b72e7464SBorislav Petkov #define _EFER_LMA		10 /* Long mode active (read-only) */
29b72e7464SBorislav Petkov #define _EFER_NX		11 /* No execute enable */
30b72e7464SBorislav Petkov #define _EFER_SVME		12 /* Enable virtualization */
31b72e7464SBorislav Petkov #define _EFER_LMSLE		13 /* Long Mode Segment Limit Enable */
32b72e7464SBorislav Petkov #define _EFER_FFXSR		14 /* Enable Fast FXSAVE/FXRSTOR */
33b72e7464SBorislav Petkov 
34b72e7464SBorislav Petkov #define EFER_SCE		(1<<_EFER_SCE)
35b72e7464SBorislav Petkov #define EFER_LME		(1<<_EFER_LME)
36b72e7464SBorislav Petkov #define EFER_LMA		(1<<_EFER_LMA)
37b72e7464SBorislav Petkov #define EFER_NX			(1<<_EFER_NX)
38b72e7464SBorislav Petkov #define EFER_SVME		(1<<_EFER_SVME)
39b72e7464SBorislav Petkov #define EFER_LMSLE		(1<<_EFER_LMSLE)
40b72e7464SBorislav Petkov #define EFER_FFXSR		(1<<_EFER_FFXSR)
41b72e7464SBorislav Petkov 
42b72e7464SBorislav Petkov /* Intel MSRs. Some also available on other CPUs */
433f5a7896STony Luck 
441e340c60SDavid Woodhouse #define MSR_IA32_SPEC_CTRL		0x00000048 /* Speculation Control */
45d8eabc37SThomas Gleixner #define SPEC_CTRL_IBRS			BIT(0)	   /* Indirect Branch Restricted Speculation */
465bfbe3adSTim Chen #define SPEC_CTRL_STIBP_SHIFT		1	   /* Single Thread Indirect Branch Predictor (STIBP) bit */
47d8eabc37SThomas Gleixner #define SPEC_CTRL_STIBP			BIT(SPEC_CTRL_STIBP_SHIFT)	/* STIBP mask */
489f65fb29SKonrad Rzeszutek Wilk #define SPEC_CTRL_SSBD_SHIFT		2	   /* Speculative Store Bypass Disable bit */
49d8eabc37SThomas Gleixner #define SPEC_CTRL_SSBD			BIT(SPEC_CTRL_SSBD_SHIFT)	/* Speculative Store Bypass Disable */
501e340c60SDavid Woodhouse 
511e340c60SDavid Woodhouse #define MSR_IA32_PRED_CMD		0x00000049 /* Prediction Command */
52d8eabc37SThomas Gleixner #define PRED_CMD_IBPB			BIT(0)	   /* Indirect Branch Prediction Barrier */
531e340c60SDavid Woodhouse 
543f5a7896STony Luck #define MSR_PPIN_CTL			0x0000004e
553f5a7896STony Luck #define MSR_PPIN			0x0000004f
563f5a7896STony Luck 
57b72e7464SBorislav Petkov #define MSR_IA32_PERFCTR0		0x000000c1
58b72e7464SBorislav Petkov #define MSR_IA32_PERFCTR1		0x000000c2
59b72e7464SBorislav Petkov #define MSR_FSB_FREQ			0x000000cd
605369a21eSLen Brown #define MSR_PLATFORM_INFO		0x000000ce
6190218ac7SKyle Huey #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT	31
6290218ac7SKyle Huey #define MSR_PLATFORM_INFO_CPUID_FAULT		BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
63b72e7464SBorislav Petkov 
64bd688c69SFenghua Yu #define MSR_IA32_UMWAIT_CONTROL			0xe1
65bd688c69SFenghua Yu #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE	BIT(0)
66bd688c69SFenghua Yu #define MSR_IA32_UMWAIT_CONTROL_RESERVED	BIT(1)
67bd688c69SFenghua Yu /*
68bd688c69SFenghua Yu  * The time field is bit[31:2], but representing a 32bit value with
69bd688c69SFenghua Yu  * bit[1:0] zero.
70bd688c69SFenghua Yu  */
71bd688c69SFenghua Yu #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK	(~0x03U)
72bd688c69SFenghua Yu 
7340496c8eSLen Brown #define MSR_PKG_CST_CONFIG_CONTROL	0x000000e2
74b72e7464SBorislav Petkov #define NHM_C3_AUTO_DEMOTE		(1UL << 25)
75b72e7464SBorislav Petkov #define NHM_C1_AUTO_DEMOTE		(1UL << 26)
76b72e7464SBorislav Petkov #define ATM_LNC_C6_AUTO_DEMOTE		(1UL << 25)
77a00072a2SMatt Turner #define SNB_C3_AUTO_UNDEMOTE		(1UL << 27)
78a00072a2SMatt Turner #define SNB_C1_AUTO_UNDEMOTE		(1UL << 28)
79b72e7464SBorislav Petkov 
80b72e7464SBorislav Petkov #define MSR_MTRRcap			0x000000fe
811e340c60SDavid Woodhouse 
821e340c60SDavid Woodhouse #define MSR_IA32_ARCH_CAPABILITIES	0x0000010a
83d8eabc37SThomas Gleixner #define ARCH_CAP_RDCL_NO		BIT(0)	/* Not susceptible to Meltdown */
84d8eabc37SThomas Gleixner #define ARCH_CAP_IBRS_ALL		BIT(1)	/* Enhanced IBRS support */
85d8eabc37SThomas Gleixner #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH	BIT(3)	/* Skip L1D flush on vmentry */
86d8eabc37SThomas Gleixner #define ARCH_CAP_SSB_NO			BIT(4)	/*
8777243971SKonrad Rzeszutek Wilk 						 * Not susceptible to Speculative Store Bypass
889f65fb29SKonrad Rzeszutek Wilk 						 * attack, so no Speculative Store Bypass
899f65fb29SKonrad Rzeszutek Wilk 						 * control required.
9077243971SKonrad Rzeszutek Wilk 						 */
91ed5194c2SAndi Kleen #define ARCH_CAP_MDS_NO			BIT(5)   /*
92ed5194c2SAndi Kleen 						  * Not susceptible to
93ed5194c2SAndi Kleen 						  * Microarchitectural Data
94ed5194c2SAndi Kleen 						  * Sampling (MDS) vulnerabilities.
95ed5194c2SAndi Kleen 						  */
961e340c60SDavid Woodhouse 
973fa045beSPaolo Bonzini #define MSR_IA32_FLUSH_CMD		0x0000010b
98d8eabc37SThomas Gleixner #define L1D_FLUSH			BIT(0)	/*
993fa045beSPaolo Bonzini 						 * Writeback and invalidate the
1003fa045beSPaolo Bonzini 						 * L1 data cache.
1013fa045beSPaolo Bonzini 						 */
1023fa045beSPaolo Bonzini 
103b72e7464SBorislav Petkov #define MSR_IA32_BBL_CR_CTL		0x00000119
104b72e7464SBorislav Petkov #define MSR_IA32_BBL_CR_CTL3		0x0000011e
105b72e7464SBorislav Petkov 
106b72e7464SBorislav Petkov #define MSR_IA32_SYSENTER_CS		0x00000174
107b72e7464SBorislav Petkov #define MSR_IA32_SYSENTER_ESP		0x00000175
108b72e7464SBorislav Petkov #define MSR_IA32_SYSENTER_EIP		0x00000176
109b72e7464SBorislav Petkov 
110b72e7464SBorislav Petkov #define MSR_IA32_MCG_CAP		0x00000179
111b72e7464SBorislav Petkov #define MSR_IA32_MCG_STATUS		0x0000017a
112b72e7464SBorislav Petkov #define MSR_IA32_MCG_CTL		0x0000017b
113b72e7464SBorislav Petkov #define MSR_IA32_MCG_EXT_CTL		0x000004d0
114b72e7464SBorislav Petkov 
115b72e7464SBorislav Petkov #define MSR_OFFCORE_RSP_0		0x000001a6
116b72e7464SBorislav Petkov #define MSR_OFFCORE_RSP_1		0x000001a7
117b72e7464SBorislav Petkov #define MSR_TURBO_RATIO_LIMIT		0x000001ad
118b72e7464SBorislav Petkov #define MSR_TURBO_RATIO_LIMIT1		0x000001ae
119b72e7464SBorislav Petkov #define MSR_TURBO_RATIO_LIMIT2		0x000001af
120b72e7464SBorislav Petkov 
121b72e7464SBorislav Petkov #define MSR_LBR_SELECT			0x000001c8
122b72e7464SBorislav Petkov #define MSR_LBR_TOS			0x000001c9
123b72e7464SBorislav Petkov #define MSR_LBR_NHM_FROM		0x00000680
124b72e7464SBorislav Petkov #define MSR_LBR_NHM_TO			0x000006c0
125b72e7464SBorislav Petkov #define MSR_LBR_CORE_FROM		0x00000040
126b72e7464SBorislav Petkov #define MSR_LBR_CORE_TO			0x00000060
127b72e7464SBorislav Petkov 
128b83ff1c8SAndi Kleen #define MSR_LBR_INFO_0			0x00000dc0 /* ... 0xddf for _31 */
129b83ff1c8SAndi Kleen #define LBR_INFO_MISPRED		BIT_ULL(63)
130b83ff1c8SAndi Kleen #define LBR_INFO_IN_TX			BIT_ULL(62)
131b83ff1c8SAndi Kleen #define LBR_INFO_ABORT			BIT_ULL(61)
132b83ff1c8SAndi Kleen #define LBR_INFO_CYCLES			0xffff
133b83ff1c8SAndi Kleen 
134b72e7464SBorislav Petkov #define MSR_IA32_PEBS_ENABLE		0x000003f1
135c22497f5SKan Liang #define MSR_PEBS_DATA_CFG		0x000003f2
136b72e7464SBorislav Petkov #define MSR_IA32_DS_AREA		0x00000600
137b72e7464SBorislav Petkov #define MSR_IA32_PERF_CAPABILITIES	0x00000345
138b72e7464SBorislav Petkov #define MSR_PEBS_LD_LAT_THRESHOLD	0x000003f6
139b72e7464SBorislav Petkov 
140b72e7464SBorislav Petkov #define MSR_IA32_RTIT_CTL		0x00000570
141887eda13SChao Peng #define RTIT_CTL_TRACEEN		BIT(0)
142887eda13SChao Peng #define RTIT_CTL_CYCLEACC		BIT(1)
143887eda13SChao Peng #define RTIT_CTL_OS			BIT(2)
144887eda13SChao Peng #define RTIT_CTL_USR			BIT(3)
145887eda13SChao Peng #define RTIT_CTL_PWR_EVT_EN		BIT(4)
146887eda13SChao Peng #define RTIT_CTL_FUP_ON_PTW		BIT(5)
14769843a91SLuwei Kang #define RTIT_CTL_FABRIC_EN		BIT(6)
148887eda13SChao Peng #define RTIT_CTL_CR3EN			BIT(7)
149887eda13SChao Peng #define RTIT_CTL_TOPA			BIT(8)
150887eda13SChao Peng #define RTIT_CTL_MTC_EN			BIT(9)
151887eda13SChao Peng #define RTIT_CTL_TSC_EN			BIT(10)
152887eda13SChao Peng #define RTIT_CTL_DISRETC		BIT(11)
153887eda13SChao Peng #define RTIT_CTL_PTW_EN			BIT(12)
154887eda13SChao Peng #define RTIT_CTL_BRANCH_EN		BIT(13)
155887eda13SChao Peng #define RTIT_CTL_MTC_RANGE_OFFSET	14
156887eda13SChao Peng #define RTIT_CTL_MTC_RANGE		(0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
157887eda13SChao Peng #define RTIT_CTL_CYC_THRESH_OFFSET	19
158887eda13SChao Peng #define RTIT_CTL_CYC_THRESH		(0x0full << RTIT_CTL_CYC_THRESH_OFFSET)
159887eda13SChao Peng #define RTIT_CTL_PSB_FREQ_OFFSET	24
160887eda13SChao Peng #define RTIT_CTL_PSB_FREQ		(0x0full << RTIT_CTL_PSB_FREQ_OFFSET)
161887eda13SChao Peng #define RTIT_CTL_ADDR0_OFFSET		32
162887eda13SChao Peng #define RTIT_CTL_ADDR0			(0x0full << RTIT_CTL_ADDR0_OFFSET)
163887eda13SChao Peng #define RTIT_CTL_ADDR1_OFFSET		36
164887eda13SChao Peng #define RTIT_CTL_ADDR1			(0x0full << RTIT_CTL_ADDR1_OFFSET)
165887eda13SChao Peng #define RTIT_CTL_ADDR2_OFFSET		40
166887eda13SChao Peng #define RTIT_CTL_ADDR2			(0x0full << RTIT_CTL_ADDR2_OFFSET)
167887eda13SChao Peng #define RTIT_CTL_ADDR3_OFFSET		44
168887eda13SChao Peng #define RTIT_CTL_ADDR3			(0x0full << RTIT_CTL_ADDR3_OFFSET)
169b72e7464SBorislav Petkov #define MSR_IA32_RTIT_STATUS		0x00000571
170887eda13SChao Peng #define RTIT_STATUS_FILTEREN		BIT(0)
171887eda13SChao Peng #define RTIT_STATUS_CONTEXTEN		BIT(1)
172887eda13SChao Peng #define RTIT_STATUS_TRIGGEREN		BIT(2)
173887eda13SChao Peng #define RTIT_STATUS_BUFFOVF		BIT(3)
174887eda13SChao Peng #define RTIT_STATUS_ERROR		BIT(4)
175887eda13SChao Peng #define RTIT_STATUS_STOPPED		BIT(5)
17669843a91SLuwei Kang #define RTIT_STATUS_BYTECNT_OFFSET	32
17769843a91SLuwei Kang #define RTIT_STATUS_BYTECNT		(0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET)
178f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR0_A		0x00000580
179f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR0_B		0x00000581
180f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR1_A		0x00000582
181f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR1_B		0x00000583
182f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR2_A		0x00000584
183f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR2_B		0x00000585
184f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR3_A		0x00000586
185f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR3_B		0x00000587
186b72e7464SBorislav Petkov #define MSR_IA32_RTIT_CR3_MATCH		0x00000572
187b72e7464SBorislav Petkov #define MSR_IA32_RTIT_OUTPUT_BASE	0x00000560
188b72e7464SBorislav Petkov #define MSR_IA32_RTIT_OUTPUT_MASK	0x00000561
189b72e7464SBorislav Petkov 
190b72e7464SBorislav Petkov #define MSR_MTRRfix64K_00000		0x00000250
191b72e7464SBorislav Petkov #define MSR_MTRRfix16K_80000		0x00000258
192b72e7464SBorislav Petkov #define MSR_MTRRfix16K_A0000		0x00000259
193b72e7464SBorislav Petkov #define MSR_MTRRfix4K_C0000		0x00000268
194b72e7464SBorislav Petkov #define MSR_MTRRfix4K_C8000		0x00000269
195b72e7464SBorislav Petkov #define MSR_MTRRfix4K_D0000		0x0000026a
196b72e7464SBorislav Petkov #define MSR_MTRRfix4K_D8000		0x0000026b
197b72e7464SBorislav Petkov #define MSR_MTRRfix4K_E0000		0x0000026c
198b72e7464SBorislav Petkov #define MSR_MTRRfix4K_E8000		0x0000026d
199b72e7464SBorislav Petkov #define MSR_MTRRfix4K_F0000		0x0000026e
200b72e7464SBorislav Petkov #define MSR_MTRRfix4K_F8000		0x0000026f
201b72e7464SBorislav Petkov #define MSR_MTRRdefType			0x000002ff
202b72e7464SBorislav Petkov 
203b72e7464SBorislav Petkov #define MSR_IA32_CR_PAT			0x00000277
204b72e7464SBorislav Petkov 
205b72e7464SBorislav Petkov #define MSR_IA32_DEBUGCTLMSR		0x000001d9
206b72e7464SBorislav Petkov #define MSR_IA32_LASTBRANCHFROMIP	0x000001db
207b72e7464SBorislav Petkov #define MSR_IA32_LASTBRANCHTOIP		0x000001dc
208b72e7464SBorislav Petkov #define MSR_IA32_LASTINTFROMIP		0x000001dd
209b72e7464SBorislav Petkov #define MSR_IA32_LASTINTTOIP		0x000001de
210b72e7464SBorislav Petkov 
211b72e7464SBorislav Petkov /* DEBUGCTLMSR bits (others vary by model): */
212b72e7464SBorislav Petkov #define DEBUGCTLMSR_LBR			(1UL <<  0) /* last branch recording */
213b9894a2fSKyle Huey #define DEBUGCTLMSR_BTF_SHIFT		1
214b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTF			(1UL <<  1) /* single-step on branches */
215b72e7464SBorislav Petkov #define DEBUGCTLMSR_TR			(1UL <<  6)
216b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTS			(1UL <<  7)
217b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTINT		(1UL <<  8)
218b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTS_OFF_OS		(1UL <<  9)
219b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTS_OFF_USR		(1UL << 10)
220b72e7464SBorislav Petkov #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI	(1UL << 11)
221af3bdb99SAndi Kleen #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI	(1UL << 12)
2226089327fSKan Liang #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT	14
2236089327fSKan Liang #define DEBUGCTLMSR_FREEZE_IN_SMM	(1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT)
224b72e7464SBorislav Petkov 
225d0dc8494SAndi Kleen #define MSR_PEBS_FRONTEND		0x000003f7
226d0dc8494SAndi Kleen 
227b72e7464SBorislav Petkov #define MSR_IA32_POWER_CTL		0x000001fc
228b72e7464SBorislav Petkov 
229b72e7464SBorislav Petkov #define MSR_IA32_MC0_CTL		0x00000400
230b72e7464SBorislav Petkov #define MSR_IA32_MC0_STATUS		0x00000401
231b72e7464SBorislav Petkov #define MSR_IA32_MC0_ADDR		0x00000402
232b72e7464SBorislav Petkov #define MSR_IA32_MC0_MISC		0x00000403
233b72e7464SBorislav Petkov 
234b72e7464SBorislav Petkov /* C-state Residency Counters */
235b72e7464SBorislav Petkov #define MSR_PKG_C3_RESIDENCY		0x000003f8
236b72e7464SBorislav Petkov #define MSR_PKG_C6_RESIDENCY		0x000003f9
2370539ba11SLen Brown #define MSR_ATOM_PKG_C6_RESIDENCY	0x000003fa
238b72e7464SBorislav Petkov #define MSR_PKG_C7_RESIDENCY		0x000003fa
239b72e7464SBorislav Petkov #define MSR_CORE_C3_RESIDENCY		0x000003fc
240b72e7464SBorislav Petkov #define MSR_CORE_C6_RESIDENCY		0x000003fd
241b72e7464SBorislav Petkov #define MSR_CORE_C7_RESIDENCY		0x000003fe
242b72e7464SBorislav Petkov #define MSR_KNL_CORE_C6_RESIDENCY	0x000003ff
243b72e7464SBorislav Petkov #define MSR_PKG_C2_RESIDENCY		0x0000060d
244b72e7464SBorislav Petkov #define MSR_PKG_C8_RESIDENCY		0x00000630
245b72e7464SBorislav Petkov #define MSR_PKG_C9_RESIDENCY		0x00000631
246b72e7464SBorislav Petkov #define MSR_PKG_C10_RESIDENCY		0x00000632
247b72e7464SBorislav Petkov 
2485a63426eSLen Brown /* Interrupt Response Limit */
2495a63426eSLen Brown #define MSR_PKGC3_IRTL			0x0000060a
2505a63426eSLen Brown #define MSR_PKGC6_IRTL			0x0000060b
2515a63426eSLen Brown #define MSR_PKGC7_IRTL			0x0000060c
2525a63426eSLen Brown #define MSR_PKGC8_IRTL			0x00000633
2535a63426eSLen Brown #define MSR_PKGC9_IRTL			0x00000634
2545a63426eSLen Brown #define MSR_PKGC10_IRTL			0x00000635
2555a63426eSLen Brown 
256b72e7464SBorislav Petkov /* Run Time Average Power Limiting (RAPL) Interface */
257b72e7464SBorislav Petkov 
258b72e7464SBorislav Petkov #define MSR_RAPL_POWER_UNIT		0x00000606
259b72e7464SBorislav Petkov 
260b72e7464SBorislav Petkov #define MSR_PKG_POWER_LIMIT		0x00000610
261b72e7464SBorislav Petkov #define MSR_PKG_ENERGY_STATUS		0x00000611
262b72e7464SBorislav Petkov #define MSR_PKG_PERF_STATUS		0x00000613
263b72e7464SBorislav Petkov #define MSR_PKG_POWER_INFO		0x00000614
264b72e7464SBorislav Petkov 
265b72e7464SBorislav Petkov #define MSR_DRAM_POWER_LIMIT		0x00000618
266b72e7464SBorislav Petkov #define MSR_DRAM_ENERGY_STATUS		0x00000619
267b72e7464SBorislav Petkov #define MSR_DRAM_PERF_STATUS		0x0000061b
268b72e7464SBorislav Petkov #define MSR_DRAM_POWER_INFO		0x0000061c
269b72e7464SBorislav Petkov 
270b72e7464SBorislav Petkov #define MSR_PP0_POWER_LIMIT		0x00000638
271b72e7464SBorislav Petkov #define MSR_PP0_ENERGY_STATUS		0x00000639
272b72e7464SBorislav Petkov #define MSR_PP0_POLICY			0x0000063a
273b72e7464SBorislav Petkov #define MSR_PP0_PERF_STATUS		0x0000063b
274b72e7464SBorislav Petkov 
275b72e7464SBorislav Petkov #define MSR_PP1_POWER_LIMIT		0x00000640
276b72e7464SBorislav Petkov #define MSR_PP1_ENERGY_STATUS		0x00000641
277b72e7464SBorislav Petkov #define MSR_PP1_POLICY			0x00000642
278b72e7464SBorislav Petkov 
2794a6772f5SVladimir Zapolskiy /* Config TDP MSRs */
28082bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_NOMINAL		0x00000648
28182bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_LEVEL_1		0x00000649
28282bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_LEVEL_2		0x0000064A
28382bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_CONTROL		0x0000064B
28482bb70c5SRafael J. Wysocki #define MSR_TURBO_ACTIVATION_RATIO	0x0000064C
28582bb70c5SRafael J. Wysocki 
286dcee75b3SSrinivas Pandruvada #define MSR_PLATFORM_ENERGY_STATUS	0x0000064D
287dcee75b3SSrinivas Pandruvada 
288b72e7464SBorislav Petkov #define MSR_PKG_WEIGHTED_CORE_C0_RES	0x00000658
289b72e7464SBorislav Petkov #define MSR_PKG_ANY_CORE_C0_RES		0x00000659
290b72e7464SBorislav Petkov #define MSR_PKG_ANY_GFXE_C0_RES		0x0000065A
291b72e7464SBorislav Petkov #define MSR_PKG_BOTH_CORE_GFXE_C0_RES	0x0000065B
292b72e7464SBorislav Petkov 
293b72e7464SBorislav Petkov #define MSR_CORE_C1_RES			0x00000660
2940539ba11SLen Brown #define MSR_MODULE_C6_RES_MS		0x00000664
295b72e7464SBorislav Petkov 
296b72e7464SBorislav Petkov #define MSR_CC6_DEMOTION_POLICY_CONFIG	0x00000668
297b72e7464SBorislav Petkov #define MSR_MC6_DEMOTION_POLICY_CONFIG	0x00000669
298b72e7464SBorislav Petkov 
2998a34fd02SLen Brown #define MSR_ATOM_CORE_RATIOS		0x0000066a
3008a34fd02SLen Brown #define MSR_ATOM_CORE_VIDS		0x0000066b
3018a34fd02SLen Brown #define MSR_ATOM_CORE_TURBO_RATIOS	0x0000066c
3028a34fd02SLen Brown #define MSR_ATOM_CORE_TURBO_VIDS	0x0000066d
3038a34fd02SLen Brown 
3048a34fd02SLen Brown 
305b72e7464SBorislav Petkov #define MSR_CORE_PERF_LIMIT_REASONS	0x00000690
306b72e7464SBorislav Petkov #define MSR_GFX_PERF_LIMIT_REASONS	0x000006B0
307b72e7464SBorislav Petkov #define MSR_RING_PERF_LIMIT_REASONS	0x000006B1
308b72e7464SBorislav Petkov 
309b72e7464SBorislav Petkov /* Hardware P state interface */
310b72e7464SBorislav Petkov #define MSR_PPERF			0x0000064e
311b72e7464SBorislav Petkov #define MSR_PERF_LIMIT_REASONS		0x0000064f
312b72e7464SBorislav Petkov #define MSR_PM_ENABLE			0x00000770
313b72e7464SBorislav Petkov #define MSR_HWP_CAPABILITIES		0x00000771
314b72e7464SBorislav Petkov #define MSR_HWP_REQUEST_PKG		0x00000772
315b72e7464SBorislav Petkov #define MSR_HWP_INTERRUPT		0x00000773
316b72e7464SBorislav Petkov #define MSR_HWP_REQUEST 		0x00000774
317b72e7464SBorislav Petkov #define MSR_HWP_STATUS			0x00000777
318b72e7464SBorislav Petkov 
319b72e7464SBorislav Petkov /* CPUID.6.EAX */
320b72e7464SBorislav Petkov #define HWP_BASE_BIT			(1<<7)
321b72e7464SBorislav Petkov #define HWP_NOTIFICATIONS_BIT		(1<<8)
322b72e7464SBorislav Petkov #define HWP_ACTIVITY_WINDOW_BIT		(1<<9)
323b72e7464SBorislav Petkov #define HWP_ENERGY_PERF_PREFERENCE_BIT	(1<<10)
324b72e7464SBorislav Petkov #define HWP_PACKAGE_LEVEL_REQUEST_BIT	(1<<11)
325b72e7464SBorislav Petkov 
326b72e7464SBorislav Petkov /* IA32_HWP_CAPABILITIES */
327670e27d8SLen Brown #define HWP_HIGHEST_PERF(x)		(((x) >> 0) & 0xff)
328670e27d8SLen Brown #define HWP_GUARANTEED_PERF(x)		(((x) >> 8) & 0xff)
329670e27d8SLen Brown #define HWP_MOSTEFFICIENT_PERF(x)	(((x) >> 16) & 0xff)
330670e27d8SLen Brown #define HWP_LOWEST_PERF(x)		(((x) >> 24) & 0xff)
331b72e7464SBorislav Petkov 
332b72e7464SBorislav Petkov /* IA32_HWP_REQUEST */
333b72e7464SBorislav Petkov #define HWP_MIN_PERF(x) 		(x & 0xff)
334b72e7464SBorislav Petkov #define HWP_MAX_PERF(x) 		((x & 0xff) << 8)
335b72e7464SBorislav Petkov #define HWP_DESIRED_PERF(x)		((x & 0xff) << 16)
3362fc49cb0SLen Brown #define HWP_ENERGY_PERF_PREFERENCE(x)	(((unsigned long long) x & 0xff) << 24)
3378d84e906SLen Brown #define HWP_EPP_PERFORMANCE		0x00
3388d84e906SLen Brown #define HWP_EPP_BALANCE_PERFORMANCE	0x80
3398d84e906SLen Brown #define HWP_EPP_BALANCE_POWERSAVE	0xC0
3408d84e906SLen Brown #define HWP_EPP_POWERSAVE		0xFF
3412fc49cb0SLen Brown #define HWP_ACTIVITY_WINDOW(x)		((unsigned long long)(x & 0xff3) << 32)
3422fc49cb0SLen Brown #define HWP_PACKAGE_CONTROL(x)		((unsigned long long)(x & 0x1) << 42)
343b72e7464SBorislav Petkov 
344b72e7464SBorislav Petkov /* IA32_HWP_STATUS */
345b72e7464SBorislav Petkov #define HWP_GUARANTEED_CHANGE(x)	(x & 0x1)
346b72e7464SBorislav Petkov #define HWP_EXCURSION_TO_MINIMUM(x)	(x & 0x4)
347b72e7464SBorislav Petkov 
348b72e7464SBorislav Petkov /* IA32_HWP_INTERRUPT */
349b72e7464SBorislav Petkov #define HWP_CHANGE_TO_GUARANTEED_INT(x)	(x & 0x1)
350b72e7464SBorislav Petkov #define HWP_EXCURSION_TO_MINIMUM_INT(x)	(x & 0x2)
351b72e7464SBorislav Petkov 
352b72e7464SBorislav Petkov #define MSR_AMD64_MC0_MASK		0xc0010044
353b72e7464SBorislav Petkov 
354b72e7464SBorislav Petkov #define MSR_IA32_MCx_CTL(x)		(MSR_IA32_MC0_CTL + 4*(x))
355b72e7464SBorislav Petkov #define MSR_IA32_MCx_STATUS(x)		(MSR_IA32_MC0_STATUS + 4*(x))
356b72e7464SBorislav Petkov #define MSR_IA32_MCx_ADDR(x)		(MSR_IA32_MC0_ADDR + 4*(x))
357b72e7464SBorislav Petkov #define MSR_IA32_MCx_MISC(x)		(MSR_IA32_MC0_MISC + 4*(x))
358b72e7464SBorislav Petkov 
359b72e7464SBorislav Petkov #define MSR_AMD64_MCx_MASK(x)		(MSR_AMD64_MC0_MASK + (x))
360b72e7464SBorislav Petkov 
361b72e7464SBorislav Petkov /* These are consecutive and not in the normal 4er MCE bank block */
362b72e7464SBorislav Petkov #define MSR_IA32_MC0_CTL2		0x00000280
363b72e7464SBorislav Petkov #define MSR_IA32_MCx_CTL2(x)		(MSR_IA32_MC0_CTL2 + (x))
364b72e7464SBorislav Petkov 
365b72e7464SBorislav Petkov #define MSR_P6_PERFCTR0			0x000000c1
366b72e7464SBorislav Petkov #define MSR_P6_PERFCTR1			0x000000c2
367b72e7464SBorislav Petkov #define MSR_P6_EVNTSEL0			0x00000186
368b72e7464SBorislav Petkov #define MSR_P6_EVNTSEL1			0x00000187
369b72e7464SBorislav Petkov 
370b72e7464SBorislav Petkov #define MSR_KNC_PERFCTR0               0x00000020
371b72e7464SBorislav Petkov #define MSR_KNC_PERFCTR1               0x00000021
372b72e7464SBorislav Petkov #define MSR_KNC_EVNTSEL0               0x00000028
373b72e7464SBorislav Petkov #define MSR_KNC_EVNTSEL1               0x00000029
374b72e7464SBorislav Petkov 
375b72e7464SBorislav Petkov /* Alternative perfctr range with full access. */
376b72e7464SBorislav Petkov #define MSR_IA32_PMC0			0x000004c1
377b72e7464SBorislav Petkov 
37842880f72SAlexander Shishkin /* Auto-reload via MSR instead of DS area */
37942880f72SAlexander Shishkin #define MSR_RELOAD_PMC0			0x000014c1
38042880f72SAlexander Shishkin #define MSR_RELOAD_FIXED_CTR0		0x00001309
38142880f72SAlexander Shishkin 
382342061c5SBorislav Petkov /*
383342061c5SBorislav Petkov  * AMD64 MSRs. Not complete. See the architecture manual for a more
384342061c5SBorislav Petkov  * complete list.
385342061c5SBorislav Petkov  */
386b72e7464SBorislav Petkov #define MSR_AMD64_PATCH_LEVEL		0x0000008b
387b72e7464SBorislav Petkov #define MSR_AMD64_TSC_RATIO		0xc0000104
388b72e7464SBorislav Petkov #define MSR_AMD64_NB_CFG		0xc001001f
389c49a0a80STom Lendacky #define MSR_AMD64_CPUID_FN_1		0xc0011004
390b72e7464SBorislav Petkov #define MSR_AMD64_PATCH_LOADER		0xc0010020
391342061c5SBorislav Petkov #define MSR_AMD_PERF_CTL		0xc0010062
392342061c5SBorislav Petkov #define MSR_AMD_PERF_STATUS		0xc0010063
393342061c5SBorislav Petkov #define MSR_AMD_PSTATE_DEF_BASE		0xc0010064
394b72e7464SBorislav Petkov #define MSR_AMD64_OSVW_ID_LENGTH	0xc0010140
395b72e7464SBorislav Petkov #define MSR_AMD64_OSVW_STATUS		0xc0010141
3964e3f77d8SJan Beulich #define MSR_AMD_PPIN_CTL		0xc00102f0
3974e3f77d8SJan Beulich #define MSR_AMD_PPIN			0xc00102f1
398b72e7464SBorislav Petkov #define MSR_AMD64_LS_CFG		0xc0011020
399b72e7464SBorislav Petkov #define MSR_AMD64_DC_CFG		0xc0011022
400b72e7464SBorislav Petkov #define MSR_AMD64_BU_CFG2		0xc001102a
401b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCHCTL		0xc0011030
402b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCHLINAD		0xc0011031
403b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCHPHYSAD	0xc0011032
404b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCH_REG_COUNT	3
405b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCH_REG_MASK	((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
406b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPCTL		0xc0011033
407b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPRIP		0xc0011034
408b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA		0xc0011035
409b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA2		0xc0011036
410b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA3		0xc0011037
411b72e7464SBorislav Petkov #define MSR_AMD64_IBSDCLINAD		0xc0011038
412b72e7464SBorislav Petkov #define MSR_AMD64_IBSDCPHYSAD		0xc0011039
413b72e7464SBorislav Petkov #define MSR_AMD64_IBSOP_REG_COUNT	7
414b72e7464SBorislav Petkov #define MSR_AMD64_IBSOP_REG_MASK	((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
415b72e7464SBorislav Petkov #define MSR_AMD64_IBSCTL		0xc001103a
416b72e7464SBorislav Petkov #define MSR_AMD64_IBSBRTARGET		0xc001103b
417b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA4		0xc001103d
418b72e7464SBorislav Petkov #define MSR_AMD64_IBS_REG_COUNT_MAX	8 /* includes MSR_AMD64_IBSBRTARGET */
4191958b5fcSTom Lendacky #define MSR_AMD64_SEV			0xc0010131
4201958b5fcSTom Lendacky #define MSR_AMD64_SEV_ENABLED_BIT	0
4211958b5fcSTom Lendacky #define MSR_AMD64_SEV_ENABLED		BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT)
422b72e7464SBorislav Petkov 
42311fb0683STom Lendacky #define MSR_AMD64_VIRT_SPEC_CTRL	0xc001011f
42411fb0683STom Lendacky 
425aaf24884SHuang Rui /* Fam 17h MSRs */
426aaf24884SHuang Rui #define MSR_F17H_IRPERF			0xc00000e9
427aaf24884SHuang Rui 
428b72e7464SBorislav Petkov /* Fam 16h MSRs */
429b72e7464SBorislav Petkov #define MSR_F16H_L2I_PERF_CTL		0xc0010230
430b72e7464SBorislav Petkov #define MSR_F16H_L2I_PERF_CTR		0xc0010231
431b72e7464SBorislav Petkov #define MSR_F16H_DR1_ADDR_MASK		0xc0011019
432b72e7464SBorislav Petkov #define MSR_F16H_DR2_ADDR_MASK		0xc001101a
433b72e7464SBorislav Petkov #define MSR_F16H_DR3_ADDR_MASK		0xc001101b
434b72e7464SBorislav Petkov #define MSR_F16H_DR0_ADDR_MASK		0xc0011027
435b72e7464SBorislav Petkov 
436b72e7464SBorislav Petkov /* Fam 15h MSRs */
437b72e7464SBorislav Petkov #define MSR_F15H_PERF_CTL		0xc0010200
438e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL0		MSR_F15H_PERF_CTL
439e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL1		(MSR_F15H_PERF_CTL + 2)
440e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL2		(MSR_F15H_PERF_CTL + 4)
441e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL3		(MSR_F15H_PERF_CTL + 6)
442e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL4		(MSR_F15H_PERF_CTL + 8)
443e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL5		(MSR_F15H_PERF_CTL + 10)
444e84b7119SJanakarajan Natarajan 
445b72e7464SBorislav Petkov #define MSR_F15H_PERF_CTR		0xc0010201
446e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR0		MSR_F15H_PERF_CTR
447e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR1		(MSR_F15H_PERF_CTR + 2)
448e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR2		(MSR_F15H_PERF_CTR + 4)
449e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR3		(MSR_F15H_PERF_CTR + 6)
450e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR4		(MSR_F15H_PERF_CTR + 8)
451e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR5		(MSR_F15H_PERF_CTR + 10)
452e84b7119SJanakarajan Natarajan 
453b72e7464SBorislav Petkov #define MSR_F15H_NB_PERF_CTL		0xc0010240
454b72e7464SBorislav Petkov #define MSR_F15H_NB_PERF_CTR		0xc0010241
4558a224261SHuang Rui #define MSR_F15H_PTSC			0xc0010280
456ae8b7875SBorislav Petkov #define MSR_F15H_IC_CFG			0xc0011021
4570e1b869fSEduardo Habkost #define MSR_F15H_EX_CFG			0xc001102c
458b72e7464SBorislav Petkov 
459b72e7464SBorislav Petkov /* Fam 10h MSRs */
460b72e7464SBorislav Petkov #define MSR_FAM10H_MMIO_CONF_BASE	0xc0010058
461b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_ENABLE		(1<<0)
462b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BUSRANGE_MASK	0xf
463b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
464b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BASE_MASK	0xfffffffULL
465b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BASE_SHIFT	20
466b72e7464SBorislav Petkov #define MSR_FAM10H_NODE_ID		0xc001100c
467e4d0e84eSTom Lendacky #define MSR_F10H_DECFG			0xc0011029
468e4d0e84eSTom Lendacky #define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT	1
4699c6a73c7STom Lendacky #define MSR_F10H_DECFG_LFENCE_SERIALIZE		BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT)
470b72e7464SBorislav Petkov 
471b72e7464SBorislav Petkov /* K8 MSRs */
472b72e7464SBorislav Petkov #define MSR_K8_TOP_MEM1			0xc001001a
473b72e7464SBorislav Petkov #define MSR_K8_TOP_MEM2			0xc001001d
474b72e7464SBorislav Petkov #define MSR_K8_SYSCFG			0xc0010010
475872cbefdSTom Lendacky #define MSR_K8_SYSCFG_MEM_ENCRYPT_BIT	23
476872cbefdSTom Lendacky #define MSR_K8_SYSCFG_MEM_ENCRYPT	BIT_ULL(MSR_K8_SYSCFG_MEM_ENCRYPT_BIT)
477b72e7464SBorislav Petkov #define MSR_K8_INT_PENDING_MSG		0xc0010055
478b72e7464SBorislav Petkov /* C1E active bits in int pending message */
479b72e7464SBorislav Petkov #define K8_INTP_C1E_ACTIVE_MASK		0x18000000
480b72e7464SBorislav Petkov #define MSR_K8_TSEG_ADDR		0xc0010112
4813afb1121SPaolo Bonzini #define MSR_K8_TSEG_MASK		0xc0010113
482b72e7464SBorislav Petkov #define K8_MTRRFIXRANGE_DRAM_ENABLE	0x00040000 /* MtrrFixDramEn bit    */
483b72e7464SBorislav Petkov #define K8_MTRRFIXRANGE_DRAM_MODIFY	0x00080000 /* MtrrFixDramModEn bit */
484b72e7464SBorislav Petkov #define K8_MTRR_RDMEM_WRMEM_MASK	0x18181818 /* Mask: RdMem|WrMem    */
485b72e7464SBorislav Petkov 
486b72e7464SBorislav Petkov /* K7 MSRs */
487b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL0			0xc0010000
488b72e7464SBorislav Petkov #define MSR_K7_PERFCTR0			0xc0010004
489b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL1			0xc0010001
490b72e7464SBorislav Petkov #define MSR_K7_PERFCTR1			0xc0010005
491b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL2			0xc0010002
492b72e7464SBorislav Petkov #define MSR_K7_PERFCTR2			0xc0010006
493b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL3			0xc0010003
494b72e7464SBorislav Petkov #define MSR_K7_PERFCTR3			0xc0010007
495b72e7464SBorislav Petkov #define MSR_K7_CLK_CTL			0xc001001b
496b72e7464SBorislav Petkov #define MSR_K7_HWCR			0xc0010015
49718c71ce9STom Lendacky #define MSR_K7_HWCR_SMMLOCK_BIT		0
49818c71ce9STom Lendacky #define MSR_K7_HWCR_SMMLOCK		BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT)
499b72e7464SBorislav Petkov #define MSR_K7_FID_VID_CTL		0xc0010041
500b72e7464SBorislav Petkov #define MSR_K7_FID_VID_STATUS		0xc0010042
501b72e7464SBorislav Petkov 
502b72e7464SBorislav Petkov /* K6 MSRs */
503b72e7464SBorislav Petkov #define MSR_K6_WHCR			0xc0000082
504b72e7464SBorislav Petkov #define MSR_K6_UWCCR			0xc0000085
505b72e7464SBorislav Petkov #define MSR_K6_EPMR			0xc0000086
506b72e7464SBorislav Petkov #define MSR_K6_PSOR			0xc0000087
507b72e7464SBorislav Petkov #define MSR_K6_PFIR			0xc0000088
508b72e7464SBorislav Petkov 
509b72e7464SBorislav Petkov /* Centaur-Hauls/IDT defined MSRs. */
510b72e7464SBorislav Petkov #define MSR_IDT_FCR1			0x00000107
511b72e7464SBorislav Petkov #define MSR_IDT_FCR2			0x00000108
512b72e7464SBorislav Petkov #define MSR_IDT_FCR3			0x00000109
513b72e7464SBorislav Petkov #define MSR_IDT_FCR4			0x0000010a
514b72e7464SBorislav Petkov 
515b72e7464SBorislav Petkov #define MSR_IDT_MCR0			0x00000110
516b72e7464SBorislav Petkov #define MSR_IDT_MCR1			0x00000111
517b72e7464SBorislav Petkov #define MSR_IDT_MCR2			0x00000112
518b72e7464SBorislav Petkov #define MSR_IDT_MCR3			0x00000113
519b72e7464SBorislav Petkov #define MSR_IDT_MCR4			0x00000114
520b72e7464SBorislav Petkov #define MSR_IDT_MCR5			0x00000115
521b72e7464SBorislav Petkov #define MSR_IDT_MCR6			0x00000116
522b72e7464SBorislav Petkov #define MSR_IDT_MCR7			0x00000117
523b72e7464SBorislav Petkov #define MSR_IDT_MCR_CTRL		0x00000120
524b72e7464SBorislav Petkov 
525b72e7464SBorislav Petkov /* VIA Cyrix defined MSRs*/
526b72e7464SBorislav Petkov #define MSR_VIA_FCR			0x00001107
527b72e7464SBorislav Petkov #define MSR_VIA_LONGHAUL		0x0000110a
528b72e7464SBorislav Petkov #define MSR_VIA_RNG			0x0000110b
529b72e7464SBorislav Petkov #define MSR_VIA_BCR2			0x00001147
530b72e7464SBorislav Petkov 
531b72e7464SBorislav Petkov /* Transmeta defined MSRs */
532b72e7464SBorislav Petkov #define MSR_TMTA_LONGRUN_CTRL		0x80868010
533b72e7464SBorislav Petkov #define MSR_TMTA_LONGRUN_FLAGS		0x80868011
534b72e7464SBorislav Petkov #define MSR_TMTA_LRTI_READOUT		0x80868018
535b72e7464SBorislav Petkov #define MSR_TMTA_LRTI_VOLT_MHZ		0x8086801a
536b72e7464SBorislav Petkov 
537b72e7464SBorislav Petkov /* Intel defined MSRs. */
538b72e7464SBorislav Petkov #define MSR_IA32_P5_MC_ADDR		0x00000000
539b72e7464SBorislav Petkov #define MSR_IA32_P5_MC_TYPE		0x00000001
540b72e7464SBorislav Petkov #define MSR_IA32_TSC			0x00000010
541b72e7464SBorislav Petkov #define MSR_IA32_PLATFORM_ID		0x00000017
542b72e7464SBorislav Petkov #define MSR_IA32_EBL_CR_POWERON		0x0000002a
543b72e7464SBorislav Petkov #define MSR_EBC_FREQUENCY_ID		0x0000002c
544b72e7464SBorislav Petkov #define MSR_SMI_COUNT			0x00000034
545b72e7464SBorislav Petkov #define MSR_IA32_FEATURE_CONTROL        0x0000003a
546b72e7464SBorislav Petkov #define MSR_IA32_TSC_ADJUST             0x0000003b
547b72e7464SBorislav Petkov #define MSR_IA32_BNDCFGS		0x00000d90
548b72e7464SBorislav Petkov 
5494531662dSJim Mattson #define MSR_IA32_BNDCFGS_RSVD		0x00000ffc
5504531662dSJim Mattson 
551b72e7464SBorislav Petkov #define MSR_IA32_XSS			0x00000da0
552b72e7464SBorislav Petkov 
553b72e7464SBorislav Petkov #define FEATURE_CONTROL_LOCKED				(1<<0)
554b72e7464SBorislav Petkov #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX	(1<<1)
555b72e7464SBorislav Petkov #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX	(1<<2)
556b72e7464SBorislav Petkov #define FEATURE_CONTROL_LMCE				(1<<20)
557b72e7464SBorislav Petkov 
558b72e7464SBorislav Petkov #define MSR_IA32_APICBASE		0x0000001b
559b72e7464SBorislav Petkov #define MSR_IA32_APICBASE_BSP		(1<<8)
560b72e7464SBorislav Petkov #define MSR_IA32_APICBASE_ENABLE	(1<<11)
561b72e7464SBorislav Petkov #define MSR_IA32_APICBASE_BASE		(0xfffff<<12)
562b72e7464SBorislav Petkov 
563b72e7464SBorislav Petkov #define MSR_IA32_TSCDEADLINE		0x000006e0
564b72e7464SBorislav Petkov 
565b72e7464SBorislav Petkov #define MSR_IA32_UCODE_WRITE		0x00000079
566b72e7464SBorislav Petkov #define MSR_IA32_UCODE_REV		0x0000008b
567b72e7464SBorislav Petkov 
568b72e7464SBorislav Petkov #define MSR_IA32_SMM_MONITOR_CTL	0x0000009b
569b72e7464SBorislav Petkov #define MSR_IA32_SMBASE			0x0000009e
570b72e7464SBorislav Petkov 
571b72e7464SBorislav Petkov #define MSR_IA32_PERF_STATUS		0x00000198
572b72e7464SBorislav Petkov #define MSR_IA32_PERF_CTL		0x00000199
573b72e7464SBorislav Petkov #define INTEL_PERF_CTL_MASK		0xffff
574b72e7464SBorislav Petkov 
575b72e7464SBorislav Petkov #define MSR_IA32_MPERF			0x000000e7
576b72e7464SBorislav Petkov #define MSR_IA32_APERF			0x000000e8
577b72e7464SBorislav Petkov 
578b72e7464SBorislav Petkov #define MSR_IA32_THERM_CONTROL		0x0000019a
579b72e7464SBorislav Petkov #define MSR_IA32_THERM_INTERRUPT	0x0000019b
580b72e7464SBorislav Petkov 
581b72e7464SBorislav Petkov #define THERM_INT_HIGH_ENABLE		(1 << 0)
582b72e7464SBorislav Petkov #define THERM_INT_LOW_ENABLE		(1 << 1)
583b72e7464SBorislav Petkov #define THERM_INT_PLN_ENABLE		(1 << 24)
584b72e7464SBorislav Petkov 
585b72e7464SBorislav Petkov #define MSR_IA32_THERM_STATUS		0x0000019c
586b72e7464SBorislav Petkov 
587b72e7464SBorislav Petkov #define THERM_STATUS_PROCHOT		(1 << 0)
588b72e7464SBorislav Petkov #define THERM_STATUS_POWER_LIMIT	(1 << 10)
589b72e7464SBorislav Petkov 
590b72e7464SBorislav Petkov #define MSR_THERM2_CTL			0x0000019d
591b72e7464SBorislav Petkov 
592b72e7464SBorislav Petkov #define MSR_THERM2_CTL_TM_SELECT	(1ULL << 16)
593b72e7464SBorislav Petkov 
594b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE		0x000001a0
595b72e7464SBorislav Petkov 
596b72e7464SBorislav Petkov #define MSR_IA32_TEMPERATURE_TARGET	0x000001a2
597b72e7464SBorislav Petkov 
59898af7459SLen Brown #define MSR_MISC_FEATURE_CONTROL	0x000001a4
599b72e7464SBorislav Petkov #define MSR_MISC_PWR_MGMT		0x000001aa
600b72e7464SBorislav Petkov 
601b72e7464SBorislav Petkov #define MSR_IA32_ENERGY_PERF_BIAS	0x000001b0
602b72e7464SBorislav Petkov #define ENERGY_PERF_BIAS_PERFORMANCE		0
603d0117a0eSLen Brown #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE	4
604b72e7464SBorislav Petkov #define ENERGY_PERF_BIAS_NORMAL			6
605d0117a0eSLen Brown #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE	8
606b72e7464SBorislav Petkov #define ENERGY_PERF_BIAS_POWERSAVE		15
607b72e7464SBorislav Petkov 
608b72e7464SBorislav Petkov #define MSR_IA32_PACKAGE_THERM_STATUS		0x000001b1
609b72e7464SBorislav Petkov 
610b72e7464SBorislav Petkov #define PACKAGE_THERM_STATUS_PROCHOT		(1 << 0)
611b72e7464SBorislav Petkov #define PACKAGE_THERM_STATUS_POWER_LIMIT	(1 << 10)
612b72e7464SBorislav Petkov 
613b72e7464SBorislav Petkov #define MSR_IA32_PACKAGE_THERM_INTERRUPT	0x000001b2
614b72e7464SBorislav Petkov 
615b72e7464SBorislav Petkov #define PACKAGE_THERM_INT_HIGH_ENABLE		(1 << 0)
616b72e7464SBorislav Petkov #define PACKAGE_THERM_INT_LOW_ENABLE		(1 << 1)
617b72e7464SBorislav Petkov #define PACKAGE_THERM_INT_PLN_ENABLE		(1 << 24)
618b72e7464SBorislav Petkov 
619b72e7464SBorislav Petkov /* Thermal Thresholds Support */
620b72e7464SBorislav Petkov #define THERM_INT_THRESHOLD0_ENABLE    (1 << 15)
621b72e7464SBorislav Petkov #define THERM_SHIFT_THRESHOLD0        8
622b72e7464SBorislav Petkov #define THERM_MASK_THRESHOLD0          (0x7f << THERM_SHIFT_THRESHOLD0)
623b72e7464SBorislav Petkov #define THERM_INT_THRESHOLD1_ENABLE    (1 << 23)
624b72e7464SBorislav Petkov #define THERM_SHIFT_THRESHOLD1        16
625b72e7464SBorislav Petkov #define THERM_MASK_THRESHOLD1          (0x7f << THERM_SHIFT_THRESHOLD1)
626b72e7464SBorislav Petkov #define THERM_STATUS_THRESHOLD0        (1 << 6)
627b72e7464SBorislav Petkov #define THERM_LOG_THRESHOLD0           (1 << 7)
628b72e7464SBorislav Petkov #define THERM_STATUS_THRESHOLD1        (1 << 8)
629b72e7464SBorislav Petkov #define THERM_LOG_THRESHOLD1           (1 << 9)
630b72e7464SBorislav Petkov 
631b72e7464SBorislav Petkov /* MISC_ENABLE bits: architectural */
632b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT		0
633b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FAST_STRING		(1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT)
634b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TCC_BIT			1
635b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TCC			(1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT)
636b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_EMON_BIT			7
637b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_EMON			(1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT)
638b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT		11
639b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL		(1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT)
640b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT		12
641b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL		(1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT)
642b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT	16
643b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP		(1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT)
644b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_MWAIT_BIT			18
645b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_MWAIT			(1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT)
646b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT		22
647b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID		(1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT)
648b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT		23
649b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE		(1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT)
650b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT		34
651b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XD_DISABLE			(1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT)
652b72e7464SBorislav Petkov 
653b72e7464SBorislav Petkov /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
654b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT		2
655b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_X87_COMPAT			(1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT)
656b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM1_BIT			3
657b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM1			(1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT)
658b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT	4
659b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE		(1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT)
660b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT	6
661b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE		(1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT)
662b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT		8
663b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK		(1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT)
664b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT	9
665b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE		(1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
666b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR_BIT			10
667b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR			(1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT)
668b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT		10
669b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX		(1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT)
670b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM2_BIT			13
671b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM2			(1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT)
672b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT	19
673b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE		(1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT)
674b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT		20
675b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK		(1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT)
676b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT		24
677b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT		(1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT)
678b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT	37
679b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE		(1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT)
680b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT		38
681b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE		(1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT)
682b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT	39
683b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE		(1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
684b72e7464SBorislav Petkov 
685ab6d9468SKyle Huey /* MISC_FEATURES_ENABLES non-architectural features */
686ab6d9468SKyle Huey #define MSR_MISC_FEATURES_ENABLES	0x00000140
687ae47eda9SGrzegorz Andrejczuk 
688e9ea1e7fSKyle Huey #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT	0
689e9ea1e7fSKyle Huey #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT		BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT)
690ab6d9468SKyle Huey #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT	1
691ae47eda9SGrzegorz Andrejczuk 
692b72e7464SBorislav Petkov #define MSR_IA32_TSC_DEADLINE		0x000006E0
693b72e7464SBorislav Petkov 
69452f64909SPeter Zijlstra (Intel) 
69552f64909SPeter Zijlstra (Intel) #define MSR_TSX_FORCE_ABORT		0x0000010F
69652f64909SPeter Zijlstra (Intel) 
69752f64909SPeter Zijlstra (Intel) #define MSR_TFA_RTM_FORCE_ABORT_BIT	0
69852f64909SPeter Zijlstra (Intel) #define MSR_TFA_RTM_FORCE_ABORT		BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT)
69952f64909SPeter Zijlstra (Intel) 
700b72e7464SBorislav Petkov /* P4/Xeon+ specific */
701b72e7464SBorislav Petkov #define MSR_IA32_MCG_EAX		0x00000180
702b72e7464SBorislav Petkov #define MSR_IA32_MCG_EBX		0x00000181
703b72e7464SBorislav Petkov #define MSR_IA32_MCG_ECX		0x00000182
704b72e7464SBorislav Petkov #define MSR_IA32_MCG_EDX		0x00000183
705b72e7464SBorislav Petkov #define MSR_IA32_MCG_ESI		0x00000184
706b72e7464SBorislav Petkov #define MSR_IA32_MCG_EDI		0x00000185
707b72e7464SBorislav Petkov #define MSR_IA32_MCG_EBP		0x00000186
708b72e7464SBorislav Petkov #define MSR_IA32_MCG_ESP		0x00000187
709b72e7464SBorislav Petkov #define MSR_IA32_MCG_EFLAGS		0x00000188
710b72e7464SBorislav Petkov #define MSR_IA32_MCG_EIP		0x00000189
711b72e7464SBorislav Petkov #define MSR_IA32_MCG_RESERVED		0x0000018a
712b72e7464SBorislav Petkov 
713b72e7464SBorislav Petkov /* Pentium IV performance counter MSRs */
714b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR0		0x00000300
715b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR1		0x00000301
716b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR2		0x00000302
717b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR3		0x00000303
718b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR0		0x00000304
719b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR1		0x00000305
720b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR2		0x00000306
721b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR3		0x00000307
722b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR0		0x00000308
723b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR1		0x00000309
724b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR2		0x0000030a
725b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR3		0x0000030b
726b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR0		0x0000030c
727b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR1		0x0000030d
728b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR2		0x0000030e
729b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR3		0x0000030f
730b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR4		0x00000310
731b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR5		0x00000311
732b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR0		0x00000360
733b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR1		0x00000361
734b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR2		0x00000362
735b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR3		0x00000363
736b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR0			0x00000364
737b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR1			0x00000365
738b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR2			0x00000366
739b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR3			0x00000367
740b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR0		0x00000368
741b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR1		0x00000369
742b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR2		0x0000036a
743b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR3		0x0000036b
744b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR0			0x0000036c
745b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR1			0x0000036d
746b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR2			0x0000036e
747b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR3			0x0000036f
748b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR4			0x00000370
749b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR5			0x00000371
750b72e7464SBorislav Petkov #define MSR_P4_ALF_ESCR0		0x000003ca
751b72e7464SBorislav Petkov #define MSR_P4_ALF_ESCR1		0x000003cb
752b72e7464SBorislav Petkov #define MSR_P4_BPU_ESCR0		0x000003b2
753b72e7464SBorislav Petkov #define MSR_P4_BPU_ESCR1		0x000003b3
754b72e7464SBorislav Petkov #define MSR_P4_BSU_ESCR0		0x000003a0
755b72e7464SBorislav Petkov #define MSR_P4_BSU_ESCR1		0x000003a1
756b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR0		0x000003b8
757b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR1		0x000003b9
758b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR2		0x000003cc
759b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR3		0x000003cd
760b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR4		0x000003e0
761b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR5		0x000003e1
762b72e7464SBorislav Petkov #define MSR_P4_DAC_ESCR0		0x000003a8
763b72e7464SBorislav Petkov #define MSR_P4_DAC_ESCR1		0x000003a9
764b72e7464SBorislav Petkov #define MSR_P4_FIRM_ESCR0		0x000003a4
765b72e7464SBorislav Petkov #define MSR_P4_FIRM_ESCR1		0x000003a5
766b72e7464SBorislav Petkov #define MSR_P4_FLAME_ESCR0		0x000003a6
767b72e7464SBorislav Petkov #define MSR_P4_FLAME_ESCR1		0x000003a7
768b72e7464SBorislav Petkov #define MSR_P4_FSB_ESCR0		0x000003a2
769b72e7464SBorislav Petkov #define MSR_P4_FSB_ESCR1		0x000003a3
770b72e7464SBorislav Petkov #define MSR_P4_IQ_ESCR0			0x000003ba
771b72e7464SBorislav Petkov #define MSR_P4_IQ_ESCR1			0x000003bb
772b72e7464SBorislav Petkov #define MSR_P4_IS_ESCR0			0x000003b4
773b72e7464SBorislav Petkov #define MSR_P4_IS_ESCR1			0x000003b5
774b72e7464SBorislav Petkov #define MSR_P4_ITLB_ESCR0		0x000003b6
775b72e7464SBorislav Petkov #define MSR_P4_ITLB_ESCR1		0x000003b7
776b72e7464SBorislav Petkov #define MSR_P4_IX_ESCR0			0x000003c8
777b72e7464SBorislav Petkov #define MSR_P4_IX_ESCR1			0x000003c9
778b72e7464SBorislav Petkov #define MSR_P4_MOB_ESCR0		0x000003aa
779b72e7464SBorislav Petkov #define MSR_P4_MOB_ESCR1		0x000003ab
780b72e7464SBorislav Petkov #define MSR_P4_MS_ESCR0			0x000003c0
781b72e7464SBorislav Petkov #define MSR_P4_MS_ESCR1			0x000003c1
782b72e7464SBorislav Petkov #define MSR_P4_PMH_ESCR0		0x000003ac
783b72e7464SBorislav Petkov #define MSR_P4_PMH_ESCR1		0x000003ad
784b72e7464SBorislav Petkov #define MSR_P4_RAT_ESCR0		0x000003bc
785b72e7464SBorislav Petkov #define MSR_P4_RAT_ESCR1		0x000003bd
786b72e7464SBorislav Petkov #define MSR_P4_SAAT_ESCR0		0x000003ae
787b72e7464SBorislav Petkov #define MSR_P4_SAAT_ESCR1		0x000003af
788b72e7464SBorislav Petkov #define MSR_P4_SSU_ESCR0		0x000003be
789b72e7464SBorislav Petkov #define MSR_P4_SSU_ESCR1		0x000003bf /* guess: not in manual */
790b72e7464SBorislav Petkov 
791b72e7464SBorislav Petkov #define MSR_P4_TBPU_ESCR0		0x000003c2
792b72e7464SBorislav Petkov #define MSR_P4_TBPU_ESCR1		0x000003c3
793b72e7464SBorislav Petkov #define MSR_P4_TC_ESCR0			0x000003c4
794b72e7464SBorislav Petkov #define MSR_P4_TC_ESCR1			0x000003c5
795b72e7464SBorislav Petkov #define MSR_P4_U2L_ESCR0		0x000003b0
796b72e7464SBorislav Petkov #define MSR_P4_U2L_ESCR1		0x000003b1
797b72e7464SBorislav Petkov 
798b72e7464SBorislav Petkov #define MSR_P4_PEBS_MATRIX_VERT		0x000003f2
799b72e7464SBorislav Petkov 
800b72e7464SBorislav Petkov /* Intel Core-based CPU performance counters */
801b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR0	0x00000309
802b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR1	0x0000030a
803b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR2	0x0000030b
804b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR_CTRL	0x0000038d
805b72e7464SBorislav Petkov #define MSR_CORE_PERF_GLOBAL_STATUS	0x0000038e
806b72e7464SBorislav Petkov #define MSR_CORE_PERF_GLOBAL_CTRL	0x0000038f
807b72e7464SBorislav Petkov #define MSR_CORE_PERF_GLOBAL_OVF_CTRL	0x00000390
808b72e7464SBorislav Petkov 
8098479e04eSLuwei Kang /* PERF_GLOBAL_OVF_CTL bits */
8108479e04eSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT	55
8118479e04eSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI		(1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT)
812c715eb9fSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT		62
813c715eb9fSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF			(1ULL <<  MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT)
814c715eb9fSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT		63
815c715eb9fSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD			(1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT)
8168479e04eSLuwei Kang 
817b72e7464SBorislav Petkov /* Geode defined MSRs */
818b72e7464SBorislav Petkov #define MSR_GEODE_BUSCONT_CONF0		0x00001900
819b72e7464SBorislav Petkov 
820b72e7464SBorislav Petkov /* Intel VT MSRs */
821b72e7464SBorislav Petkov #define MSR_IA32_VMX_BASIC              0x00000480
822b72e7464SBorislav Petkov #define MSR_IA32_VMX_PINBASED_CTLS      0x00000481
823b72e7464SBorislav Petkov #define MSR_IA32_VMX_PROCBASED_CTLS     0x00000482
824b72e7464SBorislav Petkov #define MSR_IA32_VMX_EXIT_CTLS          0x00000483
825b72e7464SBorislav Petkov #define MSR_IA32_VMX_ENTRY_CTLS         0x00000484
826b72e7464SBorislav Petkov #define MSR_IA32_VMX_MISC               0x00000485
827b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR0_FIXED0         0x00000486
828b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR0_FIXED1         0x00000487
829b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR4_FIXED0         0x00000488
830b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR4_FIXED1         0x00000489
831b72e7464SBorislav Petkov #define MSR_IA32_VMX_VMCS_ENUM          0x0000048a
832b72e7464SBorislav Petkov #define MSR_IA32_VMX_PROCBASED_CTLS2    0x0000048b
833b72e7464SBorislav Petkov #define MSR_IA32_VMX_EPT_VPID_CAP       0x0000048c
834b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_PINBASED_CTLS  0x0000048d
835b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
836b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_EXIT_CTLS      0x0000048f
837b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_ENTRY_CTLS     0x00000490
838b72e7464SBorislav Petkov #define MSR_IA32_VMX_VMFUNC             0x00000491
839b72e7464SBorislav Petkov 
840b72e7464SBorislav Petkov /* VMX_BASIC bits and bitmasks */
841b72e7464SBorislav Petkov #define VMX_BASIC_VMCS_SIZE_SHIFT	32
842b72e7464SBorislav Petkov #define VMX_BASIC_TRUE_CTLS		(1ULL << 55)
843b72e7464SBorislav Petkov #define VMX_BASIC_64		0x0001000000000000LLU
844b72e7464SBorislav Petkov #define VMX_BASIC_MEM_TYPE_SHIFT	50
845b72e7464SBorislav Petkov #define VMX_BASIC_MEM_TYPE_MASK	0x003c000000000000LLU
846b72e7464SBorislav Petkov #define VMX_BASIC_MEM_TYPE_WB	6LLU
847b72e7464SBorislav Petkov #define VMX_BASIC_INOUT		0x0040000000000000LLU
848b72e7464SBorislav Petkov 
849b72e7464SBorislav Petkov /* MSR_IA32_VMX_MISC bits */
850f99e3dafSChao Peng #define MSR_IA32_VMX_MISC_INTEL_PT                 (1ULL << 14)
851b72e7464SBorislav Petkov #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
852b72e7464SBorislav Petkov #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE   0x1F
853b72e7464SBorislav Petkov /* AMD-V MSRs */
854b72e7464SBorislav Petkov 
855b72e7464SBorislav Petkov #define MSR_VM_CR                       0xc0010114
856b72e7464SBorislav Petkov #define MSR_VM_IGNNE                    0xc0010115
857b72e7464SBorislav Petkov #define MSR_VM_HSAVE_PA                 0xc0010117
858b72e7464SBorislav Petkov 
859b72e7464SBorislav Petkov #endif /* _ASM_X86_MSR_INDEX_H */
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