1b72e7464SBorislav Petkov #ifndef _ASM_X86_MSR_INDEX_H 2b72e7464SBorislav Petkov #define _ASM_X86_MSR_INDEX_H 3b72e7464SBorislav Petkov 4b72e7464SBorislav Petkov /* CPU model specific register (MSR) numbers */ 5b72e7464SBorislav Petkov 6b72e7464SBorislav Petkov /* x86-64 specific MSRs */ 7b72e7464SBorislav Petkov #define MSR_EFER 0xc0000080 /* extended feature register */ 8b72e7464SBorislav Petkov #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 9b72e7464SBorislav Petkov #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 10b72e7464SBorislav Petkov #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 11b72e7464SBorislav Petkov #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 12b72e7464SBorislav Petkov #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 13b72e7464SBorislav Petkov #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 14b72e7464SBorislav Petkov #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 15b72e7464SBorislav Petkov #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 16b72e7464SBorislav Petkov 17b72e7464SBorislav Petkov /* EFER bits: */ 18b72e7464SBorislav Petkov #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 19b72e7464SBorislav Petkov #define _EFER_LME 8 /* Long mode enable */ 20b72e7464SBorislav Petkov #define _EFER_LMA 10 /* Long mode active (read-only) */ 21b72e7464SBorislav Petkov #define _EFER_NX 11 /* No execute enable */ 22b72e7464SBorislav Petkov #define _EFER_SVME 12 /* Enable virtualization */ 23b72e7464SBorislav Petkov #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 24b72e7464SBorislav Petkov #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 25b72e7464SBorislav Petkov 26b72e7464SBorislav Petkov #define EFER_SCE (1<<_EFER_SCE) 27b72e7464SBorislav Petkov #define EFER_LME (1<<_EFER_LME) 28b72e7464SBorislav Petkov #define EFER_LMA (1<<_EFER_LMA) 29b72e7464SBorislav Petkov #define EFER_NX (1<<_EFER_NX) 30b72e7464SBorislav Petkov #define EFER_SVME (1<<_EFER_SVME) 31b72e7464SBorislav Petkov #define EFER_LMSLE (1<<_EFER_LMSLE) 32b72e7464SBorislav Petkov #define EFER_FFXSR (1<<_EFER_FFXSR) 33b72e7464SBorislav Petkov 34b72e7464SBorislav Petkov /* Intel MSRs. Some also available on other CPUs */ 35b72e7464SBorislav Petkov #define MSR_IA32_PERFCTR0 0x000000c1 36b72e7464SBorislav Petkov #define MSR_IA32_PERFCTR1 0x000000c2 37b72e7464SBorislav Petkov #define MSR_FSB_FREQ 0x000000cd 38b72e7464SBorislav Petkov #define MSR_NHM_PLATFORM_INFO 0x000000ce 39b72e7464SBorislav Petkov 40b72e7464SBorislav Petkov #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 41b72e7464SBorislav Petkov #define NHM_C3_AUTO_DEMOTE (1UL << 25) 42b72e7464SBorislav Petkov #define NHM_C1_AUTO_DEMOTE (1UL << 26) 43b72e7464SBorislav Petkov #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 44b72e7464SBorislav Petkov #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 45b72e7464SBorislav Petkov #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 46b72e7464SBorislav Petkov 47b72e7464SBorislav Petkov #define MSR_PLATFORM_INFO 0x000000ce 48b72e7464SBorislav Petkov #define MSR_MTRRcap 0x000000fe 49b72e7464SBorislav Petkov #define MSR_IA32_BBL_CR_CTL 0x00000119 50b72e7464SBorislav Petkov #define MSR_IA32_BBL_CR_CTL3 0x0000011e 51b72e7464SBorislav Petkov 52b72e7464SBorislav Petkov #define MSR_IA32_SYSENTER_CS 0x00000174 53b72e7464SBorislav Petkov #define MSR_IA32_SYSENTER_ESP 0x00000175 54b72e7464SBorislav Petkov #define MSR_IA32_SYSENTER_EIP 0x00000176 55b72e7464SBorislav Petkov 56b72e7464SBorislav Petkov #define MSR_IA32_MCG_CAP 0x00000179 57b72e7464SBorislav Petkov #define MSR_IA32_MCG_STATUS 0x0000017a 58b72e7464SBorislav Petkov #define MSR_IA32_MCG_CTL 0x0000017b 59b72e7464SBorislav Petkov #define MSR_IA32_MCG_EXT_CTL 0x000004d0 60b72e7464SBorislav Petkov 61b72e7464SBorislav Petkov #define MSR_OFFCORE_RSP_0 0x000001a6 62b72e7464SBorislav Petkov #define MSR_OFFCORE_RSP_1 0x000001a7 63b72e7464SBorislav Petkov #define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad 64b72e7464SBorislav Petkov #define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae 65b72e7464SBorislav Petkov #define MSR_TURBO_RATIO_LIMIT 0x000001ad 66b72e7464SBorislav Petkov #define MSR_TURBO_RATIO_LIMIT1 0x000001ae 67b72e7464SBorislav Petkov #define MSR_TURBO_RATIO_LIMIT2 0x000001af 68b72e7464SBorislav Petkov 69b72e7464SBorislav Petkov #define MSR_LBR_SELECT 0x000001c8 70b72e7464SBorislav Petkov #define MSR_LBR_TOS 0x000001c9 71b72e7464SBorislav Petkov #define MSR_LBR_NHM_FROM 0x00000680 72b72e7464SBorislav Petkov #define MSR_LBR_NHM_TO 0x000006c0 73b72e7464SBorislav Petkov #define MSR_LBR_CORE_FROM 0x00000040 74b72e7464SBorislav Petkov #define MSR_LBR_CORE_TO 0x00000060 75b72e7464SBorislav Petkov 76b83ff1c8SAndi Kleen #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 77b83ff1c8SAndi Kleen #define LBR_INFO_MISPRED BIT_ULL(63) 78b83ff1c8SAndi Kleen #define LBR_INFO_IN_TX BIT_ULL(62) 79b83ff1c8SAndi Kleen #define LBR_INFO_ABORT BIT_ULL(61) 80b83ff1c8SAndi Kleen #define LBR_INFO_CYCLES 0xffff 81b83ff1c8SAndi Kleen 82b72e7464SBorislav Petkov #define MSR_IA32_PEBS_ENABLE 0x000003f1 83b72e7464SBorislav Petkov #define MSR_IA32_DS_AREA 0x00000600 84b72e7464SBorislav Petkov #define MSR_IA32_PERF_CAPABILITIES 0x00000345 85b72e7464SBorislav Petkov #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 86b72e7464SBorislav Petkov 87b72e7464SBorislav Petkov #define MSR_IA32_RTIT_CTL 0x00000570 88b72e7464SBorislav Petkov #define RTIT_CTL_TRACEEN BIT(0) 89b1bf72d6SAlexander Shishkin #define RTIT_CTL_CYCLEACC BIT(1) 90b72e7464SBorislav Petkov #define RTIT_CTL_OS BIT(2) 91b72e7464SBorislav Petkov #define RTIT_CTL_USR BIT(3) 92b72e7464SBorislav Petkov #define RTIT_CTL_CR3EN BIT(7) 93b72e7464SBorislav Petkov #define RTIT_CTL_TOPA BIT(8) 94b1bf72d6SAlexander Shishkin #define RTIT_CTL_MTC_EN BIT(9) 95b72e7464SBorislav Petkov #define RTIT_CTL_TSC_EN BIT(10) 96b72e7464SBorislav Petkov #define RTIT_CTL_DISRETC BIT(11) 97b72e7464SBorislav Petkov #define RTIT_CTL_BRANCH_EN BIT(13) 98b1bf72d6SAlexander Shishkin #define RTIT_CTL_MTC_RANGE_OFFSET 14 99b1bf72d6SAlexander Shishkin #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 100b1bf72d6SAlexander Shishkin #define RTIT_CTL_CYC_THRESH_OFFSET 19 101b1bf72d6SAlexander Shishkin #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 102b1bf72d6SAlexander Shishkin #define RTIT_CTL_PSB_FREQ_OFFSET 24 103b1bf72d6SAlexander Shishkin #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 104b72e7464SBorislav Petkov #define MSR_IA32_RTIT_STATUS 0x00000571 105b72e7464SBorislav Petkov #define RTIT_STATUS_CONTEXTEN BIT(1) 106b72e7464SBorislav Petkov #define RTIT_STATUS_TRIGGEREN BIT(2) 107b72e7464SBorislav Petkov #define RTIT_STATUS_ERROR BIT(4) 108b72e7464SBorislav Petkov #define RTIT_STATUS_STOPPED BIT(5) 109b72e7464SBorislav Petkov #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 110b72e7464SBorislav Petkov #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 111b72e7464SBorislav Petkov #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 112b72e7464SBorislav Petkov 113b72e7464SBorislav Petkov #define MSR_MTRRfix64K_00000 0x00000250 114b72e7464SBorislav Petkov #define MSR_MTRRfix16K_80000 0x00000258 115b72e7464SBorislav Petkov #define MSR_MTRRfix16K_A0000 0x00000259 116b72e7464SBorislav Petkov #define MSR_MTRRfix4K_C0000 0x00000268 117b72e7464SBorislav Petkov #define MSR_MTRRfix4K_C8000 0x00000269 118b72e7464SBorislav Petkov #define MSR_MTRRfix4K_D0000 0x0000026a 119b72e7464SBorislav Petkov #define MSR_MTRRfix4K_D8000 0x0000026b 120b72e7464SBorislav Petkov #define MSR_MTRRfix4K_E0000 0x0000026c 121b72e7464SBorislav Petkov #define MSR_MTRRfix4K_E8000 0x0000026d 122b72e7464SBorislav Petkov #define MSR_MTRRfix4K_F0000 0x0000026e 123b72e7464SBorislav Petkov #define MSR_MTRRfix4K_F8000 0x0000026f 124b72e7464SBorislav Petkov #define MSR_MTRRdefType 0x000002ff 125b72e7464SBorislav Petkov 126b72e7464SBorislav Petkov #define MSR_IA32_CR_PAT 0x00000277 127b72e7464SBorislav Petkov 128b72e7464SBorislav Petkov #define MSR_IA32_DEBUGCTLMSR 0x000001d9 129b72e7464SBorislav Petkov #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 130b72e7464SBorislav Petkov #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 131b72e7464SBorislav Petkov #define MSR_IA32_LASTINTFROMIP 0x000001dd 132b72e7464SBorislav Petkov #define MSR_IA32_LASTINTTOIP 0x000001de 133b72e7464SBorislav Petkov 134b72e7464SBorislav Petkov /* DEBUGCTLMSR bits (others vary by model): */ 135b72e7464SBorislav Petkov #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 136b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 137b72e7464SBorislav Petkov #define DEBUGCTLMSR_TR (1UL << 6) 138b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTS (1UL << 7) 139b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTINT (1UL << 8) 140b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 141b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 142b72e7464SBorislav Petkov #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 143b72e7464SBorislav Petkov 144b72e7464SBorislav Petkov #define MSR_IA32_POWER_CTL 0x000001fc 145b72e7464SBorislav Petkov 146b72e7464SBorislav Petkov #define MSR_IA32_MC0_CTL 0x00000400 147b72e7464SBorislav Petkov #define MSR_IA32_MC0_STATUS 0x00000401 148b72e7464SBorislav Petkov #define MSR_IA32_MC0_ADDR 0x00000402 149b72e7464SBorislav Petkov #define MSR_IA32_MC0_MISC 0x00000403 150b72e7464SBorislav Petkov 151b72e7464SBorislav Petkov /* C-state Residency Counters */ 152b72e7464SBorislav Petkov #define MSR_PKG_C3_RESIDENCY 0x000003f8 153b72e7464SBorislav Petkov #define MSR_PKG_C6_RESIDENCY 0x000003f9 154b72e7464SBorislav Petkov #define MSR_PKG_C7_RESIDENCY 0x000003fa 155b72e7464SBorislav Petkov #define MSR_CORE_C3_RESIDENCY 0x000003fc 156b72e7464SBorislav Petkov #define MSR_CORE_C6_RESIDENCY 0x000003fd 157b72e7464SBorislav Petkov #define MSR_CORE_C7_RESIDENCY 0x000003fe 158b72e7464SBorislav Petkov #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 159b72e7464SBorislav Petkov #define MSR_PKG_C2_RESIDENCY 0x0000060d 160b72e7464SBorislav Petkov #define MSR_PKG_C8_RESIDENCY 0x00000630 161b72e7464SBorislav Petkov #define MSR_PKG_C9_RESIDENCY 0x00000631 162b72e7464SBorislav Petkov #define MSR_PKG_C10_RESIDENCY 0x00000632 163b72e7464SBorislav Petkov 164b72e7464SBorislav Petkov /* Run Time Average Power Limiting (RAPL) Interface */ 165b72e7464SBorislav Petkov 166b72e7464SBorislav Petkov #define MSR_RAPL_POWER_UNIT 0x00000606 167b72e7464SBorislav Petkov 168b72e7464SBorislav Petkov #define MSR_PKG_POWER_LIMIT 0x00000610 169b72e7464SBorislav Petkov #define MSR_PKG_ENERGY_STATUS 0x00000611 170b72e7464SBorislav Petkov #define MSR_PKG_PERF_STATUS 0x00000613 171b72e7464SBorislav Petkov #define MSR_PKG_POWER_INFO 0x00000614 172b72e7464SBorislav Petkov 173b72e7464SBorislav Petkov #define MSR_DRAM_POWER_LIMIT 0x00000618 174b72e7464SBorislav Petkov #define MSR_DRAM_ENERGY_STATUS 0x00000619 175b72e7464SBorislav Petkov #define MSR_DRAM_PERF_STATUS 0x0000061b 176b72e7464SBorislav Petkov #define MSR_DRAM_POWER_INFO 0x0000061c 177b72e7464SBorislav Petkov 178b72e7464SBorislav Petkov #define MSR_PP0_POWER_LIMIT 0x00000638 179b72e7464SBorislav Petkov #define MSR_PP0_ENERGY_STATUS 0x00000639 180b72e7464SBorislav Petkov #define MSR_PP0_POLICY 0x0000063a 181b72e7464SBorislav Petkov #define MSR_PP0_PERF_STATUS 0x0000063b 182b72e7464SBorislav Petkov 183b72e7464SBorislav Petkov #define MSR_PP1_POWER_LIMIT 0x00000640 184b72e7464SBorislav Petkov #define MSR_PP1_ENERGY_STATUS 0x00000641 185b72e7464SBorislav Petkov #define MSR_PP1_POLICY 0x00000642 186b72e7464SBorislav Petkov 18782bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_NOMINAL 0x00000648 18882bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 18982bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 19082bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_CONTROL 0x0000064B 19182bb70c5SRafael J. Wysocki #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 19282bb70c5SRafael J. Wysocki 193b72e7464SBorislav Petkov #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 194b72e7464SBorislav Petkov #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 195b72e7464SBorislav Petkov #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 196b72e7464SBorislav Petkov #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 197b72e7464SBorislav Petkov 198b72e7464SBorislav Petkov #define MSR_CORE_C1_RES 0x00000660 199b72e7464SBorislav Petkov 200b72e7464SBorislav Petkov #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 201b72e7464SBorislav Petkov #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 202b72e7464SBorislav Petkov 203b72e7464SBorislav Petkov #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 204b72e7464SBorislav Petkov #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 205b72e7464SBorislav Petkov #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 206b72e7464SBorislav Petkov 207b72e7464SBorislav Petkov /* Hardware P state interface */ 208b72e7464SBorislav Petkov #define MSR_PPERF 0x0000064e 209b72e7464SBorislav Petkov #define MSR_PERF_LIMIT_REASONS 0x0000064f 210b72e7464SBorislav Petkov #define MSR_PM_ENABLE 0x00000770 211b72e7464SBorislav Petkov #define MSR_HWP_CAPABILITIES 0x00000771 212b72e7464SBorislav Petkov #define MSR_HWP_REQUEST_PKG 0x00000772 213b72e7464SBorislav Petkov #define MSR_HWP_INTERRUPT 0x00000773 214b72e7464SBorislav Petkov #define MSR_HWP_REQUEST 0x00000774 215b72e7464SBorislav Petkov #define MSR_HWP_STATUS 0x00000777 216b72e7464SBorislav Petkov 217b72e7464SBorislav Petkov /* CPUID.6.EAX */ 218b72e7464SBorislav Petkov #define HWP_BASE_BIT (1<<7) 219b72e7464SBorislav Petkov #define HWP_NOTIFICATIONS_BIT (1<<8) 220b72e7464SBorislav Petkov #define HWP_ACTIVITY_WINDOW_BIT (1<<9) 221b72e7464SBorislav Petkov #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 222b72e7464SBorislav Petkov #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 223b72e7464SBorislav Petkov 224b72e7464SBorislav Petkov /* IA32_HWP_CAPABILITIES */ 225b72e7464SBorislav Petkov #define HWP_HIGHEST_PERF(x) (x & 0xff) 226b72e7464SBorislav Petkov #define HWP_GUARANTEED_PERF(x) ((x & (0xff << 8)) >>8) 227b72e7464SBorislav Petkov #define HWP_MOSTEFFICIENT_PERF(x) ((x & (0xff << 16)) >>16) 228b72e7464SBorislav Petkov #define HWP_LOWEST_PERF(x) ((x & (0xff << 24)) >>24) 229b72e7464SBorislav Petkov 230b72e7464SBorislav Petkov /* IA32_HWP_REQUEST */ 231b72e7464SBorislav Petkov #define HWP_MIN_PERF(x) (x & 0xff) 232b72e7464SBorislav Petkov #define HWP_MAX_PERF(x) ((x & 0xff) << 8) 233b72e7464SBorislav Petkov #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 234b72e7464SBorislav Petkov #define HWP_ENERGY_PERF_PREFERENCE(x) ((x & 0xff) << 24) 235b72e7464SBorislav Petkov #define HWP_ACTIVITY_WINDOW(x) ((x & 0xff3) << 32) 236b72e7464SBorislav Petkov #define HWP_PACKAGE_CONTROL(x) ((x & 0x1) << 42) 237b72e7464SBorislav Petkov 238b72e7464SBorislav Petkov /* IA32_HWP_STATUS */ 239b72e7464SBorislav Petkov #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 240b72e7464SBorislav Petkov #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 241b72e7464SBorislav Petkov 242b72e7464SBorislav Petkov /* IA32_HWP_INTERRUPT */ 243b72e7464SBorislav Petkov #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 244b72e7464SBorislav Petkov #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 245b72e7464SBorislav Petkov 246b72e7464SBorislav Petkov #define MSR_AMD64_MC0_MASK 0xc0010044 247b72e7464SBorislav Petkov 248b72e7464SBorislav Petkov #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 249b72e7464SBorislav Petkov #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 250b72e7464SBorislav Petkov #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 251b72e7464SBorislav Petkov #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 252b72e7464SBorislav Petkov 253b72e7464SBorislav Petkov #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 254b72e7464SBorislav Petkov 255b72e7464SBorislav Petkov /* These are consecutive and not in the normal 4er MCE bank block */ 256b72e7464SBorislav Petkov #define MSR_IA32_MC0_CTL2 0x00000280 257b72e7464SBorislav Petkov #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 258b72e7464SBorislav Petkov 259b72e7464SBorislav Petkov #define MSR_P6_PERFCTR0 0x000000c1 260b72e7464SBorislav Petkov #define MSR_P6_PERFCTR1 0x000000c2 261b72e7464SBorislav Petkov #define MSR_P6_EVNTSEL0 0x00000186 262b72e7464SBorislav Petkov #define MSR_P6_EVNTSEL1 0x00000187 263b72e7464SBorislav Petkov 264b72e7464SBorislav Petkov #define MSR_KNC_PERFCTR0 0x00000020 265b72e7464SBorislav Petkov #define MSR_KNC_PERFCTR1 0x00000021 266b72e7464SBorislav Petkov #define MSR_KNC_EVNTSEL0 0x00000028 267b72e7464SBorislav Petkov #define MSR_KNC_EVNTSEL1 0x00000029 268b72e7464SBorislav Petkov 269b72e7464SBorislav Petkov /* Alternative perfctr range with full access. */ 270b72e7464SBorislav Petkov #define MSR_IA32_PMC0 0x000004c1 271b72e7464SBorislav Petkov 272b72e7464SBorislav Petkov /* AMD64 MSRs. Not complete. See the architecture manual for a more 273b72e7464SBorislav Petkov complete list. */ 274b72e7464SBorislav Petkov 275b72e7464SBorislav Petkov #define MSR_AMD64_PATCH_LEVEL 0x0000008b 276b72e7464SBorislav Petkov #define MSR_AMD64_TSC_RATIO 0xc0000104 277b72e7464SBorislav Petkov #define MSR_AMD64_NB_CFG 0xc001001f 278b72e7464SBorislav Petkov #define MSR_AMD64_PATCH_LOADER 0xc0010020 279b72e7464SBorislav Petkov #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 280b72e7464SBorislav Petkov #define MSR_AMD64_OSVW_STATUS 0xc0010141 281b72e7464SBorislav Petkov #define MSR_AMD64_LS_CFG 0xc0011020 282b72e7464SBorislav Petkov #define MSR_AMD64_DC_CFG 0xc0011022 283b72e7464SBorislav Petkov #define MSR_AMD64_BU_CFG2 0xc001102a 284b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCHCTL 0xc0011030 285b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 286b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 287b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCH_REG_COUNT 3 288b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 289b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPCTL 0xc0011033 290b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPRIP 0xc0011034 291b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA 0xc0011035 292b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA2 0xc0011036 293b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA3 0xc0011037 294b72e7464SBorislav Petkov #define MSR_AMD64_IBSDCLINAD 0xc0011038 295b72e7464SBorislav Petkov #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 296b72e7464SBorislav Petkov #define MSR_AMD64_IBSOP_REG_COUNT 7 297b72e7464SBorislav Petkov #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 298b72e7464SBorislav Petkov #define MSR_AMD64_IBSCTL 0xc001103a 299b72e7464SBorislav Petkov #define MSR_AMD64_IBSBRTARGET 0xc001103b 300b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA4 0xc001103d 301b72e7464SBorislav Petkov #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 302b72e7464SBorislav Petkov 303b72e7464SBorislav Petkov /* Fam 16h MSRs */ 304b72e7464SBorislav Petkov #define MSR_F16H_L2I_PERF_CTL 0xc0010230 305b72e7464SBorislav Petkov #define MSR_F16H_L2I_PERF_CTR 0xc0010231 306b72e7464SBorislav Petkov #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 307b72e7464SBorislav Petkov #define MSR_F16H_DR2_ADDR_MASK 0xc001101a 308b72e7464SBorislav Petkov #define MSR_F16H_DR3_ADDR_MASK 0xc001101b 309b72e7464SBorislav Petkov #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 310b72e7464SBorislav Petkov 311b72e7464SBorislav Petkov /* Fam 15h MSRs */ 312b72e7464SBorislav Petkov #define MSR_F15H_PERF_CTL 0xc0010200 313b72e7464SBorislav Petkov #define MSR_F15H_PERF_CTR 0xc0010201 314b72e7464SBorislav Petkov #define MSR_F15H_NB_PERF_CTL 0xc0010240 315b72e7464SBorislav Petkov #define MSR_F15H_NB_PERF_CTR 0xc0010241 316b72e7464SBorislav Petkov 317b72e7464SBorislav Petkov /* Fam 10h MSRs */ 318b72e7464SBorislav Petkov #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 319b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_ENABLE (1<<0) 320b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 321b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 322b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 323b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BASE_SHIFT 20 324b72e7464SBorislav Petkov #define MSR_FAM10H_NODE_ID 0xc001100c 325b72e7464SBorislav Petkov 326b72e7464SBorislav Petkov /* K8 MSRs */ 327b72e7464SBorislav Petkov #define MSR_K8_TOP_MEM1 0xc001001a 328b72e7464SBorislav Petkov #define MSR_K8_TOP_MEM2 0xc001001d 329b72e7464SBorislav Petkov #define MSR_K8_SYSCFG 0xc0010010 330b72e7464SBorislav Petkov #define MSR_K8_INT_PENDING_MSG 0xc0010055 331b72e7464SBorislav Petkov /* C1E active bits in int pending message */ 332b72e7464SBorislav Petkov #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 333b72e7464SBorislav Petkov #define MSR_K8_TSEG_ADDR 0xc0010112 3343afb1121SPaolo Bonzini #define MSR_K8_TSEG_MASK 0xc0010113 335b72e7464SBorislav Petkov #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 336b72e7464SBorislav Petkov #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 337b72e7464SBorislav Petkov #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 338b72e7464SBorislav Petkov 339b72e7464SBorislav Petkov /* K7 MSRs */ 340b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL0 0xc0010000 341b72e7464SBorislav Petkov #define MSR_K7_PERFCTR0 0xc0010004 342b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL1 0xc0010001 343b72e7464SBorislav Petkov #define MSR_K7_PERFCTR1 0xc0010005 344b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL2 0xc0010002 345b72e7464SBorislav Petkov #define MSR_K7_PERFCTR2 0xc0010006 346b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL3 0xc0010003 347b72e7464SBorislav Petkov #define MSR_K7_PERFCTR3 0xc0010007 348b72e7464SBorislav Petkov #define MSR_K7_CLK_CTL 0xc001001b 349b72e7464SBorislav Petkov #define MSR_K7_HWCR 0xc0010015 350b72e7464SBorislav Petkov #define MSR_K7_FID_VID_CTL 0xc0010041 351b72e7464SBorislav Petkov #define MSR_K7_FID_VID_STATUS 0xc0010042 352b72e7464SBorislav Petkov 353b72e7464SBorislav Petkov /* K6 MSRs */ 354b72e7464SBorislav Petkov #define MSR_K6_WHCR 0xc0000082 355b72e7464SBorislav Petkov #define MSR_K6_UWCCR 0xc0000085 356b72e7464SBorislav Petkov #define MSR_K6_EPMR 0xc0000086 357b72e7464SBorislav Petkov #define MSR_K6_PSOR 0xc0000087 358b72e7464SBorislav Petkov #define MSR_K6_PFIR 0xc0000088 359b72e7464SBorislav Petkov 360b72e7464SBorislav Petkov /* Centaur-Hauls/IDT defined MSRs. */ 361b72e7464SBorislav Petkov #define MSR_IDT_FCR1 0x00000107 362b72e7464SBorislav Petkov #define MSR_IDT_FCR2 0x00000108 363b72e7464SBorislav Petkov #define MSR_IDT_FCR3 0x00000109 364b72e7464SBorislav Petkov #define MSR_IDT_FCR4 0x0000010a 365b72e7464SBorislav Petkov 366b72e7464SBorislav Petkov #define MSR_IDT_MCR0 0x00000110 367b72e7464SBorislav Petkov #define MSR_IDT_MCR1 0x00000111 368b72e7464SBorislav Petkov #define MSR_IDT_MCR2 0x00000112 369b72e7464SBorislav Petkov #define MSR_IDT_MCR3 0x00000113 370b72e7464SBorislav Petkov #define MSR_IDT_MCR4 0x00000114 371b72e7464SBorislav Petkov #define MSR_IDT_MCR5 0x00000115 372b72e7464SBorislav Petkov #define MSR_IDT_MCR6 0x00000116 373b72e7464SBorislav Petkov #define MSR_IDT_MCR7 0x00000117 374b72e7464SBorislav Petkov #define MSR_IDT_MCR_CTRL 0x00000120 375b72e7464SBorislav Petkov 376b72e7464SBorislav Petkov /* VIA Cyrix defined MSRs*/ 377b72e7464SBorislav Petkov #define MSR_VIA_FCR 0x00001107 378b72e7464SBorislav Petkov #define MSR_VIA_LONGHAUL 0x0000110a 379b72e7464SBorislav Petkov #define MSR_VIA_RNG 0x0000110b 380b72e7464SBorislav Petkov #define MSR_VIA_BCR2 0x00001147 381b72e7464SBorislav Petkov 382b72e7464SBorislav Petkov /* Transmeta defined MSRs */ 383b72e7464SBorislav Petkov #define MSR_TMTA_LONGRUN_CTRL 0x80868010 384b72e7464SBorislav Petkov #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 385b72e7464SBorislav Petkov #define MSR_TMTA_LRTI_READOUT 0x80868018 386b72e7464SBorislav Petkov #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 387b72e7464SBorislav Petkov 388b72e7464SBorislav Petkov /* Intel defined MSRs. */ 389b72e7464SBorislav Petkov #define MSR_IA32_P5_MC_ADDR 0x00000000 390b72e7464SBorislav Petkov #define MSR_IA32_P5_MC_TYPE 0x00000001 391b72e7464SBorislav Petkov #define MSR_IA32_TSC 0x00000010 392b72e7464SBorislav Petkov #define MSR_IA32_PLATFORM_ID 0x00000017 393b72e7464SBorislav Petkov #define MSR_IA32_EBL_CR_POWERON 0x0000002a 394b72e7464SBorislav Petkov #define MSR_EBC_FREQUENCY_ID 0x0000002c 395b72e7464SBorislav Petkov #define MSR_SMI_COUNT 0x00000034 396b72e7464SBorislav Petkov #define MSR_IA32_FEATURE_CONTROL 0x0000003a 397b72e7464SBorislav Petkov #define MSR_IA32_TSC_ADJUST 0x0000003b 398b72e7464SBorislav Petkov #define MSR_IA32_BNDCFGS 0x00000d90 399b72e7464SBorislav Petkov 400b72e7464SBorislav Petkov #define MSR_IA32_XSS 0x00000da0 401b72e7464SBorislav Petkov 402b72e7464SBorislav Petkov #define FEATURE_CONTROL_LOCKED (1<<0) 403b72e7464SBorislav Petkov #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 404b72e7464SBorislav Petkov #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 405b72e7464SBorislav Petkov #define FEATURE_CONTROL_LMCE (1<<20) 406b72e7464SBorislav Petkov 407b72e7464SBorislav Petkov #define MSR_IA32_APICBASE 0x0000001b 408b72e7464SBorislav Petkov #define MSR_IA32_APICBASE_BSP (1<<8) 409b72e7464SBorislav Petkov #define MSR_IA32_APICBASE_ENABLE (1<<11) 410b72e7464SBorislav Petkov #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 411b72e7464SBorislav Petkov 412b72e7464SBorislav Petkov #define MSR_IA32_TSCDEADLINE 0x000006e0 413b72e7464SBorislav Petkov 414b72e7464SBorislav Petkov #define MSR_IA32_UCODE_WRITE 0x00000079 415b72e7464SBorislav Petkov #define MSR_IA32_UCODE_REV 0x0000008b 416b72e7464SBorislav Petkov 417b72e7464SBorislav Petkov #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 418b72e7464SBorislav Petkov #define MSR_IA32_SMBASE 0x0000009e 419b72e7464SBorislav Petkov 420b72e7464SBorislav Petkov #define MSR_IA32_PERF_STATUS 0x00000198 421b72e7464SBorislav Petkov #define MSR_IA32_PERF_CTL 0x00000199 422b72e7464SBorislav Petkov #define INTEL_PERF_CTL_MASK 0xffff 423b72e7464SBorislav Petkov #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 424b72e7464SBorislav Petkov #define MSR_AMD_PERF_STATUS 0xc0010063 425b72e7464SBorislav Petkov #define MSR_AMD_PERF_CTL 0xc0010062 426b72e7464SBorislav Petkov 427b72e7464SBorislav Petkov #define MSR_IA32_MPERF 0x000000e7 428b72e7464SBorislav Petkov #define MSR_IA32_APERF 0x000000e8 429b72e7464SBorislav Petkov 430b72e7464SBorislav Petkov #define MSR_IA32_THERM_CONTROL 0x0000019a 431b72e7464SBorislav Petkov #define MSR_IA32_THERM_INTERRUPT 0x0000019b 432b72e7464SBorislav Petkov 433b72e7464SBorislav Petkov #define THERM_INT_HIGH_ENABLE (1 << 0) 434b72e7464SBorislav Petkov #define THERM_INT_LOW_ENABLE (1 << 1) 435b72e7464SBorislav Petkov #define THERM_INT_PLN_ENABLE (1 << 24) 436b72e7464SBorislav Petkov 437b72e7464SBorislav Petkov #define MSR_IA32_THERM_STATUS 0x0000019c 438b72e7464SBorislav Petkov 439b72e7464SBorislav Petkov #define THERM_STATUS_PROCHOT (1 << 0) 440b72e7464SBorislav Petkov #define THERM_STATUS_POWER_LIMIT (1 << 10) 441b72e7464SBorislav Petkov 442b72e7464SBorislav Petkov #define MSR_THERM2_CTL 0x0000019d 443b72e7464SBorislav Petkov 444b72e7464SBorislav Petkov #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 445b72e7464SBorislav Petkov 446b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE 0x000001a0 447b72e7464SBorislav Petkov 448b72e7464SBorislav Petkov #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 449b72e7464SBorislav Petkov 450b72e7464SBorislav Petkov #define MSR_MISC_PWR_MGMT 0x000001aa 451b72e7464SBorislav Petkov 452b72e7464SBorislav Petkov #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 453b72e7464SBorislav Petkov #define ENERGY_PERF_BIAS_PERFORMANCE 0 454b72e7464SBorislav Petkov #define ENERGY_PERF_BIAS_NORMAL 6 455b72e7464SBorislav Petkov #define ENERGY_PERF_BIAS_POWERSAVE 15 456b72e7464SBorislav Petkov 457b72e7464SBorislav Petkov #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 458b72e7464SBorislav Petkov 459b72e7464SBorislav Petkov #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 460b72e7464SBorislav Petkov #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 461b72e7464SBorislav Petkov 462b72e7464SBorislav Petkov #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 463b72e7464SBorislav Petkov 464b72e7464SBorislav Petkov #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 465b72e7464SBorislav Petkov #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 466b72e7464SBorislav Petkov #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 467b72e7464SBorislav Petkov 468b72e7464SBorislav Petkov /* Thermal Thresholds Support */ 469b72e7464SBorislav Petkov #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 470b72e7464SBorislav Petkov #define THERM_SHIFT_THRESHOLD0 8 471b72e7464SBorislav Petkov #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 472b72e7464SBorislav Petkov #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 473b72e7464SBorislav Petkov #define THERM_SHIFT_THRESHOLD1 16 474b72e7464SBorislav Petkov #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 475b72e7464SBorislav Petkov #define THERM_STATUS_THRESHOLD0 (1 << 6) 476b72e7464SBorislav Petkov #define THERM_LOG_THRESHOLD0 (1 << 7) 477b72e7464SBorislav Petkov #define THERM_STATUS_THRESHOLD1 (1 << 8) 478b72e7464SBorislav Petkov #define THERM_LOG_THRESHOLD1 (1 << 9) 479b72e7464SBorislav Petkov 480b72e7464SBorislav Petkov /* MISC_ENABLE bits: architectural */ 481b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 482b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 483b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 484b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 485b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 486b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 487b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 488b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 489b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 490b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 491b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 492b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 493b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 494b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 495b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 496b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 497b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 498b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 499b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 500b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 501b72e7464SBorislav Petkov 502b72e7464SBorislav Petkov /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 503b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 504b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 505b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 506b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 507b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 508b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 509b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 510b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 511b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 512b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 513b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 514b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 515b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 516b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 517b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 518b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 519b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 520b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 521b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 522b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 523b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 524b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 525b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 526b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 527b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 528b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 529b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 530b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 531b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 532b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 533b72e7464SBorislav Petkov 534b72e7464SBorislav Petkov #define MSR_IA32_TSC_DEADLINE 0x000006E0 535b72e7464SBorislav Petkov 536b72e7464SBorislav Petkov /* P4/Xeon+ specific */ 537b72e7464SBorislav Petkov #define MSR_IA32_MCG_EAX 0x00000180 538b72e7464SBorislav Petkov #define MSR_IA32_MCG_EBX 0x00000181 539b72e7464SBorislav Petkov #define MSR_IA32_MCG_ECX 0x00000182 540b72e7464SBorislav Petkov #define MSR_IA32_MCG_EDX 0x00000183 541b72e7464SBorislav Petkov #define MSR_IA32_MCG_ESI 0x00000184 542b72e7464SBorislav Petkov #define MSR_IA32_MCG_EDI 0x00000185 543b72e7464SBorislav Petkov #define MSR_IA32_MCG_EBP 0x00000186 544b72e7464SBorislav Petkov #define MSR_IA32_MCG_ESP 0x00000187 545b72e7464SBorislav Petkov #define MSR_IA32_MCG_EFLAGS 0x00000188 546b72e7464SBorislav Petkov #define MSR_IA32_MCG_EIP 0x00000189 547b72e7464SBorislav Petkov #define MSR_IA32_MCG_RESERVED 0x0000018a 548b72e7464SBorislav Petkov 549b72e7464SBorislav Petkov /* Pentium IV performance counter MSRs */ 550b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR0 0x00000300 551b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR1 0x00000301 552b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR2 0x00000302 553b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR3 0x00000303 554b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR0 0x00000304 555b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR1 0x00000305 556b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR2 0x00000306 557b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR3 0x00000307 558b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR0 0x00000308 559b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR1 0x00000309 560b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR2 0x0000030a 561b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR3 0x0000030b 562b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR0 0x0000030c 563b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR1 0x0000030d 564b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR2 0x0000030e 565b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR3 0x0000030f 566b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR4 0x00000310 567b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR5 0x00000311 568b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR0 0x00000360 569b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR1 0x00000361 570b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR2 0x00000362 571b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR3 0x00000363 572b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR0 0x00000364 573b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR1 0x00000365 574b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR2 0x00000366 575b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR3 0x00000367 576b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR0 0x00000368 577b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR1 0x00000369 578b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR2 0x0000036a 579b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR3 0x0000036b 580b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR0 0x0000036c 581b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR1 0x0000036d 582b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR2 0x0000036e 583b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR3 0x0000036f 584b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR4 0x00000370 585b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR5 0x00000371 586b72e7464SBorislav Petkov #define MSR_P4_ALF_ESCR0 0x000003ca 587b72e7464SBorislav Petkov #define MSR_P4_ALF_ESCR1 0x000003cb 588b72e7464SBorislav Petkov #define MSR_P4_BPU_ESCR0 0x000003b2 589b72e7464SBorislav Petkov #define MSR_P4_BPU_ESCR1 0x000003b3 590b72e7464SBorislav Petkov #define MSR_P4_BSU_ESCR0 0x000003a0 591b72e7464SBorislav Petkov #define MSR_P4_BSU_ESCR1 0x000003a1 592b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR0 0x000003b8 593b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR1 0x000003b9 594b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR2 0x000003cc 595b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR3 0x000003cd 596b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR4 0x000003e0 597b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR5 0x000003e1 598b72e7464SBorislav Petkov #define MSR_P4_DAC_ESCR0 0x000003a8 599b72e7464SBorislav Petkov #define MSR_P4_DAC_ESCR1 0x000003a9 600b72e7464SBorislav Petkov #define MSR_P4_FIRM_ESCR0 0x000003a4 601b72e7464SBorislav Petkov #define MSR_P4_FIRM_ESCR1 0x000003a5 602b72e7464SBorislav Petkov #define MSR_P4_FLAME_ESCR0 0x000003a6 603b72e7464SBorislav Petkov #define MSR_P4_FLAME_ESCR1 0x000003a7 604b72e7464SBorislav Petkov #define MSR_P4_FSB_ESCR0 0x000003a2 605b72e7464SBorislav Petkov #define MSR_P4_FSB_ESCR1 0x000003a3 606b72e7464SBorislav Petkov #define MSR_P4_IQ_ESCR0 0x000003ba 607b72e7464SBorislav Petkov #define MSR_P4_IQ_ESCR1 0x000003bb 608b72e7464SBorislav Petkov #define MSR_P4_IS_ESCR0 0x000003b4 609b72e7464SBorislav Petkov #define MSR_P4_IS_ESCR1 0x000003b5 610b72e7464SBorislav Petkov #define MSR_P4_ITLB_ESCR0 0x000003b6 611b72e7464SBorislav Petkov #define MSR_P4_ITLB_ESCR1 0x000003b7 612b72e7464SBorislav Petkov #define MSR_P4_IX_ESCR0 0x000003c8 613b72e7464SBorislav Petkov #define MSR_P4_IX_ESCR1 0x000003c9 614b72e7464SBorislav Petkov #define MSR_P4_MOB_ESCR0 0x000003aa 615b72e7464SBorislav Petkov #define MSR_P4_MOB_ESCR1 0x000003ab 616b72e7464SBorislav Petkov #define MSR_P4_MS_ESCR0 0x000003c0 617b72e7464SBorislav Petkov #define MSR_P4_MS_ESCR1 0x000003c1 618b72e7464SBorislav Petkov #define MSR_P4_PMH_ESCR0 0x000003ac 619b72e7464SBorislav Petkov #define MSR_P4_PMH_ESCR1 0x000003ad 620b72e7464SBorislav Petkov #define MSR_P4_RAT_ESCR0 0x000003bc 621b72e7464SBorislav Petkov #define MSR_P4_RAT_ESCR1 0x000003bd 622b72e7464SBorislav Petkov #define MSR_P4_SAAT_ESCR0 0x000003ae 623b72e7464SBorislav Petkov #define MSR_P4_SAAT_ESCR1 0x000003af 624b72e7464SBorislav Petkov #define MSR_P4_SSU_ESCR0 0x000003be 625b72e7464SBorislav Petkov #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 626b72e7464SBorislav Petkov 627b72e7464SBorislav Petkov #define MSR_P4_TBPU_ESCR0 0x000003c2 628b72e7464SBorislav Petkov #define MSR_P4_TBPU_ESCR1 0x000003c3 629b72e7464SBorislav Petkov #define MSR_P4_TC_ESCR0 0x000003c4 630b72e7464SBorislav Petkov #define MSR_P4_TC_ESCR1 0x000003c5 631b72e7464SBorislav Petkov #define MSR_P4_U2L_ESCR0 0x000003b0 632b72e7464SBorislav Petkov #define MSR_P4_U2L_ESCR1 0x000003b1 633b72e7464SBorislav Petkov 634b72e7464SBorislav Petkov #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 635b72e7464SBorislav Petkov 636b72e7464SBorislav Petkov /* Intel Core-based CPU performance counters */ 637b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 638b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 639b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 640b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 641b72e7464SBorislav Petkov #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 642b72e7464SBorislav Petkov #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 643b72e7464SBorislav Petkov #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 644b72e7464SBorislav Petkov 645b72e7464SBorislav Petkov /* Geode defined MSRs */ 646b72e7464SBorislav Petkov #define MSR_GEODE_BUSCONT_CONF0 0x00001900 647b72e7464SBorislav Petkov 648b72e7464SBorislav Petkov /* Intel VT MSRs */ 649b72e7464SBorislav Petkov #define MSR_IA32_VMX_BASIC 0x00000480 650b72e7464SBorislav Petkov #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 651b72e7464SBorislav Petkov #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 652b72e7464SBorislav Petkov #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 653b72e7464SBorislav Petkov #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 654b72e7464SBorislav Petkov #define MSR_IA32_VMX_MISC 0x00000485 655b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 656b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 657b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 658b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 659b72e7464SBorislav Petkov #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 660b72e7464SBorislav Petkov #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 661b72e7464SBorislav Petkov #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 662b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 663b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 664b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 665b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 666b72e7464SBorislav Petkov #define MSR_IA32_VMX_VMFUNC 0x00000491 667b72e7464SBorislav Petkov 668b72e7464SBorislav Petkov /* VMX_BASIC bits and bitmasks */ 669b72e7464SBorislav Petkov #define VMX_BASIC_VMCS_SIZE_SHIFT 32 670b72e7464SBorislav Petkov #define VMX_BASIC_TRUE_CTLS (1ULL << 55) 671b72e7464SBorislav Petkov #define VMX_BASIC_64 0x0001000000000000LLU 672b72e7464SBorislav Petkov #define VMX_BASIC_MEM_TYPE_SHIFT 50 673b72e7464SBorislav Petkov #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 674b72e7464SBorislav Petkov #define VMX_BASIC_MEM_TYPE_WB 6LLU 675b72e7464SBorislav Petkov #define VMX_BASIC_INOUT 0x0040000000000000LLU 676b72e7464SBorislav Petkov 677b72e7464SBorislav Petkov /* MSR_IA32_VMX_MISC bits */ 678b72e7464SBorislav Petkov #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 679b72e7464SBorislav Petkov #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 680b72e7464SBorislav Petkov /* AMD-V MSRs */ 681b72e7464SBorislav Petkov 682b72e7464SBorislav Petkov #define MSR_VM_CR 0xc0010114 683b72e7464SBorislav Petkov #define MSR_VM_IGNNE 0xc0010115 684b72e7464SBorislav Petkov #define MSR_VM_HSAVE_PA 0xc0010117 685b72e7464SBorislav Petkov 686b72e7464SBorislav Petkov #endif /* _ASM_X86_MSR_INDEX_H */ 687