1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2b72e7464SBorislav Petkov #ifndef _ASM_X86_MSR_INDEX_H 3b72e7464SBorislav Petkov #define _ASM_X86_MSR_INDEX_H 4b72e7464SBorislav Petkov 5053080a9SBorislav Petkov /* 6053080a9SBorislav Petkov * CPU model specific register (MSR) numbers. 7053080a9SBorislav Petkov * 8053080a9SBorislav Petkov * Do not add new entries to this file unless the definitions are shared 9053080a9SBorislav Petkov * between multiple compilation units. 10053080a9SBorislav Petkov */ 11b72e7464SBorislav Petkov 12b72e7464SBorislav Petkov /* x86-64 specific MSRs */ 13b72e7464SBorislav Petkov #define MSR_EFER 0xc0000080 /* extended feature register */ 14b72e7464SBorislav Petkov #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 15b72e7464SBorislav Petkov #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 16b72e7464SBorislav Petkov #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 17b72e7464SBorislav Petkov #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 18b72e7464SBorislav Petkov #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 19b72e7464SBorislav Petkov #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 20b72e7464SBorislav Petkov #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 21b72e7464SBorislav Petkov #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 22b72e7464SBorislav Petkov 23b72e7464SBorislav Petkov /* EFER bits: */ 24b72e7464SBorislav Petkov #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 25b72e7464SBorislav Petkov #define _EFER_LME 8 /* Long mode enable */ 26b72e7464SBorislav Petkov #define _EFER_LMA 10 /* Long mode active (read-only) */ 27b72e7464SBorislav Petkov #define _EFER_NX 11 /* No execute enable */ 28b72e7464SBorislav Petkov #define _EFER_SVME 12 /* Enable virtualization */ 29b72e7464SBorislav Petkov #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 30b72e7464SBorislav Petkov #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 31b72e7464SBorislav Petkov 32b72e7464SBorislav Petkov #define EFER_SCE (1<<_EFER_SCE) 33b72e7464SBorislav Petkov #define EFER_LME (1<<_EFER_LME) 34b72e7464SBorislav Petkov #define EFER_LMA (1<<_EFER_LMA) 35b72e7464SBorislav Petkov #define EFER_NX (1<<_EFER_NX) 36b72e7464SBorislav Petkov #define EFER_SVME (1<<_EFER_SVME) 37b72e7464SBorislav Petkov #define EFER_LMSLE (1<<_EFER_LMSLE) 38b72e7464SBorislav Petkov #define EFER_FFXSR (1<<_EFER_FFXSR) 39b72e7464SBorislav Petkov 40b72e7464SBorislav Petkov /* Intel MSRs. Some also available on other CPUs */ 413f5a7896STony Luck 421e340c60SDavid Woodhouse #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 431e340c60SDavid Woodhouse #define SPEC_CTRL_IBRS (1 << 0) /* Indirect Branch Restricted Speculation */ 441e340c60SDavid Woodhouse #define SPEC_CTRL_STIBP (1 << 1) /* Single Thread Indirect Branch Predictors */ 459f65fb29SKonrad Rzeszutek Wilk #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ 469f65fb29SKonrad Rzeszutek Wilk #define SPEC_CTRL_SSBD (1 << SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ 471e340c60SDavid Woodhouse 481e340c60SDavid Woodhouse #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 491e340c60SDavid Woodhouse #define PRED_CMD_IBPB (1 << 0) /* Indirect Branch Prediction Barrier */ 501e340c60SDavid Woodhouse 513f5a7896STony Luck #define MSR_PPIN_CTL 0x0000004e 523f5a7896STony Luck #define MSR_PPIN 0x0000004f 533f5a7896STony Luck 54b72e7464SBorislav Petkov #define MSR_IA32_PERFCTR0 0x000000c1 55b72e7464SBorislav Petkov #define MSR_IA32_PERFCTR1 0x000000c2 56b72e7464SBorislav Petkov #define MSR_FSB_FREQ 0x000000cd 575369a21eSLen Brown #define MSR_PLATFORM_INFO 0x000000ce 5890218ac7SKyle Huey #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 5990218ac7SKyle Huey #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) 60b72e7464SBorislav Petkov 6140496c8eSLen Brown #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 62b72e7464SBorislav Petkov #define NHM_C3_AUTO_DEMOTE (1UL << 25) 63b72e7464SBorislav Petkov #define NHM_C1_AUTO_DEMOTE (1UL << 26) 64b72e7464SBorislav Petkov #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 65b72e7464SBorislav Petkov #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 66b72e7464SBorislav Petkov #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 67b72e7464SBorislav Petkov 68b72e7464SBorislav Petkov #define MSR_MTRRcap 0x000000fe 691e340c60SDavid Woodhouse 701e340c60SDavid Woodhouse #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 711e340c60SDavid Woodhouse #define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to Meltdown */ 721e340c60SDavid Woodhouse #define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */ 73240da953SKonrad Rzeszutek Wilk #define ARCH_CAP_SSB_NO (1 << 4) /* 7477243971SKonrad Rzeszutek Wilk * Not susceptible to Speculative Store Bypass 759f65fb29SKonrad Rzeszutek Wilk * attack, so no Speculative Store Bypass 769f65fb29SKonrad Rzeszutek Wilk * control required. 7777243971SKonrad Rzeszutek Wilk */ 781e340c60SDavid Woodhouse 79b72e7464SBorislav Petkov #define MSR_IA32_BBL_CR_CTL 0x00000119 80b72e7464SBorislav Petkov #define MSR_IA32_BBL_CR_CTL3 0x0000011e 81b72e7464SBorislav Petkov 82b72e7464SBorislav Petkov #define MSR_IA32_SYSENTER_CS 0x00000174 83b72e7464SBorislav Petkov #define MSR_IA32_SYSENTER_ESP 0x00000175 84b72e7464SBorislav Petkov #define MSR_IA32_SYSENTER_EIP 0x00000176 85b72e7464SBorislav Petkov 86b72e7464SBorislav Petkov #define MSR_IA32_MCG_CAP 0x00000179 87b72e7464SBorislav Petkov #define MSR_IA32_MCG_STATUS 0x0000017a 88b72e7464SBorislav Petkov #define MSR_IA32_MCG_CTL 0x0000017b 89b72e7464SBorislav Petkov #define MSR_IA32_MCG_EXT_CTL 0x000004d0 90b72e7464SBorislav Petkov 91b72e7464SBorislav Petkov #define MSR_OFFCORE_RSP_0 0x000001a6 92b72e7464SBorislav Petkov #define MSR_OFFCORE_RSP_1 0x000001a7 93b72e7464SBorislav Petkov #define MSR_TURBO_RATIO_LIMIT 0x000001ad 94b72e7464SBorislav Petkov #define MSR_TURBO_RATIO_LIMIT1 0x000001ae 95b72e7464SBorislav Petkov #define MSR_TURBO_RATIO_LIMIT2 0x000001af 96b72e7464SBorislav Petkov 97b72e7464SBorislav Petkov #define MSR_LBR_SELECT 0x000001c8 98b72e7464SBorislav Petkov #define MSR_LBR_TOS 0x000001c9 99b72e7464SBorislav Petkov #define MSR_LBR_NHM_FROM 0x00000680 100b72e7464SBorislav Petkov #define MSR_LBR_NHM_TO 0x000006c0 101b72e7464SBorislav Petkov #define MSR_LBR_CORE_FROM 0x00000040 102b72e7464SBorislav Petkov #define MSR_LBR_CORE_TO 0x00000060 103b72e7464SBorislav Petkov 104b83ff1c8SAndi Kleen #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 105b83ff1c8SAndi Kleen #define LBR_INFO_MISPRED BIT_ULL(63) 106b83ff1c8SAndi Kleen #define LBR_INFO_IN_TX BIT_ULL(62) 107b83ff1c8SAndi Kleen #define LBR_INFO_ABORT BIT_ULL(61) 108b83ff1c8SAndi Kleen #define LBR_INFO_CYCLES 0xffff 109b83ff1c8SAndi Kleen 110b72e7464SBorislav Petkov #define MSR_IA32_PEBS_ENABLE 0x000003f1 111b72e7464SBorislav Petkov #define MSR_IA32_DS_AREA 0x00000600 112b72e7464SBorislav Petkov #define MSR_IA32_PERF_CAPABILITIES 0x00000345 113b72e7464SBorislav Petkov #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 114b72e7464SBorislav Petkov 115b72e7464SBorislav Petkov #define MSR_IA32_RTIT_CTL 0x00000570 116b72e7464SBorislav Petkov #define MSR_IA32_RTIT_STATUS 0x00000571 117f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR0_A 0x00000580 118f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR0_B 0x00000581 119f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR1_A 0x00000582 120f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR1_B 0x00000583 121f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR2_A 0x00000584 122f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR2_B 0x00000585 123f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR3_A 0x00000586 124f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR3_B 0x00000587 125b72e7464SBorislav Petkov #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 126b72e7464SBorislav Petkov #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 127b72e7464SBorislav Petkov #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 128b72e7464SBorislav Petkov 129b72e7464SBorislav Petkov #define MSR_MTRRfix64K_00000 0x00000250 130b72e7464SBorislav Petkov #define MSR_MTRRfix16K_80000 0x00000258 131b72e7464SBorislav Petkov #define MSR_MTRRfix16K_A0000 0x00000259 132b72e7464SBorislav Petkov #define MSR_MTRRfix4K_C0000 0x00000268 133b72e7464SBorislav Petkov #define MSR_MTRRfix4K_C8000 0x00000269 134b72e7464SBorislav Petkov #define MSR_MTRRfix4K_D0000 0x0000026a 135b72e7464SBorislav Petkov #define MSR_MTRRfix4K_D8000 0x0000026b 136b72e7464SBorislav Petkov #define MSR_MTRRfix4K_E0000 0x0000026c 137b72e7464SBorislav Petkov #define MSR_MTRRfix4K_E8000 0x0000026d 138b72e7464SBorislav Petkov #define MSR_MTRRfix4K_F0000 0x0000026e 139b72e7464SBorislav Petkov #define MSR_MTRRfix4K_F8000 0x0000026f 140b72e7464SBorislav Petkov #define MSR_MTRRdefType 0x000002ff 141b72e7464SBorislav Petkov 142b72e7464SBorislav Petkov #define MSR_IA32_CR_PAT 0x00000277 143b72e7464SBorislav Petkov 144b72e7464SBorislav Petkov #define MSR_IA32_DEBUGCTLMSR 0x000001d9 145b72e7464SBorislav Petkov #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 146b72e7464SBorislav Petkov #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 147b72e7464SBorislav Petkov #define MSR_IA32_LASTINTFROMIP 0x000001dd 148b72e7464SBorislav Petkov #define MSR_IA32_LASTINTTOIP 0x000001de 149b72e7464SBorislav Petkov 150b72e7464SBorislav Petkov /* DEBUGCTLMSR bits (others vary by model): */ 151b72e7464SBorislav Petkov #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 152b9894a2fSKyle Huey #define DEBUGCTLMSR_BTF_SHIFT 1 153b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 154b72e7464SBorislav Petkov #define DEBUGCTLMSR_TR (1UL << 6) 155b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTS (1UL << 7) 156b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTINT (1UL << 8) 157b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 158b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 159b72e7464SBorislav Petkov #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 1606089327fSKan Liang #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 1616089327fSKan Liang #define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 162b72e7464SBorislav Petkov 163d0dc8494SAndi Kleen #define MSR_PEBS_FRONTEND 0x000003f7 164d0dc8494SAndi Kleen 165b72e7464SBorislav Petkov #define MSR_IA32_POWER_CTL 0x000001fc 166b72e7464SBorislav Petkov 167b72e7464SBorislav Petkov #define MSR_IA32_MC0_CTL 0x00000400 168b72e7464SBorislav Petkov #define MSR_IA32_MC0_STATUS 0x00000401 169b72e7464SBorislav Petkov #define MSR_IA32_MC0_ADDR 0x00000402 170b72e7464SBorislav Petkov #define MSR_IA32_MC0_MISC 0x00000403 171b72e7464SBorislav Petkov 172b72e7464SBorislav Petkov /* C-state Residency Counters */ 173b72e7464SBorislav Petkov #define MSR_PKG_C3_RESIDENCY 0x000003f8 174b72e7464SBorislav Petkov #define MSR_PKG_C6_RESIDENCY 0x000003f9 1750539ba11SLen Brown #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 176b72e7464SBorislav Petkov #define MSR_PKG_C7_RESIDENCY 0x000003fa 177b72e7464SBorislav Petkov #define MSR_CORE_C3_RESIDENCY 0x000003fc 178b72e7464SBorislav Petkov #define MSR_CORE_C6_RESIDENCY 0x000003fd 179b72e7464SBorislav Petkov #define MSR_CORE_C7_RESIDENCY 0x000003fe 180b72e7464SBorislav Petkov #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 181b72e7464SBorislav Petkov #define MSR_PKG_C2_RESIDENCY 0x0000060d 182b72e7464SBorislav Petkov #define MSR_PKG_C8_RESIDENCY 0x00000630 183b72e7464SBorislav Petkov #define MSR_PKG_C9_RESIDENCY 0x00000631 184b72e7464SBorislav Petkov #define MSR_PKG_C10_RESIDENCY 0x00000632 185b72e7464SBorislav Petkov 1865a63426eSLen Brown /* Interrupt Response Limit */ 1875a63426eSLen Brown #define MSR_PKGC3_IRTL 0x0000060a 1885a63426eSLen Brown #define MSR_PKGC6_IRTL 0x0000060b 1895a63426eSLen Brown #define MSR_PKGC7_IRTL 0x0000060c 1905a63426eSLen Brown #define MSR_PKGC8_IRTL 0x00000633 1915a63426eSLen Brown #define MSR_PKGC9_IRTL 0x00000634 1925a63426eSLen Brown #define MSR_PKGC10_IRTL 0x00000635 1935a63426eSLen Brown 194b72e7464SBorislav Petkov /* Run Time Average Power Limiting (RAPL) Interface */ 195b72e7464SBorislav Petkov 196b72e7464SBorislav Petkov #define MSR_RAPL_POWER_UNIT 0x00000606 197b72e7464SBorislav Petkov 198b72e7464SBorislav Petkov #define MSR_PKG_POWER_LIMIT 0x00000610 199b72e7464SBorislav Petkov #define MSR_PKG_ENERGY_STATUS 0x00000611 200b72e7464SBorislav Petkov #define MSR_PKG_PERF_STATUS 0x00000613 201b72e7464SBorislav Petkov #define MSR_PKG_POWER_INFO 0x00000614 202b72e7464SBorislav Petkov 203b72e7464SBorislav Petkov #define MSR_DRAM_POWER_LIMIT 0x00000618 204b72e7464SBorislav Petkov #define MSR_DRAM_ENERGY_STATUS 0x00000619 205b72e7464SBorislav Petkov #define MSR_DRAM_PERF_STATUS 0x0000061b 206b72e7464SBorislav Petkov #define MSR_DRAM_POWER_INFO 0x0000061c 207b72e7464SBorislav Petkov 208b72e7464SBorislav Petkov #define MSR_PP0_POWER_LIMIT 0x00000638 209b72e7464SBorislav Petkov #define MSR_PP0_ENERGY_STATUS 0x00000639 210b72e7464SBorislav Petkov #define MSR_PP0_POLICY 0x0000063a 211b72e7464SBorislav Petkov #define MSR_PP0_PERF_STATUS 0x0000063b 212b72e7464SBorislav Petkov 213b72e7464SBorislav Petkov #define MSR_PP1_POWER_LIMIT 0x00000640 214b72e7464SBorislav Petkov #define MSR_PP1_ENERGY_STATUS 0x00000641 215b72e7464SBorislav Petkov #define MSR_PP1_POLICY 0x00000642 216b72e7464SBorislav Petkov 2174a6772f5SVladimir Zapolskiy /* Config TDP MSRs */ 21882bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_NOMINAL 0x00000648 21982bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 22082bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 22182bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_CONTROL 0x0000064B 22282bb70c5SRafael J. Wysocki #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 22382bb70c5SRafael J. Wysocki 224dcee75b3SSrinivas Pandruvada #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 225dcee75b3SSrinivas Pandruvada 226b72e7464SBorislav Petkov #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 227b72e7464SBorislav Petkov #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 228b72e7464SBorislav Petkov #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 229b72e7464SBorislav Petkov #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 230b72e7464SBorislav Petkov 231b72e7464SBorislav Petkov #define MSR_CORE_C1_RES 0x00000660 2320539ba11SLen Brown #define MSR_MODULE_C6_RES_MS 0x00000664 233b72e7464SBorislav Petkov 234b72e7464SBorislav Petkov #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 235b72e7464SBorislav Petkov #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 236b72e7464SBorislav Petkov 2378a34fd02SLen Brown #define MSR_ATOM_CORE_RATIOS 0x0000066a 2388a34fd02SLen Brown #define MSR_ATOM_CORE_VIDS 0x0000066b 2398a34fd02SLen Brown #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 2408a34fd02SLen Brown #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 2418a34fd02SLen Brown 2428a34fd02SLen Brown 243b72e7464SBorislav Petkov #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 244b72e7464SBorislav Petkov #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 245b72e7464SBorislav Petkov #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 246b72e7464SBorislav Petkov 247b72e7464SBorislav Petkov /* Hardware P state interface */ 248b72e7464SBorislav Petkov #define MSR_PPERF 0x0000064e 249b72e7464SBorislav Petkov #define MSR_PERF_LIMIT_REASONS 0x0000064f 250b72e7464SBorislav Petkov #define MSR_PM_ENABLE 0x00000770 251b72e7464SBorislav Petkov #define MSR_HWP_CAPABILITIES 0x00000771 252b72e7464SBorislav Petkov #define MSR_HWP_REQUEST_PKG 0x00000772 253b72e7464SBorislav Petkov #define MSR_HWP_INTERRUPT 0x00000773 254b72e7464SBorislav Petkov #define MSR_HWP_REQUEST 0x00000774 255b72e7464SBorislav Petkov #define MSR_HWP_STATUS 0x00000777 256b72e7464SBorislav Petkov 257b72e7464SBorislav Petkov /* CPUID.6.EAX */ 258b72e7464SBorislav Petkov #define HWP_BASE_BIT (1<<7) 259b72e7464SBorislav Petkov #define HWP_NOTIFICATIONS_BIT (1<<8) 260b72e7464SBorislav Petkov #define HWP_ACTIVITY_WINDOW_BIT (1<<9) 261b72e7464SBorislav Petkov #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 262b72e7464SBorislav Petkov #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 263b72e7464SBorislav Petkov 264b72e7464SBorislav Petkov /* IA32_HWP_CAPABILITIES */ 265670e27d8SLen Brown #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 266670e27d8SLen Brown #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 267670e27d8SLen Brown #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 268670e27d8SLen Brown #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 269b72e7464SBorislav Petkov 270b72e7464SBorislav Petkov /* IA32_HWP_REQUEST */ 271b72e7464SBorislav Petkov #define HWP_MIN_PERF(x) (x & 0xff) 272b72e7464SBorislav Petkov #define HWP_MAX_PERF(x) ((x & 0xff) << 8) 273b72e7464SBorislav Petkov #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 2742fc49cb0SLen Brown #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) 2758d84e906SLen Brown #define HWP_EPP_PERFORMANCE 0x00 2768d84e906SLen Brown #define HWP_EPP_BALANCE_PERFORMANCE 0x80 2778d84e906SLen Brown #define HWP_EPP_BALANCE_POWERSAVE 0xC0 2788d84e906SLen Brown #define HWP_EPP_POWERSAVE 0xFF 2792fc49cb0SLen Brown #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) 2802fc49cb0SLen Brown #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) 281b72e7464SBorislav Petkov 282b72e7464SBorislav Petkov /* IA32_HWP_STATUS */ 283b72e7464SBorislav Petkov #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 284b72e7464SBorislav Petkov #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 285b72e7464SBorislav Petkov 286b72e7464SBorislav Petkov /* IA32_HWP_INTERRUPT */ 287b72e7464SBorislav Petkov #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 288b72e7464SBorislav Petkov #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 289b72e7464SBorislav Petkov 290b72e7464SBorislav Petkov #define MSR_AMD64_MC0_MASK 0xc0010044 291b72e7464SBorislav Petkov 292b72e7464SBorislav Petkov #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 293b72e7464SBorislav Petkov #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 294b72e7464SBorislav Petkov #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 295b72e7464SBorislav Petkov #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 296b72e7464SBorislav Petkov 297b72e7464SBorislav Petkov #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 298b72e7464SBorislav Petkov 299b72e7464SBorislav Petkov /* These are consecutive and not in the normal 4er MCE bank block */ 300b72e7464SBorislav Petkov #define MSR_IA32_MC0_CTL2 0x00000280 301b72e7464SBorislav Petkov #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 302b72e7464SBorislav Petkov 303b72e7464SBorislav Petkov #define MSR_P6_PERFCTR0 0x000000c1 304b72e7464SBorislav Petkov #define MSR_P6_PERFCTR1 0x000000c2 305b72e7464SBorislav Petkov #define MSR_P6_EVNTSEL0 0x00000186 306b72e7464SBorislav Petkov #define MSR_P6_EVNTSEL1 0x00000187 307b72e7464SBorislav Petkov 308b72e7464SBorislav Petkov #define MSR_KNC_PERFCTR0 0x00000020 309b72e7464SBorislav Petkov #define MSR_KNC_PERFCTR1 0x00000021 310b72e7464SBorislav Petkov #define MSR_KNC_EVNTSEL0 0x00000028 311b72e7464SBorislav Petkov #define MSR_KNC_EVNTSEL1 0x00000029 312b72e7464SBorislav Petkov 313b72e7464SBorislav Petkov /* Alternative perfctr range with full access. */ 314b72e7464SBorislav Petkov #define MSR_IA32_PMC0 0x000004c1 315b72e7464SBorislav Petkov 316b72e7464SBorislav Petkov /* AMD64 MSRs. Not complete. See the architecture manual for a more 317b72e7464SBorislav Petkov complete list. */ 318b72e7464SBorislav Petkov 319b72e7464SBorislav Petkov #define MSR_AMD64_PATCH_LEVEL 0x0000008b 320b72e7464SBorislav Petkov #define MSR_AMD64_TSC_RATIO 0xc0000104 321b72e7464SBorislav Petkov #define MSR_AMD64_NB_CFG 0xc001001f 322b72e7464SBorislav Petkov #define MSR_AMD64_PATCH_LOADER 0xc0010020 323b72e7464SBorislav Petkov #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 324b72e7464SBorislav Petkov #define MSR_AMD64_OSVW_STATUS 0xc0010141 325b72e7464SBorislav Petkov #define MSR_AMD64_LS_CFG 0xc0011020 326b72e7464SBorislav Petkov #define MSR_AMD64_DC_CFG 0xc0011022 327b72e7464SBorislav Petkov #define MSR_AMD64_BU_CFG2 0xc001102a 328b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCHCTL 0xc0011030 329b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 330b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 331b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCH_REG_COUNT 3 332b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 333b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPCTL 0xc0011033 334b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPRIP 0xc0011034 335b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA 0xc0011035 336b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA2 0xc0011036 337b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA3 0xc0011037 338b72e7464SBorislav Petkov #define MSR_AMD64_IBSDCLINAD 0xc0011038 339b72e7464SBorislav Petkov #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 340b72e7464SBorislav Petkov #define MSR_AMD64_IBSOP_REG_COUNT 7 341b72e7464SBorislav Petkov #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 342b72e7464SBorislav Petkov #define MSR_AMD64_IBSCTL 0xc001103a 343b72e7464SBorislav Petkov #define MSR_AMD64_IBSBRTARGET 0xc001103b 344b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA4 0xc001103d 345b72e7464SBorislav Petkov #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 3461958b5fcSTom Lendacky #define MSR_AMD64_SEV 0xc0010131 3471958b5fcSTom Lendacky #define MSR_AMD64_SEV_ENABLED_BIT 0 3481958b5fcSTom Lendacky #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) 349b72e7464SBorislav Petkov 35011fb0683STom Lendacky #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f 35111fb0683STom Lendacky 352aaf24884SHuang Rui /* Fam 17h MSRs */ 353aaf24884SHuang Rui #define MSR_F17H_IRPERF 0xc00000e9 354aaf24884SHuang Rui 355b72e7464SBorislav Petkov /* Fam 16h MSRs */ 356b72e7464SBorislav Petkov #define MSR_F16H_L2I_PERF_CTL 0xc0010230 357b72e7464SBorislav Petkov #define MSR_F16H_L2I_PERF_CTR 0xc0010231 358b72e7464SBorislav Petkov #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 359b72e7464SBorislav Petkov #define MSR_F16H_DR2_ADDR_MASK 0xc001101a 360b72e7464SBorislav Petkov #define MSR_F16H_DR3_ADDR_MASK 0xc001101b 361b72e7464SBorislav Petkov #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 362b72e7464SBorislav Petkov 363b72e7464SBorislav Petkov /* Fam 15h MSRs */ 364b72e7464SBorislav Petkov #define MSR_F15H_PERF_CTL 0xc0010200 365e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 366e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 367e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 368e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 369e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 370e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 371e84b7119SJanakarajan Natarajan 372b72e7464SBorislav Petkov #define MSR_F15H_PERF_CTR 0xc0010201 373e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 374e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 375e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 376e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 377e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 378e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 379e84b7119SJanakarajan Natarajan 380b72e7464SBorislav Petkov #define MSR_F15H_NB_PERF_CTL 0xc0010240 381b72e7464SBorislav Petkov #define MSR_F15H_NB_PERF_CTR 0xc0010241 3828a224261SHuang Rui #define MSR_F15H_PTSC 0xc0010280 383ae8b7875SBorislav Petkov #define MSR_F15H_IC_CFG 0xc0011021 384b72e7464SBorislav Petkov 385b72e7464SBorislav Petkov /* Fam 10h MSRs */ 386b72e7464SBorislav Petkov #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 387b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_ENABLE (1<<0) 388b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 389b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 390b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 391b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BASE_SHIFT 20 392b72e7464SBorislav Petkov #define MSR_FAM10H_NODE_ID 0xc001100c 393e4d0e84eSTom Lendacky #define MSR_F10H_DECFG 0xc0011029 394e4d0e84eSTom Lendacky #define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1 3959c6a73c7STom Lendacky #define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT) 396b72e7464SBorislav Petkov 397b72e7464SBorislav Petkov /* K8 MSRs */ 398b72e7464SBorislav Petkov #define MSR_K8_TOP_MEM1 0xc001001a 399b72e7464SBorislav Petkov #define MSR_K8_TOP_MEM2 0xc001001d 400b72e7464SBorislav Petkov #define MSR_K8_SYSCFG 0xc0010010 401872cbefdSTom Lendacky #define MSR_K8_SYSCFG_MEM_ENCRYPT_BIT 23 402872cbefdSTom Lendacky #define MSR_K8_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_K8_SYSCFG_MEM_ENCRYPT_BIT) 403b72e7464SBorislav Petkov #define MSR_K8_INT_PENDING_MSG 0xc0010055 404b72e7464SBorislav Petkov /* C1E active bits in int pending message */ 405b72e7464SBorislav Petkov #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 406b72e7464SBorislav Petkov #define MSR_K8_TSEG_ADDR 0xc0010112 4073afb1121SPaolo Bonzini #define MSR_K8_TSEG_MASK 0xc0010113 408b72e7464SBorislav Petkov #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 409b72e7464SBorislav Petkov #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 410b72e7464SBorislav Petkov #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 411b72e7464SBorislav Petkov 412b72e7464SBorislav Petkov /* K7 MSRs */ 413b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL0 0xc0010000 414b72e7464SBorislav Petkov #define MSR_K7_PERFCTR0 0xc0010004 415b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL1 0xc0010001 416b72e7464SBorislav Petkov #define MSR_K7_PERFCTR1 0xc0010005 417b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL2 0xc0010002 418b72e7464SBorislav Petkov #define MSR_K7_PERFCTR2 0xc0010006 419b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL3 0xc0010003 420b72e7464SBorislav Petkov #define MSR_K7_PERFCTR3 0xc0010007 421b72e7464SBorislav Petkov #define MSR_K7_CLK_CTL 0xc001001b 422b72e7464SBorislav Petkov #define MSR_K7_HWCR 0xc0010015 42318c71ce9STom Lendacky #define MSR_K7_HWCR_SMMLOCK_BIT 0 42418c71ce9STom Lendacky #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) 425b72e7464SBorislav Petkov #define MSR_K7_FID_VID_CTL 0xc0010041 426b72e7464SBorislav Petkov #define MSR_K7_FID_VID_STATUS 0xc0010042 427b72e7464SBorislav Petkov 428b72e7464SBorislav Petkov /* K6 MSRs */ 429b72e7464SBorislav Petkov #define MSR_K6_WHCR 0xc0000082 430b72e7464SBorislav Petkov #define MSR_K6_UWCCR 0xc0000085 431b72e7464SBorislav Petkov #define MSR_K6_EPMR 0xc0000086 432b72e7464SBorislav Petkov #define MSR_K6_PSOR 0xc0000087 433b72e7464SBorislav Petkov #define MSR_K6_PFIR 0xc0000088 434b72e7464SBorislav Petkov 435b72e7464SBorislav Petkov /* Centaur-Hauls/IDT defined MSRs. */ 436b72e7464SBorislav Petkov #define MSR_IDT_FCR1 0x00000107 437b72e7464SBorislav Petkov #define MSR_IDT_FCR2 0x00000108 438b72e7464SBorislav Petkov #define MSR_IDT_FCR3 0x00000109 439b72e7464SBorislav Petkov #define MSR_IDT_FCR4 0x0000010a 440b72e7464SBorislav Petkov 441b72e7464SBorislav Petkov #define MSR_IDT_MCR0 0x00000110 442b72e7464SBorislav Petkov #define MSR_IDT_MCR1 0x00000111 443b72e7464SBorislav Petkov #define MSR_IDT_MCR2 0x00000112 444b72e7464SBorislav Petkov #define MSR_IDT_MCR3 0x00000113 445b72e7464SBorislav Petkov #define MSR_IDT_MCR4 0x00000114 446b72e7464SBorislav Petkov #define MSR_IDT_MCR5 0x00000115 447b72e7464SBorislav Petkov #define MSR_IDT_MCR6 0x00000116 448b72e7464SBorislav Petkov #define MSR_IDT_MCR7 0x00000117 449b72e7464SBorislav Petkov #define MSR_IDT_MCR_CTRL 0x00000120 450b72e7464SBorislav Petkov 451b72e7464SBorislav Petkov /* VIA Cyrix defined MSRs*/ 452b72e7464SBorislav Petkov #define MSR_VIA_FCR 0x00001107 453b72e7464SBorislav Petkov #define MSR_VIA_LONGHAUL 0x0000110a 454b72e7464SBorislav Petkov #define MSR_VIA_RNG 0x0000110b 455b72e7464SBorislav Petkov #define MSR_VIA_BCR2 0x00001147 456b72e7464SBorislav Petkov 457b72e7464SBorislav Petkov /* Transmeta defined MSRs */ 458b72e7464SBorislav Petkov #define MSR_TMTA_LONGRUN_CTRL 0x80868010 459b72e7464SBorislav Petkov #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 460b72e7464SBorislav Petkov #define MSR_TMTA_LRTI_READOUT 0x80868018 461b72e7464SBorislav Petkov #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 462b72e7464SBorislav Petkov 463b72e7464SBorislav Petkov /* Intel defined MSRs. */ 464b72e7464SBorislav Petkov #define MSR_IA32_P5_MC_ADDR 0x00000000 465b72e7464SBorislav Petkov #define MSR_IA32_P5_MC_TYPE 0x00000001 466b72e7464SBorislav Petkov #define MSR_IA32_TSC 0x00000010 467b72e7464SBorislav Petkov #define MSR_IA32_PLATFORM_ID 0x00000017 468b72e7464SBorislav Petkov #define MSR_IA32_EBL_CR_POWERON 0x0000002a 469b72e7464SBorislav Petkov #define MSR_EBC_FREQUENCY_ID 0x0000002c 470b72e7464SBorislav Petkov #define MSR_SMI_COUNT 0x00000034 471b72e7464SBorislav Petkov #define MSR_IA32_FEATURE_CONTROL 0x0000003a 472b72e7464SBorislav Petkov #define MSR_IA32_TSC_ADJUST 0x0000003b 473b72e7464SBorislav Petkov #define MSR_IA32_BNDCFGS 0x00000d90 474b72e7464SBorislav Petkov 4754531662dSJim Mattson #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 4764531662dSJim Mattson 477b72e7464SBorislav Petkov #define MSR_IA32_XSS 0x00000da0 478b72e7464SBorislav Petkov 479b72e7464SBorislav Petkov #define FEATURE_CONTROL_LOCKED (1<<0) 480b72e7464SBorislav Petkov #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 481b72e7464SBorislav Petkov #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 482b72e7464SBorislav Petkov #define FEATURE_CONTROL_LMCE (1<<20) 483b72e7464SBorislav Petkov 484b72e7464SBorislav Petkov #define MSR_IA32_APICBASE 0x0000001b 485b72e7464SBorislav Petkov #define MSR_IA32_APICBASE_BSP (1<<8) 486b72e7464SBorislav Petkov #define MSR_IA32_APICBASE_ENABLE (1<<11) 487b72e7464SBorislav Petkov #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 488b72e7464SBorislav Petkov 489b72e7464SBorislav Petkov #define MSR_IA32_TSCDEADLINE 0x000006e0 490b72e7464SBorislav Petkov 491b72e7464SBorislav Petkov #define MSR_IA32_UCODE_WRITE 0x00000079 492b72e7464SBorislav Petkov #define MSR_IA32_UCODE_REV 0x0000008b 493b72e7464SBorislav Petkov 494b72e7464SBorislav Petkov #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 495b72e7464SBorislav Petkov #define MSR_IA32_SMBASE 0x0000009e 496b72e7464SBorislav Petkov 497b72e7464SBorislav Petkov #define MSR_IA32_PERF_STATUS 0x00000198 498b72e7464SBorislav Petkov #define MSR_IA32_PERF_CTL 0x00000199 499b72e7464SBorislav Petkov #define INTEL_PERF_CTL_MASK 0xffff 500b72e7464SBorislav Petkov #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 501b72e7464SBorislav Petkov #define MSR_AMD_PERF_STATUS 0xc0010063 502b72e7464SBorislav Petkov #define MSR_AMD_PERF_CTL 0xc0010062 503b72e7464SBorislav Petkov 504b72e7464SBorislav Petkov #define MSR_IA32_MPERF 0x000000e7 505b72e7464SBorislav Petkov #define MSR_IA32_APERF 0x000000e8 506b72e7464SBorislav Petkov 507b72e7464SBorislav Petkov #define MSR_IA32_THERM_CONTROL 0x0000019a 508b72e7464SBorislav Petkov #define MSR_IA32_THERM_INTERRUPT 0x0000019b 509b72e7464SBorislav Petkov 510b72e7464SBorislav Petkov #define THERM_INT_HIGH_ENABLE (1 << 0) 511b72e7464SBorislav Petkov #define THERM_INT_LOW_ENABLE (1 << 1) 512b72e7464SBorislav Petkov #define THERM_INT_PLN_ENABLE (1 << 24) 513b72e7464SBorislav Petkov 514b72e7464SBorislav Petkov #define MSR_IA32_THERM_STATUS 0x0000019c 515b72e7464SBorislav Petkov 516b72e7464SBorislav Petkov #define THERM_STATUS_PROCHOT (1 << 0) 517b72e7464SBorislav Petkov #define THERM_STATUS_POWER_LIMIT (1 << 10) 518b72e7464SBorislav Petkov 519b72e7464SBorislav Petkov #define MSR_THERM2_CTL 0x0000019d 520b72e7464SBorislav Petkov 521b72e7464SBorislav Petkov #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 522b72e7464SBorislav Petkov 523b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE 0x000001a0 524b72e7464SBorislav Petkov 525b72e7464SBorislav Petkov #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 526b72e7464SBorislav Petkov 52798af7459SLen Brown #define MSR_MISC_FEATURE_CONTROL 0x000001a4 528b72e7464SBorislav Petkov #define MSR_MISC_PWR_MGMT 0x000001aa 529b72e7464SBorislav Petkov 530b72e7464SBorislav Petkov #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 531b72e7464SBorislav Petkov #define ENERGY_PERF_BIAS_PERFORMANCE 0 532d0117a0eSLen Brown #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 533b72e7464SBorislav Petkov #define ENERGY_PERF_BIAS_NORMAL 6 534d0117a0eSLen Brown #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 535b72e7464SBorislav Petkov #define ENERGY_PERF_BIAS_POWERSAVE 15 536b72e7464SBorislav Petkov 537b72e7464SBorislav Petkov #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 538b72e7464SBorislav Petkov 539b72e7464SBorislav Petkov #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 540b72e7464SBorislav Petkov #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 541b72e7464SBorislav Petkov 542b72e7464SBorislav Petkov #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 543b72e7464SBorislav Petkov 544b72e7464SBorislav Petkov #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 545b72e7464SBorislav Petkov #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 546b72e7464SBorislav Petkov #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 547b72e7464SBorislav Petkov 548b72e7464SBorislav Petkov /* Thermal Thresholds Support */ 549b72e7464SBorislav Petkov #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 550b72e7464SBorislav Petkov #define THERM_SHIFT_THRESHOLD0 8 551b72e7464SBorislav Petkov #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 552b72e7464SBorislav Petkov #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 553b72e7464SBorislav Petkov #define THERM_SHIFT_THRESHOLD1 16 554b72e7464SBorislav Petkov #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 555b72e7464SBorislav Petkov #define THERM_STATUS_THRESHOLD0 (1 << 6) 556b72e7464SBorislav Petkov #define THERM_LOG_THRESHOLD0 (1 << 7) 557b72e7464SBorislav Petkov #define THERM_STATUS_THRESHOLD1 (1 << 8) 558b72e7464SBorislav Petkov #define THERM_LOG_THRESHOLD1 (1 << 9) 559b72e7464SBorislav Petkov 560b72e7464SBorislav Petkov /* MISC_ENABLE bits: architectural */ 561b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 562b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 563b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 564b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 565b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 566b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 567b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 568b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 569b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 570b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 571b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 572b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 573b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 574b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 575b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 576b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 577b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 578b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 579b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 580b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 581b72e7464SBorislav Petkov 582b72e7464SBorislav Petkov /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 583b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 584b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 585b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 586b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 587b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 588b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 589b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 590b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 591b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 592b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 593b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 594b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 595b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 596b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 597b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 598b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 599b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 600b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 601b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 602b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 603b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 604b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 605b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 606b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 607b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 608b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 609b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 610b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 611b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 612b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 613b72e7464SBorislav Petkov 614ab6d9468SKyle Huey /* MISC_FEATURES_ENABLES non-architectural features */ 615ab6d9468SKyle Huey #define MSR_MISC_FEATURES_ENABLES 0x00000140 616ae47eda9SGrzegorz Andrejczuk 617e9ea1e7fSKyle Huey #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 618e9ea1e7fSKyle Huey #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) 619ab6d9468SKyle Huey #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 620ae47eda9SGrzegorz Andrejczuk 621b72e7464SBorislav Petkov #define MSR_IA32_TSC_DEADLINE 0x000006E0 622b72e7464SBorislav Petkov 623b72e7464SBorislav Petkov /* P4/Xeon+ specific */ 624b72e7464SBorislav Petkov #define MSR_IA32_MCG_EAX 0x00000180 625b72e7464SBorislav Petkov #define MSR_IA32_MCG_EBX 0x00000181 626b72e7464SBorislav Petkov #define MSR_IA32_MCG_ECX 0x00000182 627b72e7464SBorislav Petkov #define MSR_IA32_MCG_EDX 0x00000183 628b72e7464SBorislav Petkov #define MSR_IA32_MCG_ESI 0x00000184 629b72e7464SBorislav Petkov #define MSR_IA32_MCG_EDI 0x00000185 630b72e7464SBorislav Petkov #define MSR_IA32_MCG_EBP 0x00000186 631b72e7464SBorislav Petkov #define MSR_IA32_MCG_ESP 0x00000187 632b72e7464SBorislav Petkov #define MSR_IA32_MCG_EFLAGS 0x00000188 633b72e7464SBorislav Petkov #define MSR_IA32_MCG_EIP 0x00000189 634b72e7464SBorislav Petkov #define MSR_IA32_MCG_RESERVED 0x0000018a 635b72e7464SBorislav Petkov 636b72e7464SBorislav Petkov /* Pentium IV performance counter MSRs */ 637b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR0 0x00000300 638b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR1 0x00000301 639b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR2 0x00000302 640b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR3 0x00000303 641b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR0 0x00000304 642b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR1 0x00000305 643b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR2 0x00000306 644b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR3 0x00000307 645b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR0 0x00000308 646b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR1 0x00000309 647b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR2 0x0000030a 648b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR3 0x0000030b 649b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR0 0x0000030c 650b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR1 0x0000030d 651b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR2 0x0000030e 652b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR3 0x0000030f 653b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR4 0x00000310 654b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR5 0x00000311 655b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR0 0x00000360 656b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR1 0x00000361 657b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR2 0x00000362 658b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR3 0x00000363 659b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR0 0x00000364 660b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR1 0x00000365 661b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR2 0x00000366 662b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR3 0x00000367 663b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR0 0x00000368 664b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR1 0x00000369 665b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR2 0x0000036a 666b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR3 0x0000036b 667b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR0 0x0000036c 668b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR1 0x0000036d 669b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR2 0x0000036e 670b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR3 0x0000036f 671b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR4 0x00000370 672b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR5 0x00000371 673b72e7464SBorislav Petkov #define MSR_P4_ALF_ESCR0 0x000003ca 674b72e7464SBorislav Petkov #define MSR_P4_ALF_ESCR1 0x000003cb 675b72e7464SBorislav Petkov #define MSR_P4_BPU_ESCR0 0x000003b2 676b72e7464SBorislav Petkov #define MSR_P4_BPU_ESCR1 0x000003b3 677b72e7464SBorislav Petkov #define MSR_P4_BSU_ESCR0 0x000003a0 678b72e7464SBorislav Petkov #define MSR_P4_BSU_ESCR1 0x000003a1 679b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR0 0x000003b8 680b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR1 0x000003b9 681b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR2 0x000003cc 682b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR3 0x000003cd 683b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR4 0x000003e0 684b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR5 0x000003e1 685b72e7464SBorislav Petkov #define MSR_P4_DAC_ESCR0 0x000003a8 686b72e7464SBorislav Petkov #define MSR_P4_DAC_ESCR1 0x000003a9 687b72e7464SBorislav Petkov #define MSR_P4_FIRM_ESCR0 0x000003a4 688b72e7464SBorislav Petkov #define MSR_P4_FIRM_ESCR1 0x000003a5 689b72e7464SBorislav Petkov #define MSR_P4_FLAME_ESCR0 0x000003a6 690b72e7464SBorislav Petkov #define MSR_P4_FLAME_ESCR1 0x000003a7 691b72e7464SBorislav Petkov #define MSR_P4_FSB_ESCR0 0x000003a2 692b72e7464SBorislav Petkov #define MSR_P4_FSB_ESCR1 0x000003a3 693b72e7464SBorislav Petkov #define MSR_P4_IQ_ESCR0 0x000003ba 694b72e7464SBorislav Petkov #define MSR_P4_IQ_ESCR1 0x000003bb 695b72e7464SBorislav Petkov #define MSR_P4_IS_ESCR0 0x000003b4 696b72e7464SBorislav Petkov #define MSR_P4_IS_ESCR1 0x000003b5 697b72e7464SBorislav Petkov #define MSR_P4_ITLB_ESCR0 0x000003b6 698b72e7464SBorislav Petkov #define MSR_P4_ITLB_ESCR1 0x000003b7 699b72e7464SBorislav Petkov #define MSR_P4_IX_ESCR0 0x000003c8 700b72e7464SBorislav Petkov #define MSR_P4_IX_ESCR1 0x000003c9 701b72e7464SBorislav Petkov #define MSR_P4_MOB_ESCR0 0x000003aa 702b72e7464SBorislav Petkov #define MSR_P4_MOB_ESCR1 0x000003ab 703b72e7464SBorislav Petkov #define MSR_P4_MS_ESCR0 0x000003c0 704b72e7464SBorislav Petkov #define MSR_P4_MS_ESCR1 0x000003c1 705b72e7464SBorislav Petkov #define MSR_P4_PMH_ESCR0 0x000003ac 706b72e7464SBorislav Petkov #define MSR_P4_PMH_ESCR1 0x000003ad 707b72e7464SBorislav Petkov #define MSR_P4_RAT_ESCR0 0x000003bc 708b72e7464SBorislav Petkov #define MSR_P4_RAT_ESCR1 0x000003bd 709b72e7464SBorislav Petkov #define MSR_P4_SAAT_ESCR0 0x000003ae 710b72e7464SBorislav Petkov #define MSR_P4_SAAT_ESCR1 0x000003af 711b72e7464SBorislav Petkov #define MSR_P4_SSU_ESCR0 0x000003be 712b72e7464SBorislav Petkov #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 713b72e7464SBorislav Petkov 714b72e7464SBorislav Petkov #define MSR_P4_TBPU_ESCR0 0x000003c2 715b72e7464SBorislav Petkov #define MSR_P4_TBPU_ESCR1 0x000003c3 716b72e7464SBorislav Petkov #define MSR_P4_TC_ESCR0 0x000003c4 717b72e7464SBorislav Petkov #define MSR_P4_TC_ESCR1 0x000003c5 718b72e7464SBorislav Petkov #define MSR_P4_U2L_ESCR0 0x000003b0 719b72e7464SBorislav Petkov #define MSR_P4_U2L_ESCR1 0x000003b1 720b72e7464SBorislav Petkov 721b72e7464SBorislav Petkov #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 722b72e7464SBorislav Petkov 723b72e7464SBorislav Petkov /* Intel Core-based CPU performance counters */ 724b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 725b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 726b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 727b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 728b72e7464SBorislav Petkov #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 729b72e7464SBorislav Petkov #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 730b72e7464SBorislav Petkov #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 731b72e7464SBorislav Petkov 732b72e7464SBorislav Petkov /* Geode defined MSRs */ 733b72e7464SBorislav Petkov #define MSR_GEODE_BUSCONT_CONF0 0x00001900 734b72e7464SBorislav Petkov 735b72e7464SBorislav Petkov /* Intel VT MSRs */ 736b72e7464SBorislav Petkov #define MSR_IA32_VMX_BASIC 0x00000480 737b72e7464SBorislav Petkov #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 738b72e7464SBorislav Petkov #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 739b72e7464SBorislav Petkov #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 740b72e7464SBorislav Petkov #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 741b72e7464SBorislav Petkov #define MSR_IA32_VMX_MISC 0x00000485 742b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 743b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 744b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 745b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 746b72e7464SBorislav Petkov #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 747b72e7464SBorislav Petkov #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 748b72e7464SBorislav Petkov #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 749b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 750b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 751b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 752b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 753b72e7464SBorislav Petkov #define MSR_IA32_VMX_VMFUNC 0x00000491 754b72e7464SBorislav Petkov 755b72e7464SBorislav Petkov /* VMX_BASIC bits and bitmasks */ 756b72e7464SBorislav Petkov #define VMX_BASIC_VMCS_SIZE_SHIFT 32 757b72e7464SBorislav Petkov #define VMX_BASIC_TRUE_CTLS (1ULL << 55) 758b72e7464SBorislav Petkov #define VMX_BASIC_64 0x0001000000000000LLU 759b72e7464SBorislav Petkov #define VMX_BASIC_MEM_TYPE_SHIFT 50 760b72e7464SBorislav Petkov #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 761b72e7464SBorislav Petkov #define VMX_BASIC_MEM_TYPE_WB 6LLU 762b72e7464SBorislav Petkov #define VMX_BASIC_INOUT 0x0040000000000000LLU 763b72e7464SBorislav Petkov 764b72e7464SBorislav Petkov /* MSR_IA32_VMX_MISC bits */ 765b72e7464SBorislav Petkov #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 766b72e7464SBorislav Petkov #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 767b72e7464SBorislav Petkov /* AMD-V MSRs */ 768b72e7464SBorislav Petkov 769b72e7464SBorislav Petkov #define MSR_VM_CR 0xc0010114 770b72e7464SBorislav Petkov #define MSR_VM_IGNNE 0xc0010115 771b72e7464SBorislav Petkov #define MSR_VM_HSAVE_PA 0xc0010117 772b72e7464SBorislav Petkov 773b72e7464SBorislav Petkov #endif /* _ASM_X86_MSR_INDEX_H */ 774