1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2b72e7464SBorislav Petkov #ifndef _ASM_X86_MSR_INDEX_H 3b72e7464SBorislav Petkov #define _ASM_X86_MSR_INDEX_H 4b72e7464SBorislav Petkov 5d8eabc37SThomas Gleixner #include <linux/bits.h> 6d8eabc37SThomas Gleixner 797fa21f6SBorislav Petkov /* CPU model specific register (MSR) numbers. */ 8b72e7464SBorislav Petkov 9b72e7464SBorislav Petkov /* x86-64 specific MSRs */ 10b72e7464SBorislav Petkov #define MSR_EFER 0xc0000080 /* extended feature register */ 11b72e7464SBorislav Petkov #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 12b72e7464SBorislav Petkov #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 13b72e7464SBorislav Petkov #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 14b72e7464SBorislav Petkov #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 15b72e7464SBorislav Petkov #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 16b72e7464SBorislav Petkov #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 17b72e7464SBorislav Petkov #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 18b72e7464SBorislav Petkov #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 19b72e7464SBorislav Petkov 20b72e7464SBorislav Petkov /* EFER bits: */ 21b72e7464SBorislav Petkov #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 22b72e7464SBorislav Petkov #define _EFER_LME 8 /* Long mode enable */ 23b72e7464SBorislav Petkov #define _EFER_LMA 10 /* Long mode active (read-only) */ 24b72e7464SBorislav Petkov #define _EFER_NX 11 /* No execute enable */ 25b72e7464SBorislav Petkov #define _EFER_SVME 12 /* Enable virtualization */ 26b72e7464SBorislav Petkov #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 27b72e7464SBorislav Petkov #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 28e7862edaSKim Phillips #define _EFER_AUTOIBRS 21 /* Enable Automatic IBRS */ 29b72e7464SBorislav Petkov 30b72e7464SBorislav Petkov #define EFER_SCE (1<<_EFER_SCE) 31b72e7464SBorislav Petkov #define EFER_LME (1<<_EFER_LME) 32b72e7464SBorislav Petkov #define EFER_LMA (1<<_EFER_LMA) 33b72e7464SBorislav Petkov #define EFER_NX (1<<_EFER_NX) 34b72e7464SBorislav Petkov #define EFER_SVME (1<<_EFER_SVME) 35b72e7464SBorislav Petkov #define EFER_LMSLE (1<<_EFER_LMSLE) 36b72e7464SBorislav Petkov #define EFER_FFXSR (1<<_EFER_FFXSR) 37e7862edaSKim Phillips #define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS) 38b72e7464SBorislav Petkov 39b72e7464SBorislav Petkov /* Intel MSRs. Some also available on other CPUs */ 403f5a7896STony Luck 416650cdd9SPeter Zijlstra (Intel) #define MSR_TEST_CTRL 0x00000033 426650cdd9SPeter Zijlstra (Intel) #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 436650cdd9SPeter Zijlstra (Intel) #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) 446650cdd9SPeter Zijlstra (Intel) 451e340c60SDavid Woodhouse #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 46d8eabc37SThomas Gleixner #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ 475bfbe3adSTim Chen #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ 48d8eabc37SThomas Gleixner #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ 499f65fb29SKonrad Rzeszutek Wilk #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ 50d8eabc37SThomas Gleixner #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ 514ad3278dSPawan Gupta #define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */ 524ad3278dSPawan Gupta #define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT) 531e340c60SDavid Woodhouse 540125acdaSBreno Leitao /* A mask for bits which the kernel toggles when controlling mitigations */ 550125acdaSBreno Leitao #define SPEC_CTRL_MITIGATIONS_MASK (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \ 560125acdaSBreno Leitao | SPEC_CTRL_RRSBA_DIS_S) 570125acdaSBreno Leitao 581e340c60SDavid Woodhouse #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 59d8eabc37SThomas Gleixner #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ 60*1b5277c0SBorislav Petkov (AMD) #define PRED_CMD_SBPB BIT(7) /* Selective Branch Prediction Barrier */ 611e340c60SDavid Woodhouse 623f5a7896STony Luck #define MSR_PPIN_CTL 0x0000004e 633f5a7896STony Luck #define MSR_PPIN 0x0000004f 643f5a7896STony Luck 65b72e7464SBorislav Petkov #define MSR_IA32_PERFCTR0 0x000000c1 66b72e7464SBorislav Petkov #define MSR_IA32_PERFCTR1 0x000000c2 67b72e7464SBorislav Petkov #define MSR_FSB_FREQ 0x000000cd 685369a21eSLen Brown #define MSR_PLATFORM_INFO 0x000000ce 6990218ac7SKyle Huey #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 7090218ac7SKyle Huey #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) 71b72e7464SBorislav Petkov 72bd688c69SFenghua Yu #define MSR_IA32_UMWAIT_CONTROL 0xe1 73bd688c69SFenghua Yu #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0) 74bd688c69SFenghua Yu #define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1) 75bd688c69SFenghua Yu /* 76bd688c69SFenghua Yu * The time field is bit[31:2], but representing a 32bit value with 77bd688c69SFenghua Yu * bit[1:0] zero. 78bd688c69SFenghua Yu */ 79bd688c69SFenghua Yu #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U) 80bd688c69SFenghua Yu 816650cdd9SPeter Zijlstra (Intel) /* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */ 826650cdd9SPeter Zijlstra (Intel) #define MSR_IA32_CORE_CAPS 0x000000cf 83db1af129STony Luck #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT 2 84db1af129STony Luck #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT) 856650cdd9SPeter Zijlstra (Intel) #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5 866650cdd9SPeter Zijlstra (Intel) #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT) 876650cdd9SPeter Zijlstra (Intel) 8840496c8eSLen Brown #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 89b72e7464SBorislav Petkov #define NHM_C3_AUTO_DEMOTE (1UL << 25) 90b72e7464SBorislav Petkov #define NHM_C1_AUTO_DEMOTE (1UL << 26) 91b72e7464SBorislav Petkov #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 92a00072a2SMatt Turner #define SNB_C3_AUTO_UNDEMOTE (1UL << 27) 93a00072a2SMatt Turner #define SNB_C1_AUTO_UNDEMOTE (1UL << 28) 94b72e7464SBorislav Petkov 95b72e7464SBorislav Petkov #define MSR_MTRRcap 0x000000fe 961e340c60SDavid Woodhouse 971e340c60SDavid Woodhouse #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 98d8eabc37SThomas Gleixner #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ 99d8eabc37SThomas Gleixner #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ 1006ad0ad2bSPeter Zijlstra #define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */ 101d8eabc37SThomas Gleixner #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ 102d8eabc37SThomas Gleixner #define ARCH_CAP_SSB_NO BIT(4) /* 10377243971SKonrad Rzeszutek Wilk * Not susceptible to Speculative Store Bypass 1049f65fb29SKonrad Rzeszutek Wilk * attack, so no Speculative Store Bypass 1059f65fb29SKonrad Rzeszutek Wilk * control required. 10677243971SKonrad Rzeszutek Wilk */ 107ed5194c2SAndi Kleen #define ARCH_CAP_MDS_NO BIT(5) /* 108ed5194c2SAndi Kleen * Not susceptible to 109ed5194c2SAndi Kleen * Microarchitectural Data 110ed5194c2SAndi Kleen * Sampling (MDS) vulnerabilities. 111ed5194c2SAndi Kleen */ 112db4d30fbSVineela Tummalapalli #define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* 113db4d30fbSVineela Tummalapalli * The processor is not susceptible to a 114db4d30fbSVineela Tummalapalli * machine check error due to modifying the 115db4d30fbSVineela Tummalapalli * code page size along with either the 116db4d30fbSVineela Tummalapalli * physical address or cache type 117db4d30fbSVineela Tummalapalli * without TLB invalidation. 118db4d30fbSVineela Tummalapalli */ 119c2955f27SPawan Gupta #define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ 1201b42f017SPawan Gupta #define ARCH_CAP_TAA_NO BIT(8) /* 1211b42f017SPawan Gupta * Not susceptible to 1221b42f017SPawan Gupta * TSX Async Abort (TAA) vulnerabilities. 1231b42f017SPawan Gupta */ 12451802186SPawan Gupta #define ARCH_CAP_SBDR_SSDP_NO BIT(13) /* 12551802186SPawan Gupta * Not susceptible to SBDR and SSDP 12651802186SPawan Gupta * variants of Processor MMIO stale data 12751802186SPawan Gupta * vulnerabilities. 12851802186SPawan Gupta */ 12951802186SPawan Gupta #define ARCH_CAP_FBSDP_NO BIT(14) /* 13051802186SPawan Gupta * Not susceptible to FBSDP variant of 13151802186SPawan Gupta * Processor MMIO stale data 13251802186SPawan Gupta * vulnerabilities. 13351802186SPawan Gupta */ 13451802186SPawan Gupta #define ARCH_CAP_PSDP_NO BIT(15) /* 13551802186SPawan Gupta * Not susceptible to PSDP variant of 13651802186SPawan Gupta * Processor MMIO stale data 13751802186SPawan Gupta * vulnerabilities. 13851802186SPawan Gupta */ 13951802186SPawan Gupta #define ARCH_CAP_FB_CLEAR BIT(17) /* 14051802186SPawan Gupta * VERW clears CPU fill buffer 14151802186SPawan Gupta * even on MDS_NO CPUs. 14251802186SPawan Gupta */ 143027bbb88SPawan Gupta #define ARCH_CAP_FB_CLEAR_CTRL BIT(18) /* 144027bbb88SPawan Gupta * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS] 145027bbb88SPawan Gupta * bit available to control VERW 146027bbb88SPawan Gupta * behavior. 147027bbb88SPawan Gupta */ 1484ad3278dSPawan Gupta #define ARCH_CAP_RRSBA BIT(19) /* 1494ad3278dSPawan Gupta * Indicates RET may use predictors 1504ad3278dSPawan Gupta * other than the RSB. With eIBRS 1514ad3278dSPawan Gupta * enabled predictions in kernel mode 1524ad3278dSPawan Gupta * are restricted to targets in 1534ad3278dSPawan Gupta * kernel. 1544ad3278dSPawan Gupta */ 1552b129932SDaniel Sneddon #define ARCH_CAP_PBRSB_NO BIT(24) /* 1562b129932SDaniel Sneddon * Not susceptible to Post-Barrier 1572b129932SDaniel Sneddon * Return Stack Buffer Predictions. 1582b129932SDaniel Sneddon */ 1591e340c60SDavid Woodhouse 160b8d1d163SDaniel Sneddon #define ARCH_CAP_XAPIC_DISABLE BIT(21) /* 161b8d1d163SDaniel Sneddon * IA32_XAPIC_DISABLE_STATUS MSR 162b8d1d163SDaniel Sneddon * supported 163b8d1d163SDaniel Sneddon */ 164b8d1d163SDaniel Sneddon 1653fa045beSPaolo Bonzini #define MSR_IA32_FLUSH_CMD 0x0000010b 166d8eabc37SThomas Gleixner #define L1D_FLUSH BIT(0) /* 1673fa045beSPaolo Bonzini * Writeback and invalidate the 1683fa045beSPaolo Bonzini * L1 data cache. 1693fa045beSPaolo Bonzini */ 1703fa045beSPaolo Bonzini 171b72e7464SBorislav Petkov #define MSR_IA32_BBL_CR_CTL 0x00000119 172b72e7464SBorislav Petkov #define MSR_IA32_BBL_CR_CTL3 0x0000011e 173b72e7464SBorislav Petkov 174c2955f27SPawan Gupta #define MSR_IA32_TSX_CTRL 0x00000122 175c2955f27SPawan Gupta #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ 176c2955f27SPawan Gupta #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ 177c2955f27SPawan Gupta 1787e5b3c26SMark Gross #define MSR_IA32_MCU_OPT_CTRL 0x00000123 179400331f8SPawan Gupta #define RNGDS_MITG_DIS BIT(0) /* SRBDS support */ 180400331f8SPawan Gupta #define RTM_ALLOW BIT(1) /* TSX development mode */ 181027bbb88SPawan Gupta #define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */ 1827e5b3c26SMark Gross 183b72e7464SBorislav Petkov #define MSR_IA32_SYSENTER_CS 0x00000174 184b72e7464SBorislav Petkov #define MSR_IA32_SYSENTER_ESP 0x00000175 185b72e7464SBorislav Petkov #define MSR_IA32_SYSENTER_EIP 0x00000176 186b72e7464SBorislav Petkov 187b72e7464SBorislav Petkov #define MSR_IA32_MCG_CAP 0x00000179 188b72e7464SBorislav Petkov #define MSR_IA32_MCG_STATUS 0x0000017a 189b72e7464SBorislav Petkov #define MSR_IA32_MCG_CTL 0x0000017b 19068299a42STony Luck #define MSR_ERROR_CONTROL 0x0000017f 191b72e7464SBorislav Petkov #define MSR_IA32_MCG_EXT_CTL 0x000004d0 192b72e7464SBorislav Petkov 193b72e7464SBorislav Petkov #define MSR_OFFCORE_RSP_0 0x000001a6 194b72e7464SBorislav Petkov #define MSR_OFFCORE_RSP_1 0x000001a7 195b72e7464SBorislav Petkov #define MSR_TURBO_RATIO_LIMIT 0x000001ad 196b72e7464SBorislav Petkov #define MSR_TURBO_RATIO_LIMIT1 0x000001ae 197b72e7464SBorislav Petkov #define MSR_TURBO_RATIO_LIMIT2 0x000001af 198b72e7464SBorislav Petkov 19938aaf921SKan Liang #define MSR_SNOOP_RSP_0 0x00001328 20038aaf921SKan Liang #define MSR_SNOOP_RSP_1 0x00001329 20138aaf921SKan Liang 202b72e7464SBorislav Petkov #define MSR_LBR_SELECT 0x000001c8 203b72e7464SBorislav Petkov #define MSR_LBR_TOS 0x000001c9 204ed7bde7aSSrinivas Pandruvada 205ed7bde7aSSrinivas Pandruvada #define MSR_IA32_POWER_CTL 0x000001fc 206ed7bde7aSSrinivas Pandruvada #define MSR_IA32_POWER_CTL_BIT_EE 19 207ed7bde7aSSrinivas Pandruvada 208db1af129STony Luck /* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */ 209db1af129STony Luck #define MSR_INTEGRITY_CAPS 0x000002d9 210c68e3d47SJithu Joseph #define MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT 2 211c68e3d47SJithu Joseph #define MSR_INTEGRITY_CAPS_ARRAY_BIST BIT(MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT) 212db1af129STony Luck #define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4 213db1af129STony Luck #define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT) 214db1af129STony Luck 215b72e7464SBorislav Petkov #define MSR_LBR_NHM_FROM 0x00000680 216b72e7464SBorislav Petkov #define MSR_LBR_NHM_TO 0x000006c0 217b72e7464SBorislav Petkov #define MSR_LBR_CORE_FROM 0x00000040 218b72e7464SBorislav Petkov #define MSR_LBR_CORE_TO 0x00000060 219b72e7464SBorislav Petkov 220b83ff1c8SAndi Kleen #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 221b83ff1c8SAndi Kleen #define LBR_INFO_MISPRED BIT_ULL(63) 222b83ff1c8SAndi Kleen #define LBR_INFO_IN_TX BIT_ULL(62) 223b83ff1c8SAndi Kleen #define LBR_INFO_ABORT BIT_ULL(61) 224d6a162a4SKan Liang #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60) 225b83ff1c8SAndi Kleen #define LBR_INFO_CYCLES 0xffff 226d6a162a4SKan Liang #define LBR_INFO_BR_TYPE_OFFSET 56 227d6a162a4SKan Liang #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) 228d6a162a4SKan Liang 229d6a162a4SKan Liang #define MSR_ARCH_LBR_CTL 0x000014ce 230d6a162a4SKan Liang #define ARCH_LBR_CTL_LBREN BIT(0) 231d6a162a4SKan Liang #define ARCH_LBR_CTL_CPL_OFFSET 1 232d6a162a4SKan Liang #define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET) 233d6a162a4SKan Liang #define ARCH_LBR_CTL_STACK_OFFSET 3 234d6a162a4SKan Liang #define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET) 235d6a162a4SKan Liang #define ARCH_LBR_CTL_FILTER_OFFSET 16 236d6a162a4SKan Liang #define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET) 237d6a162a4SKan Liang #define MSR_ARCH_LBR_DEPTH 0x000014cf 238d6a162a4SKan Liang #define MSR_ARCH_LBR_FROM_0 0x00001500 239d6a162a4SKan Liang #define MSR_ARCH_LBR_TO_0 0x00001600 240d6a162a4SKan Liang #define MSR_ARCH_LBR_INFO_0 0x00001200 241b83ff1c8SAndi Kleen 242b72e7464SBorislav Petkov #define MSR_IA32_PEBS_ENABLE 0x000003f1 243c22497f5SKan Liang #define MSR_PEBS_DATA_CFG 0x000003f2 244b72e7464SBorislav Petkov #define MSR_IA32_DS_AREA 0x00000600 245b72e7464SBorislav Petkov #define MSR_IA32_PERF_CAPABILITIES 0x00000345 246d0946a88SKan Liang #define PERF_CAP_METRICS_IDX 15 247d0946a88SKan Liang #define PERF_CAP_PT_IDX 16 248d0946a88SKan Liang 249b72e7464SBorislav Petkov #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 250c59a1f10SLike Xu #define PERF_CAP_PEBS_TRAP BIT_ULL(6) 251c59a1f10SLike Xu #define PERF_CAP_ARCH_REG BIT_ULL(7) 252c59a1f10SLike Xu #define PERF_CAP_PEBS_FORMAT 0xf00 253c59a1f10SLike Xu #define PERF_CAP_PEBS_BASELINE BIT_ULL(14) 254c59a1f10SLike Xu #define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ 255c59a1f10SLike Xu PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE) 256b72e7464SBorislav Petkov 257b72e7464SBorislav Petkov #define MSR_IA32_RTIT_CTL 0x00000570 258887eda13SChao Peng #define RTIT_CTL_TRACEEN BIT(0) 259887eda13SChao Peng #define RTIT_CTL_CYCLEACC BIT(1) 260887eda13SChao Peng #define RTIT_CTL_OS BIT(2) 261887eda13SChao Peng #define RTIT_CTL_USR BIT(3) 262887eda13SChao Peng #define RTIT_CTL_PWR_EVT_EN BIT(4) 263887eda13SChao Peng #define RTIT_CTL_FUP_ON_PTW BIT(5) 26469843a91SLuwei Kang #define RTIT_CTL_FABRIC_EN BIT(6) 265887eda13SChao Peng #define RTIT_CTL_CR3EN BIT(7) 266887eda13SChao Peng #define RTIT_CTL_TOPA BIT(8) 267887eda13SChao Peng #define RTIT_CTL_MTC_EN BIT(9) 268887eda13SChao Peng #define RTIT_CTL_TSC_EN BIT(10) 269887eda13SChao Peng #define RTIT_CTL_DISRETC BIT(11) 270887eda13SChao Peng #define RTIT_CTL_PTW_EN BIT(12) 271887eda13SChao Peng #define RTIT_CTL_BRANCH_EN BIT(13) 27228c24dedSAlexander Shishkin #define RTIT_CTL_EVENT_EN BIT(31) 273161a9a33SAlexander Shishkin #define RTIT_CTL_NOTNT BIT_ULL(55) 274887eda13SChao Peng #define RTIT_CTL_MTC_RANGE_OFFSET 14 275887eda13SChao Peng #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 276887eda13SChao Peng #define RTIT_CTL_CYC_THRESH_OFFSET 19 277887eda13SChao Peng #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 278887eda13SChao Peng #define RTIT_CTL_PSB_FREQ_OFFSET 24 279887eda13SChao Peng #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 280887eda13SChao Peng #define RTIT_CTL_ADDR0_OFFSET 32 281887eda13SChao Peng #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) 282887eda13SChao Peng #define RTIT_CTL_ADDR1_OFFSET 36 283887eda13SChao Peng #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) 284887eda13SChao Peng #define RTIT_CTL_ADDR2_OFFSET 40 285887eda13SChao Peng #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) 286887eda13SChao Peng #define RTIT_CTL_ADDR3_OFFSET 44 287887eda13SChao Peng #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) 288b72e7464SBorislav Petkov #define MSR_IA32_RTIT_STATUS 0x00000571 289887eda13SChao Peng #define RTIT_STATUS_FILTEREN BIT(0) 290887eda13SChao Peng #define RTIT_STATUS_CONTEXTEN BIT(1) 291887eda13SChao Peng #define RTIT_STATUS_TRIGGEREN BIT(2) 292887eda13SChao Peng #define RTIT_STATUS_BUFFOVF BIT(3) 293887eda13SChao Peng #define RTIT_STATUS_ERROR BIT(4) 294887eda13SChao Peng #define RTIT_STATUS_STOPPED BIT(5) 29569843a91SLuwei Kang #define RTIT_STATUS_BYTECNT_OFFSET 32 29669843a91SLuwei Kang #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) 297f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR0_A 0x00000580 298f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR0_B 0x00000581 299f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR1_A 0x00000582 300f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR1_B 0x00000583 301f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR2_A 0x00000584 302f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR2_B 0x00000585 303f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR3_A 0x00000586 304f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR3_B 0x00000587 305b72e7464SBorislav Petkov #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 306b72e7464SBorislav Petkov #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 307b72e7464SBorislav Petkov #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 308b72e7464SBorislav Petkov 309b72e7464SBorislav Petkov #define MSR_MTRRfix64K_00000 0x00000250 310b72e7464SBorislav Petkov #define MSR_MTRRfix16K_80000 0x00000258 311b72e7464SBorislav Petkov #define MSR_MTRRfix16K_A0000 0x00000259 312b72e7464SBorislav Petkov #define MSR_MTRRfix4K_C0000 0x00000268 313b72e7464SBorislav Petkov #define MSR_MTRRfix4K_C8000 0x00000269 314b72e7464SBorislav Petkov #define MSR_MTRRfix4K_D0000 0x0000026a 315b72e7464SBorislav Petkov #define MSR_MTRRfix4K_D8000 0x0000026b 316b72e7464SBorislav Petkov #define MSR_MTRRfix4K_E0000 0x0000026c 317b72e7464SBorislav Petkov #define MSR_MTRRfix4K_E8000 0x0000026d 318b72e7464SBorislav Petkov #define MSR_MTRRfix4K_F0000 0x0000026e 319b72e7464SBorislav Petkov #define MSR_MTRRfix4K_F8000 0x0000026f 320b72e7464SBorislav Petkov #define MSR_MTRRdefType 0x000002ff 321b72e7464SBorislav Petkov 322b72e7464SBorislav Petkov #define MSR_IA32_CR_PAT 0x00000277 323b72e7464SBorislav Petkov 324b72e7464SBorislav Petkov #define MSR_IA32_DEBUGCTLMSR 0x000001d9 325b72e7464SBorislav Petkov #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 326b72e7464SBorislav Petkov #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 327b72e7464SBorislav Petkov #define MSR_IA32_LASTINTFROMIP 0x000001dd 328b72e7464SBorislav Petkov #define MSR_IA32_LASTINTTOIP 0x000001de 329b72e7464SBorislav Petkov 330f0f2f9feSFenghua Yu #define MSR_IA32_PASID 0x00000d93 331f0f2f9feSFenghua Yu #define MSR_IA32_PASID_VALID BIT_ULL(31) 332f0f2f9feSFenghua Yu 333b72e7464SBorislav Petkov /* DEBUGCTLMSR bits (others vary by model): */ 334b72e7464SBorislav Petkov #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 335b9894a2fSKyle Huey #define DEBUGCTLMSR_BTF_SHIFT 1 336b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 337ebb1064eSFenghua Yu #define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2) 338b72e7464SBorislav Petkov #define DEBUGCTLMSR_TR (1UL << 6) 339b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTS (1UL << 7) 340b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTINT (1UL << 8) 341b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 342b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 343b72e7464SBorislav Petkov #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 344af3bdb99SAndi Kleen #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) 3456089327fSKan Liang #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 3466089327fSKan Liang #define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 347b72e7464SBorislav Petkov 348d0dc8494SAndi Kleen #define MSR_PEBS_FRONTEND 0x000003f7 349d0dc8494SAndi Kleen 350b72e7464SBorislav Petkov #define MSR_IA32_MC0_CTL 0x00000400 351b72e7464SBorislav Petkov #define MSR_IA32_MC0_STATUS 0x00000401 352b72e7464SBorislav Petkov #define MSR_IA32_MC0_ADDR 0x00000402 353b72e7464SBorislav Petkov #define MSR_IA32_MC0_MISC 0x00000403 354b72e7464SBorislav Petkov 355b72e7464SBorislav Petkov /* C-state Residency Counters */ 356b72e7464SBorislav Petkov #define MSR_PKG_C3_RESIDENCY 0x000003f8 357b72e7464SBorislav Petkov #define MSR_PKG_C6_RESIDENCY 0x000003f9 3580539ba11SLen Brown #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 359b72e7464SBorislav Petkov #define MSR_PKG_C7_RESIDENCY 0x000003fa 360b72e7464SBorislav Petkov #define MSR_CORE_C3_RESIDENCY 0x000003fc 361b72e7464SBorislav Petkov #define MSR_CORE_C6_RESIDENCY 0x000003fd 362b72e7464SBorislav Petkov #define MSR_CORE_C7_RESIDENCY 0x000003fe 363b72e7464SBorislav Petkov #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 364b72e7464SBorislav Petkov #define MSR_PKG_C2_RESIDENCY 0x0000060d 365b72e7464SBorislav Petkov #define MSR_PKG_C8_RESIDENCY 0x00000630 366b72e7464SBorislav Petkov #define MSR_PKG_C9_RESIDENCY 0x00000631 367b72e7464SBorislav Petkov #define MSR_PKG_C10_RESIDENCY 0x00000632 368b72e7464SBorislav Petkov 3695a63426eSLen Brown /* Interrupt Response Limit */ 3705a63426eSLen Brown #define MSR_PKGC3_IRTL 0x0000060a 3715a63426eSLen Brown #define MSR_PKGC6_IRTL 0x0000060b 3725a63426eSLen Brown #define MSR_PKGC7_IRTL 0x0000060c 3735a63426eSLen Brown #define MSR_PKGC8_IRTL 0x00000633 3745a63426eSLen Brown #define MSR_PKGC9_IRTL 0x00000634 3755a63426eSLen Brown #define MSR_PKGC10_IRTL 0x00000635 3765a63426eSLen Brown 377b72e7464SBorislav Petkov /* Run Time Average Power Limiting (RAPL) Interface */ 378b72e7464SBorislav Petkov 379f52ba931SSumeet Pawnikar #define MSR_VR_CURRENT_CONFIG 0x00000601 380b72e7464SBorislav Petkov #define MSR_RAPL_POWER_UNIT 0x00000606 381b72e7464SBorislav Petkov 382b72e7464SBorislav Petkov #define MSR_PKG_POWER_LIMIT 0x00000610 383b72e7464SBorislav Petkov #define MSR_PKG_ENERGY_STATUS 0x00000611 384b72e7464SBorislav Petkov #define MSR_PKG_PERF_STATUS 0x00000613 385b72e7464SBorislav Petkov #define MSR_PKG_POWER_INFO 0x00000614 386b72e7464SBorislav Petkov 387b72e7464SBorislav Petkov #define MSR_DRAM_POWER_LIMIT 0x00000618 388b72e7464SBorislav Petkov #define MSR_DRAM_ENERGY_STATUS 0x00000619 389b72e7464SBorislav Petkov #define MSR_DRAM_PERF_STATUS 0x0000061b 390b72e7464SBorislav Petkov #define MSR_DRAM_POWER_INFO 0x0000061c 391b72e7464SBorislav Petkov 392b72e7464SBorislav Petkov #define MSR_PP0_POWER_LIMIT 0x00000638 393b72e7464SBorislav Petkov #define MSR_PP0_ENERGY_STATUS 0x00000639 394b72e7464SBorislav Petkov #define MSR_PP0_POLICY 0x0000063a 395b72e7464SBorislav Petkov #define MSR_PP0_PERF_STATUS 0x0000063b 396b72e7464SBorislav Petkov 397b72e7464SBorislav Petkov #define MSR_PP1_POWER_LIMIT 0x00000640 398b72e7464SBorislav Petkov #define MSR_PP1_ENERGY_STATUS 0x00000641 399b72e7464SBorislav Petkov #define MSR_PP1_POLICY 0x00000642 400b72e7464SBorislav Petkov 4015cde2653SStephane Eranian #define MSR_AMD_RAPL_POWER_UNIT 0xc0010299 40243756a29SVictor Ding #define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a 403298ed2b3SVictor Ding #define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b 4045cde2653SStephane Eranian 4054a6772f5SVladimir Zapolskiy /* Config TDP MSRs */ 40682bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_NOMINAL 0x00000648 40782bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 40882bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 40982bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_CONTROL 0x0000064B 41082bb70c5SRafael J. Wysocki #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 41182bb70c5SRafael J. Wysocki 412dcee75b3SSrinivas Pandruvada #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 4134af184eeSLen Brown #define MSR_SECONDARY_TURBO_RATIO_LIMIT 0x00000650 414dcee75b3SSrinivas Pandruvada 415b72e7464SBorislav Petkov #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 416b72e7464SBorislav Petkov #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 417b72e7464SBorislav Petkov #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 418b72e7464SBorislav Petkov #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 419b72e7464SBorislav Petkov 420b72e7464SBorislav Petkov #define MSR_CORE_C1_RES 0x00000660 4210539ba11SLen Brown #define MSR_MODULE_C6_RES_MS 0x00000664 422b72e7464SBorislav Petkov 423b72e7464SBorislav Petkov #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 424b72e7464SBorislav Petkov #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 425b72e7464SBorislav Petkov 4268a34fd02SLen Brown #define MSR_ATOM_CORE_RATIOS 0x0000066a 4278a34fd02SLen Brown #define MSR_ATOM_CORE_VIDS 0x0000066b 4288a34fd02SLen Brown #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 4298a34fd02SLen Brown #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 4308a34fd02SLen Brown 431b72e7464SBorislav Petkov #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 432b72e7464SBorislav Petkov #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 433b72e7464SBorislav Petkov #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 434b72e7464SBorislav Petkov 435991625f3SPeter Zijlstra /* Control-flow Enforcement Technology MSRs */ 436991625f3SPeter Zijlstra #define MSR_IA32_U_CET 0x000006a0 /* user mode cet */ 437991625f3SPeter Zijlstra #define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */ 438991625f3SPeter Zijlstra #define CET_SHSTK_EN BIT_ULL(0) 439991625f3SPeter Zijlstra #define CET_WRSS_EN BIT_ULL(1) 440991625f3SPeter Zijlstra #define CET_ENDBR_EN BIT_ULL(2) 441991625f3SPeter Zijlstra #define CET_LEG_IW_EN BIT_ULL(3) 442991625f3SPeter Zijlstra #define CET_NO_TRACK_EN BIT_ULL(4) 443991625f3SPeter Zijlstra #define CET_SUPPRESS_DISABLE BIT_ULL(5) 444991625f3SPeter Zijlstra #define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9)) 445991625f3SPeter Zijlstra #define CET_SUPPRESS BIT_ULL(10) 446991625f3SPeter Zijlstra #define CET_WAIT_ENDBR BIT_ULL(11) 447991625f3SPeter Zijlstra 448991625f3SPeter Zijlstra #define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */ 449991625f3SPeter Zijlstra #define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */ 450991625f3SPeter Zijlstra #define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */ 451991625f3SPeter Zijlstra #define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */ 452991625f3SPeter Zijlstra #define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */ 453991625f3SPeter Zijlstra 454b72e7464SBorislav Petkov /* Hardware P state interface */ 455b72e7464SBorislav Petkov #define MSR_PPERF 0x0000064e 456b72e7464SBorislav Petkov #define MSR_PERF_LIMIT_REASONS 0x0000064f 457b72e7464SBorislav Petkov #define MSR_PM_ENABLE 0x00000770 458b72e7464SBorislav Petkov #define MSR_HWP_CAPABILITIES 0x00000771 459b72e7464SBorislav Petkov #define MSR_HWP_REQUEST_PKG 0x00000772 460b72e7464SBorislav Petkov #define MSR_HWP_INTERRUPT 0x00000773 461b72e7464SBorislav Petkov #define MSR_HWP_REQUEST 0x00000774 462b72e7464SBorislav Petkov #define MSR_HWP_STATUS 0x00000777 463b72e7464SBorislav Petkov 464b72e7464SBorislav Petkov /* CPUID.6.EAX */ 465b72e7464SBorislav Petkov #define HWP_BASE_BIT (1<<7) 466b72e7464SBorislav Petkov #define HWP_NOTIFICATIONS_BIT (1<<8) 467b72e7464SBorislav Petkov #define HWP_ACTIVITY_WINDOW_BIT (1<<9) 468b72e7464SBorislav Petkov #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 469b72e7464SBorislav Petkov #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 470b72e7464SBorislav Petkov 471b72e7464SBorislav Petkov /* IA32_HWP_CAPABILITIES */ 472670e27d8SLen Brown #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 473670e27d8SLen Brown #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 474670e27d8SLen Brown #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 475670e27d8SLen Brown #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 476b72e7464SBorislav Petkov 477b72e7464SBorislav Petkov /* IA32_HWP_REQUEST */ 478b72e7464SBorislav Petkov #define HWP_MIN_PERF(x) (x & 0xff) 479b72e7464SBorislav Petkov #define HWP_MAX_PERF(x) ((x & 0xff) << 8) 480b72e7464SBorislav Petkov #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 4812fc49cb0SLen Brown #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) 4828d84e906SLen Brown #define HWP_EPP_PERFORMANCE 0x00 4838d84e906SLen Brown #define HWP_EPP_BALANCE_PERFORMANCE 0x80 4848d84e906SLen Brown #define HWP_EPP_BALANCE_POWERSAVE 0xC0 4858d84e906SLen Brown #define HWP_EPP_POWERSAVE 0xFF 4862fc49cb0SLen Brown #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) 4872fc49cb0SLen Brown #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) 488b72e7464SBorislav Petkov 489b72e7464SBorislav Petkov /* IA32_HWP_STATUS */ 490b72e7464SBorislav Petkov #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 491b72e7464SBorislav Petkov #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 492b72e7464SBorislav Petkov 493b72e7464SBorislav Petkov /* IA32_HWP_INTERRUPT */ 494b72e7464SBorislav Petkov #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 495b72e7464SBorislav Petkov #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 496b72e7464SBorislav Petkov 497b72e7464SBorislav Petkov #define MSR_AMD64_MC0_MASK 0xc0010044 498b72e7464SBorislav Petkov 499b72e7464SBorislav Petkov #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 500b72e7464SBorislav Petkov #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 501b72e7464SBorislav Petkov #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 502b72e7464SBorislav Petkov #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 503b72e7464SBorislav Petkov 504b72e7464SBorislav Petkov #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 505b72e7464SBorislav Petkov 506b72e7464SBorislav Petkov /* These are consecutive and not in the normal 4er MCE bank block */ 507b72e7464SBorislav Petkov #define MSR_IA32_MC0_CTL2 0x00000280 508b72e7464SBorislav Petkov #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 509b72e7464SBorislav Petkov 510b72e7464SBorislav Petkov #define MSR_P6_PERFCTR0 0x000000c1 511b72e7464SBorislav Petkov #define MSR_P6_PERFCTR1 0x000000c2 512b72e7464SBorislav Petkov #define MSR_P6_EVNTSEL0 0x00000186 513b72e7464SBorislav Petkov #define MSR_P6_EVNTSEL1 0x00000187 514b72e7464SBorislav Petkov 515b72e7464SBorislav Petkov #define MSR_KNC_PERFCTR0 0x00000020 516b72e7464SBorislav Petkov #define MSR_KNC_PERFCTR1 0x00000021 517b72e7464SBorislav Petkov #define MSR_KNC_EVNTSEL0 0x00000028 518b72e7464SBorislav Petkov #define MSR_KNC_EVNTSEL1 0x00000029 519b72e7464SBorislav Petkov 520b72e7464SBorislav Petkov /* Alternative perfctr range with full access. */ 521b72e7464SBorislav Petkov #define MSR_IA32_PMC0 0x000004c1 522b72e7464SBorislav Petkov 52342880f72SAlexander Shishkin /* Auto-reload via MSR instead of DS area */ 52442880f72SAlexander Shishkin #define MSR_RELOAD_PMC0 0x000014c1 52542880f72SAlexander Shishkin #define MSR_RELOAD_FIXED_CTR0 0x00001309 52642880f72SAlexander Shishkin 527342061c5SBorislav Petkov /* 528342061c5SBorislav Petkov * AMD64 MSRs. Not complete. See the architecture manual for a more 529342061c5SBorislav Petkov * complete list. 530342061c5SBorislav Petkov */ 531b72e7464SBorislav Petkov #define MSR_AMD64_PATCH_LEVEL 0x0000008b 532b72e7464SBorislav Petkov #define MSR_AMD64_TSC_RATIO 0xc0000104 533b72e7464SBorislav Petkov #define MSR_AMD64_NB_CFG 0xc001001f 534b72e7464SBorislav Petkov #define MSR_AMD64_PATCH_LOADER 0xc0010020 535342061c5SBorislav Petkov #define MSR_AMD_PERF_CTL 0xc0010062 536342061c5SBorislav Petkov #define MSR_AMD_PERF_STATUS 0xc0010063 537342061c5SBorislav Petkov #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 538b72e7464SBorislav Petkov #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 539b72e7464SBorislav Petkov #define MSR_AMD64_OSVW_STATUS 0xc0010141 5404e3f77d8SJan Beulich #define MSR_AMD_PPIN_CTL 0xc00102f0 5414e3f77d8SJan Beulich #define MSR_AMD_PPIN 0xc00102f1 5421068ed45SBorislav Petkov #define MSR_AMD64_CPUID_FN_1 0xc0011004 543b72e7464SBorislav Petkov #define MSR_AMD64_LS_CFG 0xc0011020 544b72e7464SBorislav Petkov #define MSR_AMD64_DC_CFG 0xc0011022 5452632daebSBorislav Petkov 5462632daebSBorislav Petkov #define MSR_AMD64_DE_CFG 0xc0011029 5472632daebSBorislav Petkov #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1 5482632daebSBorislav Petkov #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT) 5492632daebSBorislav Petkov 550b72e7464SBorislav Petkov #define MSR_AMD64_BU_CFG2 0xc001102a 551b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCHCTL 0xc0011030 552b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 553b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 554b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCH_REG_COUNT 3 555b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 556b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPCTL 0xc0011033 557b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPRIP 0xc0011034 558b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA 0xc0011035 559b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA2 0xc0011036 560b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA3 0xc0011037 561b72e7464SBorislav Petkov #define MSR_AMD64_IBSDCLINAD 0xc0011038 562b72e7464SBorislav Petkov #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 563b72e7464SBorislav Petkov #define MSR_AMD64_IBSOP_REG_COUNT 7 564b72e7464SBorislav Petkov #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 565b72e7464SBorislav Petkov #define MSR_AMD64_IBSCTL 0xc001103a 566b72e7464SBorislav Petkov #define MSR_AMD64_IBSBRTARGET 0xc001103b 56736e1be8aSKim Phillips #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c 568b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA4 0xc001103d 569b72e7464SBorislav Petkov #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 57039150352SMaxim Levitsky #define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b 57169372cf0STom Lendacky #define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e 57229dcc60fSJoerg Roedel #define MSR_AMD64_SEV_ES_GHCB 0xc0010130 5731958b5fcSTom Lendacky #define MSR_AMD64_SEV 0xc0010131 5741958b5fcSTom Lendacky #define MSR_AMD64_SEV_ENABLED_BIT 0 575b57de6cdSJoerg Roedel #define MSR_AMD64_SEV_ES_ENABLED_BIT 1 576f742b90eSBrijesh Singh #define MSR_AMD64_SEV_SNP_ENABLED_BIT 2 5771958b5fcSTom Lendacky #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) 578b57de6cdSJoerg Roedel #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) 579f742b90eSBrijesh Singh #define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) 580b72e7464SBorislav Petkov 5818c29f016SNikunj A Dadhania /* SNP feature bits enabled by the hypervisor */ 5828c29f016SNikunj A Dadhania #define MSR_AMD64_SNP_VTOM BIT_ULL(3) 5838c29f016SNikunj A Dadhania #define MSR_AMD64_SNP_REFLECT_VC BIT_ULL(4) 5848c29f016SNikunj A Dadhania #define MSR_AMD64_SNP_RESTRICTED_INJ BIT_ULL(5) 5858c29f016SNikunj A Dadhania #define MSR_AMD64_SNP_ALT_INJ BIT_ULL(6) 5868c29f016SNikunj A Dadhania #define MSR_AMD64_SNP_DEBUG_SWAP BIT_ULL(7) 5878c29f016SNikunj A Dadhania #define MSR_AMD64_SNP_PREVENT_HOST_IBS BIT_ULL(8) 5888c29f016SNikunj A Dadhania #define MSR_AMD64_SNP_BTB_ISOLATION BIT_ULL(9) 5898c29f016SNikunj A Dadhania #define MSR_AMD64_SNP_VMPL_SSS BIT_ULL(10) 5908c29f016SNikunj A Dadhania #define MSR_AMD64_SNP_SECURE_TSC BIT_ULL(11) 5918c29f016SNikunj A Dadhania #define MSR_AMD64_SNP_VMGEXIT_PARAM BIT_ULL(12) 5928c29f016SNikunj A Dadhania #define MSR_AMD64_SNP_IBS_VIRT BIT_ULL(14) 5938c29f016SNikunj A Dadhania #define MSR_AMD64_SNP_VMSA_REG_PROTECTION BIT_ULL(16) 5948c29f016SNikunj A Dadhania #define MSR_AMD64_SNP_SMT_PROTECTION BIT_ULL(17) 5958c29f016SNikunj A Dadhania 5968c29f016SNikunj A Dadhania /* SNP feature bits reserved for future use. */ 5978c29f016SNikunj A Dadhania #define MSR_AMD64_SNP_RESERVED_BIT13 BIT_ULL(13) 5988c29f016SNikunj A Dadhania #define MSR_AMD64_SNP_RESERVED_BIT15 BIT_ULL(15) 5998c29f016SNikunj A Dadhania #define MSR_AMD64_SNP_RESERVED_MASK GENMASK_ULL(63, 18) 6008c29f016SNikunj A Dadhania 60111fb0683STom Lendacky #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f 60211fb0683STom Lendacky 60389aa94b4SHuang Rui /* AMD Collaborative Processor Performance Control MSRs */ 60489aa94b4SHuang Rui #define MSR_AMD_CPPC_CAP1 0xc00102b0 60589aa94b4SHuang Rui #define MSR_AMD_CPPC_ENABLE 0xc00102b1 60689aa94b4SHuang Rui #define MSR_AMD_CPPC_CAP2 0xc00102b2 60789aa94b4SHuang Rui #define MSR_AMD_CPPC_REQ 0xc00102b3 60889aa94b4SHuang Rui #define MSR_AMD_CPPC_STATUS 0xc00102b4 60989aa94b4SHuang Rui 61089aa94b4SHuang Rui #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) 61189aa94b4SHuang Rui #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) 61289aa94b4SHuang Rui #define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff) 61389aa94b4SHuang Rui #define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff) 61489aa94b4SHuang Rui 61589aa94b4SHuang Rui #define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0) 61689aa94b4SHuang Rui #define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) 61789aa94b4SHuang Rui #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) 61889aa94b4SHuang Rui #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) 61989aa94b4SHuang Rui 620089be16dSSandipan Das /* AMD Performance Counter Global Status and Control MSRs */ 621089be16dSSandipan Das #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 622089be16dSSandipan Das #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 623089be16dSSandipan Das #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 624089be16dSSandipan Das 625ca5b7c0dSSandipan Das /* AMD Last Branch Record MSRs */ 626ca5b7c0dSSandipan Das #define MSR_AMD64_LBR_SELECT 0xc000010e 627ca5b7c0dSSandipan Das 628aaf24884SHuang Rui /* Fam 17h MSRs */ 629aaf24884SHuang Rui #define MSR_F17H_IRPERF 0xc00000e9 630aaf24884SHuang Rui 631d7caac99SPeter Zijlstra #define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3 632d7caac99SPeter Zijlstra #define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1) 633d7caac99SPeter Zijlstra 634b72e7464SBorislav Petkov /* Fam 16h MSRs */ 635b72e7464SBorislav Petkov #define MSR_F16H_L2I_PERF_CTL 0xc0010230 636b72e7464SBorislav Petkov #define MSR_F16H_L2I_PERF_CTR 0xc0010231 637b72e7464SBorislav Petkov #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 638b72e7464SBorislav Petkov #define MSR_F16H_DR2_ADDR_MASK 0xc001101a 639b72e7464SBorislav Petkov #define MSR_F16H_DR3_ADDR_MASK 0xc001101b 640b72e7464SBorislav Petkov #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 641b72e7464SBorislav Petkov 642b72e7464SBorislav Petkov /* Fam 15h MSRs */ 64399e40204SBorislav Petkov #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a 64499e40204SBorislav Petkov #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b 645b72e7464SBorislav Petkov #define MSR_F15H_PERF_CTL 0xc0010200 646e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 647e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 648e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 649e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 650e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 651e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 652e84b7119SJanakarajan Natarajan 653b72e7464SBorislav Petkov #define MSR_F15H_PERF_CTR 0xc0010201 654e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 655e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 656e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 657e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 658e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 659e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 660e84b7119SJanakarajan Natarajan 661b72e7464SBorislav Petkov #define MSR_F15H_NB_PERF_CTL 0xc0010240 662b72e7464SBorislav Petkov #define MSR_F15H_NB_PERF_CTR 0xc0010241 6638a224261SHuang Rui #define MSR_F15H_PTSC 0xc0010280 664ae8b7875SBorislav Petkov #define MSR_F15H_IC_CFG 0xc0011021 6650e1b869fSEduardo Habkost #define MSR_F15H_EX_CFG 0xc001102c 666b72e7464SBorislav Petkov 667b72e7464SBorislav Petkov /* Fam 10h MSRs */ 668b72e7464SBorislav Petkov #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 669b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_ENABLE (1<<0) 670b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 671b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 672b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 673b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BASE_SHIFT 20 674b72e7464SBorislav Petkov #define MSR_FAM10H_NODE_ID 0xc001100c 675b72e7464SBorislav Petkov 676b72e7464SBorislav Petkov /* K8 MSRs */ 677b72e7464SBorislav Petkov #define MSR_K8_TOP_MEM1 0xc001001a 678b72e7464SBorislav Petkov #define MSR_K8_TOP_MEM2 0xc001001d 679059e5c32SBrijesh Singh #define MSR_AMD64_SYSCFG 0xc0010010 680059e5c32SBrijesh Singh #define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23 681059e5c32SBrijesh Singh #define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT) 682b72e7464SBorislav Petkov #define MSR_K8_INT_PENDING_MSG 0xc0010055 683b72e7464SBorislav Petkov /* C1E active bits in int pending message */ 684b72e7464SBorislav Petkov #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 685b72e7464SBorislav Petkov #define MSR_K8_TSEG_ADDR 0xc0010112 6863afb1121SPaolo Bonzini #define MSR_K8_TSEG_MASK 0xc0010113 687b72e7464SBorislav Petkov #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 688b72e7464SBorislav Petkov #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 689b72e7464SBorislav Petkov #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 690b72e7464SBorislav Petkov 691b72e7464SBorislav Petkov /* K7 MSRs */ 692b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL0 0xc0010000 693b72e7464SBorislav Petkov #define MSR_K7_PERFCTR0 0xc0010004 694b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL1 0xc0010001 695b72e7464SBorislav Petkov #define MSR_K7_PERFCTR1 0xc0010005 696b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL2 0xc0010002 697b72e7464SBorislav Petkov #define MSR_K7_PERFCTR2 0xc0010006 698b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL3 0xc0010003 699b72e7464SBorislav Petkov #define MSR_K7_PERFCTR3 0xc0010007 700b72e7464SBorislav Petkov #define MSR_K7_CLK_CTL 0xc001001b 701b72e7464SBorislav Petkov #define MSR_K7_HWCR 0xc0010015 70218c71ce9STom Lendacky #define MSR_K7_HWCR_SMMLOCK_BIT 0 70318c71ce9STom Lendacky #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) 70421b5ee59SKim Phillips #define MSR_K7_HWCR_IRPERF_EN_BIT 30 70521b5ee59SKim Phillips #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) 706b72e7464SBorislav Petkov #define MSR_K7_FID_VID_CTL 0xc0010041 707b72e7464SBorislav Petkov #define MSR_K7_FID_VID_STATUS 0xc0010042 708b72e7464SBorislav Petkov 709b72e7464SBorislav Petkov /* K6 MSRs */ 710b72e7464SBorislav Petkov #define MSR_K6_WHCR 0xc0000082 711b72e7464SBorislav Petkov #define MSR_K6_UWCCR 0xc0000085 712b72e7464SBorislav Petkov #define MSR_K6_EPMR 0xc0000086 713b72e7464SBorislav Petkov #define MSR_K6_PSOR 0xc0000087 714b72e7464SBorislav Petkov #define MSR_K6_PFIR 0xc0000088 715b72e7464SBorislav Petkov 716b72e7464SBorislav Petkov /* Centaur-Hauls/IDT defined MSRs. */ 717b72e7464SBorislav Petkov #define MSR_IDT_FCR1 0x00000107 718b72e7464SBorislav Petkov #define MSR_IDT_FCR2 0x00000108 719b72e7464SBorislav Petkov #define MSR_IDT_FCR3 0x00000109 720b72e7464SBorislav Petkov #define MSR_IDT_FCR4 0x0000010a 721b72e7464SBorislav Petkov 722b72e7464SBorislav Petkov #define MSR_IDT_MCR0 0x00000110 723b72e7464SBorislav Petkov #define MSR_IDT_MCR1 0x00000111 724b72e7464SBorislav Petkov #define MSR_IDT_MCR2 0x00000112 725b72e7464SBorislav Petkov #define MSR_IDT_MCR3 0x00000113 726b72e7464SBorislav Petkov #define MSR_IDT_MCR4 0x00000114 727b72e7464SBorislav Petkov #define MSR_IDT_MCR5 0x00000115 728b72e7464SBorislav Petkov #define MSR_IDT_MCR6 0x00000116 729b72e7464SBorislav Petkov #define MSR_IDT_MCR7 0x00000117 730b72e7464SBorislav Petkov #define MSR_IDT_MCR_CTRL 0x00000120 731b72e7464SBorislav Petkov 732b72e7464SBorislav Petkov /* VIA Cyrix defined MSRs*/ 733b72e7464SBorislav Petkov #define MSR_VIA_FCR 0x00001107 734b72e7464SBorislav Petkov #define MSR_VIA_LONGHAUL 0x0000110a 735b72e7464SBorislav Petkov #define MSR_VIA_RNG 0x0000110b 736b72e7464SBorislav Petkov #define MSR_VIA_BCR2 0x00001147 737b72e7464SBorislav Petkov 738b72e7464SBorislav Petkov /* Transmeta defined MSRs */ 739b72e7464SBorislav Petkov #define MSR_TMTA_LONGRUN_CTRL 0x80868010 740b72e7464SBorislav Petkov #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 741b72e7464SBorislav Petkov #define MSR_TMTA_LRTI_READOUT 0x80868018 742b72e7464SBorislav Petkov #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 743b72e7464SBorislav Petkov 744b72e7464SBorislav Petkov /* Intel defined MSRs. */ 745b72e7464SBorislav Petkov #define MSR_IA32_P5_MC_ADDR 0x00000000 746b72e7464SBorislav Petkov #define MSR_IA32_P5_MC_TYPE 0x00000001 747b72e7464SBorislav Petkov #define MSR_IA32_TSC 0x00000010 748b72e7464SBorislav Petkov #define MSR_IA32_PLATFORM_ID 0x00000017 749b72e7464SBorislav Petkov #define MSR_IA32_EBL_CR_POWERON 0x0000002a 750b72e7464SBorislav Petkov #define MSR_EBC_FREQUENCY_ID 0x0000002c 751b72e7464SBorislav Petkov #define MSR_SMI_COUNT 0x00000034 75232ad73dbSSean Christopherson 75332ad73dbSSean Christopherson /* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */ 75432ad73dbSSean Christopherson #define MSR_IA32_FEAT_CTL 0x0000003a 75532ad73dbSSean Christopherson #define FEAT_CTL_LOCKED BIT(0) 75632ad73dbSSean Christopherson #define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1) 75732ad73dbSSean Christopherson #define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2) 758d205e0f1SSean Christopherson #define FEAT_CTL_SGX_LC_ENABLED BIT(17) 759e7b6385bSSean Christopherson #define FEAT_CTL_SGX_ENABLED BIT(18) 76032ad73dbSSean Christopherson #define FEAT_CTL_LMCE_ENABLED BIT(20) 76132ad73dbSSean Christopherson 762b72e7464SBorislav Petkov #define MSR_IA32_TSC_ADJUST 0x0000003b 763b72e7464SBorislav Petkov #define MSR_IA32_BNDCFGS 0x00000d90 764b72e7464SBorislav Petkov 7654531662dSJim Mattson #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 7664531662dSJim Mattson 767dae1bd58SChang S. Bae #define MSR_IA32_XFD 0x000001c4 768dae1bd58SChang S. Bae #define MSR_IA32_XFD_ERR 0x000001c5 769b72e7464SBorislav Petkov #define MSR_IA32_XSS 0x00000da0 770b72e7464SBorislav Petkov 771b72e7464SBorislav Petkov #define MSR_IA32_APICBASE 0x0000001b 772b72e7464SBorislav Petkov #define MSR_IA32_APICBASE_BSP (1<<8) 773b72e7464SBorislav Petkov #define MSR_IA32_APICBASE_ENABLE (1<<11) 774b72e7464SBorislav Petkov #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 775b72e7464SBorislav Petkov 776b72e7464SBorislav Petkov #define MSR_IA32_UCODE_WRITE 0x00000079 777b72e7464SBorislav Petkov #define MSR_IA32_UCODE_REV 0x0000008b 778b72e7464SBorislav Petkov 779d205e0f1SSean Christopherson /* Intel SGX Launch Enclave Public Key Hash MSRs */ 780d205e0f1SSean Christopherson #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C 781d205e0f1SSean Christopherson #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D 782d205e0f1SSean Christopherson #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E 783d205e0f1SSean Christopherson #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F 784d205e0f1SSean Christopherson 785b72e7464SBorislav Petkov #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 786b72e7464SBorislav Petkov #define MSR_IA32_SMBASE 0x0000009e 787b72e7464SBorislav Petkov 788b72e7464SBorislav Petkov #define MSR_IA32_PERF_STATUS 0x00000198 789b72e7464SBorislav Petkov #define MSR_IA32_PERF_CTL 0x00000199 790b72e7464SBorislav Petkov #define INTEL_PERF_CTL_MASK 0xffff 791b72e7464SBorislav Petkov 792ada54345SStephane Eranian /* AMD Branch Sampling configuration */ 793ada54345SStephane Eranian #define MSR_AMD_DBG_EXTN_CFG 0xc000010f 794ada54345SStephane Eranian #define MSR_AMD_SAMP_BR_FROM 0xc0010300 795ada54345SStephane Eranian 796ca5b7c0dSSandipan Das #define DBG_EXTN_CFG_LBRV2EN BIT_ULL(6) 797ca5b7c0dSSandipan Das 798b72e7464SBorislav Petkov #define MSR_IA32_MPERF 0x000000e7 799b72e7464SBorislav Petkov #define MSR_IA32_APERF 0x000000e8 800b72e7464SBorislav Petkov 801b72e7464SBorislav Petkov #define MSR_IA32_THERM_CONTROL 0x0000019a 802b72e7464SBorislav Petkov #define MSR_IA32_THERM_INTERRUPT 0x0000019b 803b72e7464SBorislav Petkov 804b72e7464SBorislav Petkov #define THERM_INT_HIGH_ENABLE (1 << 0) 805b72e7464SBorislav Petkov #define THERM_INT_LOW_ENABLE (1 << 1) 806b72e7464SBorislav Petkov #define THERM_INT_PLN_ENABLE (1 << 24) 807b72e7464SBorislav Petkov 808b72e7464SBorislav Petkov #define MSR_IA32_THERM_STATUS 0x0000019c 809b72e7464SBorislav Petkov 810b72e7464SBorislav Petkov #define THERM_STATUS_PROCHOT (1 << 0) 811b72e7464SBorislav Petkov #define THERM_STATUS_POWER_LIMIT (1 << 10) 812b72e7464SBorislav Petkov 813b72e7464SBorislav Petkov #define MSR_THERM2_CTL 0x0000019d 814b72e7464SBorislav Petkov 815b72e7464SBorislav Petkov #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 816b72e7464SBorislav Petkov 817b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE 0x000001a0 818b72e7464SBorislav Petkov 819b72e7464SBorislav Petkov #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 820b72e7464SBorislav Petkov 82198af7459SLen Brown #define MSR_MISC_FEATURE_CONTROL 0x000001a4 822b72e7464SBorislav Petkov #define MSR_MISC_PWR_MGMT 0x000001aa 823b72e7464SBorislav Petkov 824b72e7464SBorislav Petkov #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 825b72e7464SBorislav Petkov #define ENERGY_PERF_BIAS_PERFORMANCE 0 826d0117a0eSLen Brown #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 827b72e7464SBorislav Petkov #define ENERGY_PERF_BIAS_NORMAL 6 8287420ae3bSSrinivas Pandruvada #define ENERGY_PERF_BIAS_NORMAL_POWERSAVE 7 829d0117a0eSLen Brown #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 830b72e7464SBorislav Petkov #define ENERGY_PERF_BIAS_POWERSAVE 15 831b72e7464SBorislav Petkov 832b72e7464SBorislav Petkov #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 833b72e7464SBorislav Petkov 834b72e7464SBorislav Petkov #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 835b72e7464SBorislav Petkov #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 8367b8f40b3SRicardo Neri #define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26) 837b72e7464SBorislav Petkov 838b72e7464SBorislav Petkov #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 839b72e7464SBorislav Petkov 840b72e7464SBorislav Petkov #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 841b72e7464SBorislav Petkov #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 842b72e7464SBorislav Petkov #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 8437b8f40b3SRicardo Neri #define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25) 844b72e7464SBorislav Petkov 845b72e7464SBorislav Petkov /* Thermal Thresholds Support */ 846b72e7464SBorislav Petkov #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 847b72e7464SBorislav Petkov #define THERM_SHIFT_THRESHOLD0 8 848b72e7464SBorislav Petkov #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 849b72e7464SBorislav Petkov #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 850b72e7464SBorislav Petkov #define THERM_SHIFT_THRESHOLD1 16 851b72e7464SBorislav Petkov #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 852b72e7464SBorislav Petkov #define THERM_STATUS_THRESHOLD0 (1 << 6) 853b72e7464SBorislav Petkov #define THERM_LOG_THRESHOLD0 (1 << 7) 854b72e7464SBorislav Petkov #define THERM_STATUS_THRESHOLD1 (1 << 8) 855b72e7464SBorislav Petkov #define THERM_LOG_THRESHOLD1 (1 << 9) 856b72e7464SBorislav Petkov 857b72e7464SBorislav Petkov /* MISC_ENABLE bits: architectural */ 858b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 859b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 860b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 861b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 862b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 863b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 864b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 865b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 866b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 867b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 868b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 869b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 870b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 871b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 872b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 873b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 874b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 875b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 876b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 877b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 878b72e7464SBorislav Petkov 879b72e7464SBorislav Petkov /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 880b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 881b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 882b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 883b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 884b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 885b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 886b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 887b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 888b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 889b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 890b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 891b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 892b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 893b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 894b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 895b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 896b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 897b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 898b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 899b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 900b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 901b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 902b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 903b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 904b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 905b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 906b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 907b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 908b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 909b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 910b72e7464SBorislav Petkov 911ab6d9468SKyle Huey /* MISC_FEATURES_ENABLES non-architectural features */ 912ab6d9468SKyle Huey #define MSR_MISC_FEATURES_ENABLES 0x00000140 913ae47eda9SGrzegorz Andrejczuk 914e9ea1e7fSKyle Huey #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 915e9ea1e7fSKyle Huey #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) 916ab6d9468SKyle Huey #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 917ae47eda9SGrzegorz Andrejczuk 918b72e7464SBorislav Petkov #define MSR_IA32_TSC_DEADLINE 0x000006E0 919b72e7464SBorislav Petkov 92052f64909SPeter Zijlstra (Intel) 92152f64909SPeter Zijlstra (Intel) #define MSR_TSX_FORCE_ABORT 0x0000010F 92252f64909SPeter Zijlstra (Intel) 92352f64909SPeter Zijlstra (Intel) #define MSR_TFA_RTM_FORCE_ABORT_BIT 0 92452f64909SPeter Zijlstra (Intel) #define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) 9251348924bSPawan Gupta #define MSR_TFA_TSX_CPUID_CLEAR_BIT 1 9261348924bSPawan Gupta #define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT) 9271348924bSPawan Gupta #define MSR_TFA_SDV_ENABLE_RTM_BIT 2 9281348924bSPawan Gupta #define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT) 92952f64909SPeter Zijlstra (Intel) 930b72e7464SBorislav Petkov /* P4/Xeon+ specific */ 931b72e7464SBorislav Petkov #define MSR_IA32_MCG_EAX 0x00000180 932b72e7464SBorislav Petkov #define MSR_IA32_MCG_EBX 0x00000181 933b72e7464SBorislav Petkov #define MSR_IA32_MCG_ECX 0x00000182 934b72e7464SBorislav Petkov #define MSR_IA32_MCG_EDX 0x00000183 935b72e7464SBorislav Petkov #define MSR_IA32_MCG_ESI 0x00000184 936b72e7464SBorislav Petkov #define MSR_IA32_MCG_EDI 0x00000185 937b72e7464SBorislav Petkov #define MSR_IA32_MCG_EBP 0x00000186 938b72e7464SBorislav Petkov #define MSR_IA32_MCG_ESP 0x00000187 939b72e7464SBorislav Petkov #define MSR_IA32_MCG_EFLAGS 0x00000188 940b72e7464SBorislav Petkov #define MSR_IA32_MCG_EIP 0x00000189 941b72e7464SBorislav Petkov #define MSR_IA32_MCG_RESERVED 0x0000018a 942b72e7464SBorislav Petkov 943b72e7464SBorislav Petkov /* Pentium IV performance counter MSRs */ 944b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR0 0x00000300 945b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR1 0x00000301 946b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR2 0x00000302 947b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR3 0x00000303 948b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR0 0x00000304 949b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR1 0x00000305 950b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR2 0x00000306 951b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR3 0x00000307 952b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR0 0x00000308 953b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR1 0x00000309 954b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR2 0x0000030a 955b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR3 0x0000030b 956b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR0 0x0000030c 957b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR1 0x0000030d 958b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR2 0x0000030e 959b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR3 0x0000030f 960b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR4 0x00000310 961b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR5 0x00000311 962b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR0 0x00000360 963b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR1 0x00000361 964b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR2 0x00000362 965b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR3 0x00000363 966b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR0 0x00000364 967b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR1 0x00000365 968b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR2 0x00000366 969b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR3 0x00000367 970b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR0 0x00000368 971b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR1 0x00000369 972b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR2 0x0000036a 973b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR3 0x0000036b 974b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR0 0x0000036c 975b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR1 0x0000036d 976b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR2 0x0000036e 977b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR3 0x0000036f 978b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR4 0x00000370 979b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR5 0x00000371 980b72e7464SBorislav Petkov #define MSR_P4_ALF_ESCR0 0x000003ca 981b72e7464SBorislav Petkov #define MSR_P4_ALF_ESCR1 0x000003cb 982b72e7464SBorislav Petkov #define MSR_P4_BPU_ESCR0 0x000003b2 983b72e7464SBorislav Petkov #define MSR_P4_BPU_ESCR1 0x000003b3 984b72e7464SBorislav Petkov #define MSR_P4_BSU_ESCR0 0x000003a0 985b72e7464SBorislav Petkov #define MSR_P4_BSU_ESCR1 0x000003a1 986b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR0 0x000003b8 987b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR1 0x000003b9 988b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR2 0x000003cc 989b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR3 0x000003cd 990b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR4 0x000003e0 991b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR5 0x000003e1 992b72e7464SBorislav Petkov #define MSR_P4_DAC_ESCR0 0x000003a8 993b72e7464SBorislav Petkov #define MSR_P4_DAC_ESCR1 0x000003a9 994b72e7464SBorislav Petkov #define MSR_P4_FIRM_ESCR0 0x000003a4 995b72e7464SBorislav Petkov #define MSR_P4_FIRM_ESCR1 0x000003a5 996b72e7464SBorislav Petkov #define MSR_P4_FLAME_ESCR0 0x000003a6 997b72e7464SBorislav Petkov #define MSR_P4_FLAME_ESCR1 0x000003a7 998b72e7464SBorislav Petkov #define MSR_P4_FSB_ESCR0 0x000003a2 999b72e7464SBorislav Petkov #define MSR_P4_FSB_ESCR1 0x000003a3 1000b72e7464SBorislav Petkov #define MSR_P4_IQ_ESCR0 0x000003ba 1001b72e7464SBorislav Petkov #define MSR_P4_IQ_ESCR1 0x000003bb 1002b72e7464SBorislav Petkov #define MSR_P4_IS_ESCR0 0x000003b4 1003b72e7464SBorislav Petkov #define MSR_P4_IS_ESCR1 0x000003b5 1004b72e7464SBorislav Petkov #define MSR_P4_ITLB_ESCR0 0x000003b6 1005b72e7464SBorislav Petkov #define MSR_P4_ITLB_ESCR1 0x000003b7 1006b72e7464SBorislav Petkov #define MSR_P4_IX_ESCR0 0x000003c8 1007b72e7464SBorislav Petkov #define MSR_P4_IX_ESCR1 0x000003c9 1008b72e7464SBorislav Petkov #define MSR_P4_MOB_ESCR0 0x000003aa 1009b72e7464SBorislav Petkov #define MSR_P4_MOB_ESCR1 0x000003ab 1010b72e7464SBorislav Petkov #define MSR_P4_MS_ESCR0 0x000003c0 1011b72e7464SBorislav Petkov #define MSR_P4_MS_ESCR1 0x000003c1 1012b72e7464SBorislav Petkov #define MSR_P4_PMH_ESCR0 0x000003ac 1013b72e7464SBorislav Petkov #define MSR_P4_PMH_ESCR1 0x000003ad 1014b72e7464SBorislav Petkov #define MSR_P4_RAT_ESCR0 0x000003bc 1015b72e7464SBorislav Petkov #define MSR_P4_RAT_ESCR1 0x000003bd 1016b72e7464SBorislav Petkov #define MSR_P4_SAAT_ESCR0 0x000003ae 1017b72e7464SBorislav Petkov #define MSR_P4_SAAT_ESCR1 0x000003af 1018b72e7464SBorislav Petkov #define MSR_P4_SSU_ESCR0 0x000003be 1019b72e7464SBorislav Petkov #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 1020b72e7464SBorislav Petkov 1021b72e7464SBorislav Petkov #define MSR_P4_TBPU_ESCR0 0x000003c2 1022b72e7464SBorislav Petkov #define MSR_P4_TBPU_ESCR1 0x000003c3 1023b72e7464SBorislav Petkov #define MSR_P4_TC_ESCR0 0x000003c4 1024b72e7464SBorislav Petkov #define MSR_P4_TC_ESCR1 0x000003c5 1025b72e7464SBorislav Petkov #define MSR_P4_U2L_ESCR0 0x000003b0 1026b72e7464SBorislav Petkov #define MSR_P4_U2L_ESCR1 0x000003b1 1027b72e7464SBorislav Petkov 1028b72e7464SBorislav Petkov #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 1029b72e7464SBorislav Petkov 1030b72e7464SBorislav Petkov /* Intel Core-based CPU performance counters */ 1031b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 1032b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 1033b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 10347b2c05a1SKan Liang #define MSR_CORE_PERF_FIXED_CTR3 0x0000030c 1035b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 1036b72e7464SBorislav Petkov #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 1037b72e7464SBorislav Petkov #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 1038b72e7464SBorislav Petkov #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 1039b72e7464SBorislav Petkov 104059a854e2SKan Liang #define MSR_PERF_METRICS 0x00000329 104159a854e2SKan Liang 10428479e04eSLuwei Kang /* PERF_GLOBAL_OVF_CTL bits */ 10438479e04eSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55 10448479e04eSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT) 1045c715eb9fSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62 1046c715eb9fSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT) 1047c715eb9fSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 1048c715eb9fSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) 10498479e04eSLuwei Kang 1050b72e7464SBorislav Petkov /* Geode defined MSRs */ 1051b72e7464SBorislav Petkov #define MSR_GEODE_BUSCONT_CONF0 0x00001900 1052b72e7464SBorislav Petkov 1053b72e7464SBorislav Petkov /* Intel VT MSRs */ 1054b72e7464SBorislav Petkov #define MSR_IA32_VMX_BASIC 0x00000480 1055b72e7464SBorislav Petkov #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 1056b72e7464SBorislav Petkov #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 1057b72e7464SBorislav Petkov #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 1058b72e7464SBorislav Petkov #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 1059b72e7464SBorislav Petkov #define MSR_IA32_VMX_MISC 0x00000485 1060b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 1061b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 1062b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 1063b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 1064b72e7464SBorislav Petkov #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 1065b72e7464SBorislav Petkov #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 1066b72e7464SBorislav Petkov #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 1067b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 1068b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 1069b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 1070b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 1071b72e7464SBorislav Petkov #define MSR_IA32_VMX_VMFUNC 0x00000491 1072465932dbSRobert Hoo #define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492 1073b72e7464SBorislav Petkov 1074b72e7464SBorislav Petkov /* VMX_BASIC bits and bitmasks */ 1075b72e7464SBorislav Petkov #define VMX_BASIC_VMCS_SIZE_SHIFT 32 1076b72e7464SBorislav Petkov #define VMX_BASIC_TRUE_CTLS (1ULL << 55) 1077b72e7464SBorislav Petkov #define VMX_BASIC_64 0x0001000000000000LLU 1078b72e7464SBorislav Petkov #define VMX_BASIC_MEM_TYPE_SHIFT 50 1079b72e7464SBorislav Petkov #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 1080b72e7464SBorislav Petkov #define VMX_BASIC_MEM_TYPE_WB 6LLU 1081b72e7464SBorislav Petkov #define VMX_BASIC_INOUT 0x0040000000000000LLU 1082b72e7464SBorislav Petkov 108397fa21f6SBorislav Petkov /* Resctrl MSRs: */ 108497fa21f6SBorislav Petkov /* - Intel: */ 108597fa21f6SBorislav Petkov #define MSR_IA32_L3_QOS_CFG 0xc81 108697fa21f6SBorislav Petkov #define MSR_IA32_L2_QOS_CFG 0xc82 108797fa21f6SBorislav Petkov #define MSR_IA32_QM_EVTSEL 0xc8d 108897fa21f6SBorislav Petkov #define MSR_IA32_QM_CTR 0xc8e 108997fa21f6SBorislav Petkov #define MSR_IA32_PQR_ASSOC 0xc8f 109097fa21f6SBorislav Petkov #define MSR_IA32_L3_CBM_BASE 0xc90 109197fa21f6SBorislav Petkov #define MSR_IA32_L2_CBM_BASE 0xd10 109297fa21f6SBorislav Petkov #define MSR_IA32_MBA_THRTL_BASE 0xd50 109397fa21f6SBorislav Petkov 109497fa21f6SBorislav Petkov /* - AMD: */ 109597fa21f6SBorislav Petkov #define MSR_IA32_MBA_BW_BASE 0xc0000200 10965b6fac3fSBabu Moger #define MSR_IA32_SMBA_BW_BASE 0xc0000280 1097dc2a3e85SBabu Moger #define MSR_IA32_EVT_CFG_BASE 0xc0000400 109897fa21f6SBorislav Petkov 1099b72e7464SBorislav Petkov /* MSR_IA32_VMX_MISC bits */ 1100f99e3dafSChao Peng #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) 1101b72e7464SBorislav Petkov #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 1102b72e7464SBorislav Petkov #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 1103b72e7464SBorislav Petkov /* AMD-V MSRs */ 1104b72e7464SBorislav Petkov 1105b72e7464SBorislav Petkov #define MSR_VM_CR 0xc0010114 1106b72e7464SBorislav Petkov #define MSR_VM_IGNNE 0xc0010115 1107b72e7464SBorislav Petkov #define MSR_VM_HSAVE_PA 0xc0010117 1108b72e7464SBorislav Petkov 11097b8f40b3SRicardo Neri /* Hardware Feedback Interface */ 11107b8f40b3SRicardo Neri #define MSR_IA32_HW_FEEDBACK_PTR 0x17d0 11117b8f40b3SRicardo Neri #define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1 11127b8f40b3SRicardo Neri 1113b8d1d163SDaniel Sneddon /* x2APIC locked status */ 1114b8d1d163SDaniel Sneddon #define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD 1115b8d1d163SDaniel Sneddon #define LEGACY_XAPIC_DISABLED BIT(0) /* 1116b8d1d163SDaniel Sneddon * x2APIC mode is locked and 1117b8d1d163SDaniel Sneddon * disabling x2APIC will cause 1118b8d1d163SDaniel Sneddon * a #GP 1119b8d1d163SDaniel Sneddon */ 1120b8d1d163SDaniel Sneddon 1121b72e7464SBorislav Petkov #endif /* _ASM_X86_MSR_INDEX_H */ 1122