1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2b72e7464SBorislav Petkov #ifndef _ASM_X86_MSR_INDEX_H 3b72e7464SBorislav Petkov #define _ASM_X86_MSR_INDEX_H 4b72e7464SBorislav Petkov 5d8eabc37SThomas Gleixner #include <linux/bits.h> 6d8eabc37SThomas Gleixner 797fa21f6SBorislav Petkov /* CPU model specific register (MSR) numbers. */ 8b72e7464SBorislav Petkov 9b72e7464SBorislav Petkov /* x86-64 specific MSRs */ 10b72e7464SBorislav Petkov #define MSR_EFER 0xc0000080 /* extended feature register */ 11b72e7464SBorislav Petkov #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 12b72e7464SBorislav Petkov #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 13b72e7464SBorislav Petkov #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 14b72e7464SBorislav Petkov #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 15b72e7464SBorislav Petkov #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 16b72e7464SBorislav Petkov #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 17b72e7464SBorislav Petkov #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 18b72e7464SBorislav Petkov #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 19b72e7464SBorislav Petkov 20b72e7464SBorislav Petkov /* EFER bits: */ 21b72e7464SBorislav Petkov #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 22b72e7464SBorislav Petkov #define _EFER_LME 8 /* Long mode enable */ 23b72e7464SBorislav Petkov #define _EFER_LMA 10 /* Long mode active (read-only) */ 24b72e7464SBorislav Petkov #define _EFER_NX 11 /* No execute enable */ 25b72e7464SBorislav Petkov #define _EFER_SVME 12 /* Enable virtualization */ 26b72e7464SBorislav Petkov #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 27b72e7464SBorislav Petkov #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 28b72e7464SBorislav Petkov 29b72e7464SBorislav Petkov #define EFER_SCE (1<<_EFER_SCE) 30b72e7464SBorislav Petkov #define EFER_LME (1<<_EFER_LME) 31b72e7464SBorislav Petkov #define EFER_LMA (1<<_EFER_LMA) 32b72e7464SBorislav Petkov #define EFER_NX (1<<_EFER_NX) 33b72e7464SBorislav Petkov #define EFER_SVME (1<<_EFER_SVME) 34b72e7464SBorislav Petkov #define EFER_LMSLE (1<<_EFER_LMSLE) 35b72e7464SBorislav Petkov #define EFER_FFXSR (1<<_EFER_FFXSR) 36b72e7464SBorislav Petkov 37b72e7464SBorislav Petkov /* Intel MSRs. Some also available on other CPUs */ 383f5a7896STony Luck 396650cdd9SPeter Zijlstra (Intel) #define MSR_TEST_CTRL 0x00000033 406650cdd9SPeter Zijlstra (Intel) #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 416650cdd9SPeter Zijlstra (Intel) #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) 426650cdd9SPeter Zijlstra (Intel) 431e340c60SDavid Woodhouse #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 44d8eabc37SThomas Gleixner #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ 455bfbe3adSTim Chen #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ 46d8eabc37SThomas Gleixner #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ 479f65fb29SKonrad Rzeszutek Wilk #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ 48d8eabc37SThomas Gleixner #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ 494ad3278dSPawan Gupta #define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */ 504ad3278dSPawan Gupta #define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT) 511e340c60SDavid Woodhouse 52*0125acdaSBreno Leitao /* A mask for bits which the kernel toggles when controlling mitigations */ 53*0125acdaSBreno Leitao #define SPEC_CTRL_MITIGATIONS_MASK (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \ 54*0125acdaSBreno Leitao | SPEC_CTRL_RRSBA_DIS_S) 55*0125acdaSBreno Leitao 561e340c60SDavid Woodhouse #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 57d8eabc37SThomas Gleixner #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ 581e340c60SDavid Woodhouse 593f5a7896STony Luck #define MSR_PPIN_CTL 0x0000004e 603f5a7896STony Luck #define MSR_PPIN 0x0000004f 613f5a7896STony Luck 62b72e7464SBorislav Petkov #define MSR_IA32_PERFCTR0 0x000000c1 63b72e7464SBorislav Petkov #define MSR_IA32_PERFCTR1 0x000000c2 64b72e7464SBorislav Petkov #define MSR_FSB_FREQ 0x000000cd 655369a21eSLen Brown #define MSR_PLATFORM_INFO 0x000000ce 6690218ac7SKyle Huey #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 6790218ac7SKyle Huey #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) 68b72e7464SBorislav Petkov 69bd688c69SFenghua Yu #define MSR_IA32_UMWAIT_CONTROL 0xe1 70bd688c69SFenghua Yu #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0) 71bd688c69SFenghua Yu #define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1) 72bd688c69SFenghua Yu /* 73bd688c69SFenghua Yu * The time field is bit[31:2], but representing a 32bit value with 74bd688c69SFenghua Yu * bit[1:0] zero. 75bd688c69SFenghua Yu */ 76bd688c69SFenghua Yu #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U) 77bd688c69SFenghua Yu 786650cdd9SPeter Zijlstra (Intel) /* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */ 796650cdd9SPeter Zijlstra (Intel) #define MSR_IA32_CORE_CAPS 0x000000cf 80db1af129STony Luck #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT 2 81db1af129STony Luck #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT) 826650cdd9SPeter Zijlstra (Intel) #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5 836650cdd9SPeter Zijlstra (Intel) #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT) 846650cdd9SPeter Zijlstra (Intel) 8540496c8eSLen Brown #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 86b72e7464SBorislav Petkov #define NHM_C3_AUTO_DEMOTE (1UL << 25) 87b72e7464SBorislav Petkov #define NHM_C1_AUTO_DEMOTE (1UL << 26) 88b72e7464SBorislav Petkov #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 89a00072a2SMatt Turner #define SNB_C3_AUTO_UNDEMOTE (1UL << 27) 90a00072a2SMatt Turner #define SNB_C1_AUTO_UNDEMOTE (1UL << 28) 91b72e7464SBorislav Petkov 92b72e7464SBorislav Petkov #define MSR_MTRRcap 0x000000fe 931e340c60SDavid Woodhouse 941e340c60SDavid Woodhouse #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 95d8eabc37SThomas Gleixner #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ 96d8eabc37SThomas Gleixner #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ 976ad0ad2bSPeter Zijlstra #define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */ 98d8eabc37SThomas Gleixner #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ 99d8eabc37SThomas Gleixner #define ARCH_CAP_SSB_NO BIT(4) /* 10077243971SKonrad Rzeszutek Wilk * Not susceptible to Speculative Store Bypass 1019f65fb29SKonrad Rzeszutek Wilk * attack, so no Speculative Store Bypass 1029f65fb29SKonrad Rzeszutek Wilk * control required. 10377243971SKonrad Rzeszutek Wilk */ 104ed5194c2SAndi Kleen #define ARCH_CAP_MDS_NO BIT(5) /* 105ed5194c2SAndi Kleen * Not susceptible to 106ed5194c2SAndi Kleen * Microarchitectural Data 107ed5194c2SAndi Kleen * Sampling (MDS) vulnerabilities. 108ed5194c2SAndi Kleen */ 109db4d30fbSVineela Tummalapalli #define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* 110db4d30fbSVineela Tummalapalli * The processor is not susceptible to a 111db4d30fbSVineela Tummalapalli * machine check error due to modifying the 112db4d30fbSVineela Tummalapalli * code page size along with either the 113db4d30fbSVineela Tummalapalli * physical address or cache type 114db4d30fbSVineela Tummalapalli * without TLB invalidation. 115db4d30fbSVineela Tummalapalli */ 116c2955f27SPawan Gupta #define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ 1171b42f017SPawan Gupta #define ARCH_CAP_TAA_NO BIT(8) /* 1181b42f017SPawan Gupta * Not susceptible to 1191b42f017SPawan Gupta * TSX Async Abort (TAA) vulnerabilities. 1201b42f017SPawan Gupta */ 12151802186SPawan Gupta #define ARCH_CAP_SBDR_SSDP_NO BIT(13) /* 12251802186SPawan Gupta * Not susceptible to SBDR and SSDP 12351802186SPawan Gupta * variants of Processor MMIO stale data 12451802186SPawan Gupta * vulnerabilities. 12551802186SPawan Gupta */ 12651802186SPawan Gupta #define ARCH_CAP_FBSDP_NO BIT(14) /* 12751802186SPawan Gupta * Not susceptible to FBSDP variant of 12851802186SPawan Gupta * Processor MMIO stale data 12951802186SPawan Gupta * vulnerabilities. 13051802186SPawan Gupta */ 13151802186SPawan Gupta #define ARCH_CAP_PSDP_NO BIT(15) /* 13251802186SPawan Gupta * Not susceptible to PSDP variant of 13351802186SPawan Gupta * Processor MMIO stale data 13451802186SPawan Gupta * vulnerabilities. 13551802186SPawan Gupta */ 13651802186SPawan Gupta #define ARCH_CAP_FB_CLEAR BIT(17) /* 13751802186SPawan Gupta * VERW clears CPU fill buffer 13851802186SPawan Gupta * even on MDS_NO CPUs. 13951802186SPawan Gupta */ 140027bbb88SPawan Gupta #define ARCH_CAP_FB_CLEAR_CTRL BIT(18) /* 141027bbb88SPawan Gupta * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS] 142027bbb88SPawan Gupta * bit available to control VERW 143027bbb88SPawan Gupta * behavior. 144027bbb88SPawan Gupta */ 1454ad3278dSPawan Gupta #define ARCH_CAP_RRSBA BIT(19) /* 1464ad3278dSPawan Gupta * Indicates RET may use predictors 1474ad3278dSPawan Gupta * other than the RSB. With eIBRS 1484ad3278dSPawan Gupta * enabled predictions in kernel mode 1494ad3278dSPawan Gupta * are restricted to targets in 1504ad3278dSPawan Gupta * kernel. 1514ad3278dSPawan Gupta */ 1522b129932SDaniel Sneddon #define ARCH_CAP_PBRSB_NO BIT(24) /* 1532b129932SDaniel Sneddon * Not susceptible to Post-Barrier 1542b129932SDaniel Sneddon * Return Stack Buffer Predictions. 1552b129932SDaniel Sneddon */ 1561e340c60SDavid Woodhouse 157b8d1d163SDaniel Sneddon #define ARCH_CAP_XAPIC_DISABLE BIT(21) /* 158b8d1d163SDaniel Sneddon * IA32_XAPIC_DISABLE_STATUS MSR 159b8d1d163SDaniel Sneddon * supported 160b8d1d163SDaniel Sneddon */ 161b8d1d163SDaniel Sneddon 1623fa045beSPaolo Bonzini #define MSR_IA32_FLUSH_CMD 0x0000010b 163d8eabc37SThomas Gleixner #define L1D_FLUSH BIT(0) /* 1643fa045beSPaolo Bonzini * Writeback and invalidate the 1653fa045beSPaolo Bonzini * L1 data cache. 1663fa045beSPaolo Bonzini */ 1673fa045beSPaolo Bonzini 168b72e7464SBorislav Petkov #define MSR_IA32_BBL_CR_CTL 0x00000119 169b72e7464SBorislav Petkov #define MSR_IA32_BBL_CR_CTL3 0x0000011e 170b72e7464SBorislav Petkov 171c2955f27SPawan Gupta #define MSR_IA32_TSX_CTRL 0x00000122 172c2955f27SPawan Gupta #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ 173c2955f27SPawan Gupta #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ 174c2955f27SPawan Gupta 1757e5b3c26SMark Gross #define MSR_IA32_MCU_OPT_CTRL 0x00000123 176400331f8SPawan Gupta #define RNGDS_MITG_DIS BIT(0) /* SRBDS support */ 177400331f8SPawan Gupta #define RTM_ALLOW BIT(1) /* TSX development mode */ 178027bbb88SPawan Gupta #define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */ 1797e5b3c26SMark Gross 180b72e7464SBorislav Petkov #define MSR_IA32_SYSENTER_CS 0x00000174 181b72e7464SBorislav Petkov #define MSR_IA32_SYSENTER_ESP 0x00000175 182b72e7464SBorislav Petkov #define MSR_IA32_SYSENTER_EIP 0x00000176 183b72e7464SBorislav Petkov 184b72e7464SBorislav Petkov #define MSR_IA32_MCG_CAP 0x00000179 185b72e7464SBorislav Petkov #define MSR_IA32_MCG_STATUS 0x0000017a 186b72e7464SBorislav Petkov #define MSR_IA32_MCG_CTL 0x0000017b 18768299a42STony Luck #define MSR_ERROR_CONTROL 0x0000017f 188b72e7464SBorislav Petkov #define MSR_IA32_MCG_EXT_CTL 0x000004d0 189b72e7464SBorislav Petkov 190b72e7464SBorislav Petkov #define MSR_OFFCORE_RSP_0 0x000001a6 191b72e7464SBorislav Petkov #define MSR_OFFCORE_RSP_1 0x000001a7 192b72e7464SBorislav Petkov #define MSR_TURBO_RATIO_LIMIT 0x000001ad 193b72e7464SBorislav Petkov #define MSR_TURBO_RATIO_LIMIT1 0x000001ae 194b72e7464SBorislav Petkov #define MSR_TURBO_RATIO_LIMIT2 0x000001af 195b72e7464SBorislav Petkov 196b72e7464SBorislav Petkov #define MSR_LBR_SELECT 0x000001c8 197b72e7464SBorislav Petkov #define MSR_LBR_TOS 0x000001c9 198ed7bde7aSSrinivas Pandruvada 199ed7bde7aSSrinivas Pandruvada #define MSR_IA32_POWER_CTL 0x000001fc 200ed7bde7aSSrinivas Pandruvada #define MSR_IA32_POWER_CTL_BIT_EE 19 201ed7bde7aSSrinivas Pandruvada 202db1af129STony Luck /* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */ 203db1af129STony Luck #define MSR_INTEGRITY_CAPS 0x000002d9 204db1af129STony Luck #define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4 205db1af129STony Luck #define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT) 206db1af129STony Luck 207b72e7464SBorislav Petkov #define MSR_LBR_NHM_FROM 0x00000680 208b72e7464SBorislav Petkov #define MSR_LBR_NHM_TO 0x000006c0 209b72e7464SBorislav Petkov #define MSR_LBR_CORE_FROM 0x00000040 210b72e7464SBorislav Petkov #define MSR_LBR_CORE_TO 0x00000060 211b72e7464SBorislav Petkov 212b83ff1c8SAndi Kleen #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 213b83ff1c8SAndi Kleen #define LBR_INFO_MISPRED BIT_ULL(63) 214b83ff1c8SAndi Kleen #define LBR_INFO_IN_TX BIT_ULL(62) 215b83ff1c8SAndi Kleen #define LBR_INFO_ABORT BIT_ULL(61) 216d6a162a4SKan Liang #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60) 217b83ff1c8SAndi Kleen #define LBR_INFO_CYCLES 0xffff 218d6a162a4SKan Liang #define LBR_INFO_BR_TYPE_OFFSET 56 219d6a162a4SKan Liang #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) 220d6a162a4SKan Liang 221d6a162a4SKan Liang #define MSR_ARCH_LBR_CTL 0x000014ce 222d6a162a4SKan Liang #define ARCH_LBR_CTL_LBREN BIT(0) 223d6a162a4SKan Liang #define ARCH_LBR_CTL_CPL_OFFSET 1 224d6a162a4SKan Liang #define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET) 225d6a162a4SKan Liang #define ARCH_LBR_CTL_STACK_OFFSET 3 226d6a162a4SKan Liang #define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET) 227d6a162a4SKan Liang #define ARCH_LBR_CTL_FILTER_OFFSET 16 228d6a162a4SKan Liang #define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET) 229d6a162a4SKan Liang #define MSR_ARCH_LBR_DEPTH 0x000014cf 230d6a162a4SKan Liang #define MSR_ARCH_LBR_FROM_0 0x00001500 231d6a162a4SKan Liang #define MSR_ARCH_LBR_TO_0 0x00001600 232d6a162a4SKan Liang #define MSR_ARCH_LBR_INFO_0 0x00001200 233b83ff1c8SAndi Kleen 234b72e7464SBorislav Petkov #define MSR_IA32_PEBS_ENABLE 0x000003f1 235c22497f5SKan Liang #define MSR_PEBS_DATA_CFG 0x000003f2 236b72e7464SBorislav Petkov #define MSR_IA32_DS_AREA 0x00000600 237b72e7464SBorislav Petkov #define MSR_IA32_PERF_CAPABILITIES 0x00000345 238d0946a88SKan Liang #define PERF_CAP_METRICS_IDX 15 239d0946a88SKan Liang #define PERF_CAP_PT_IDX 16 240d0946a88SKan Liang 241b72e7464SBorislav Petkov #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 242c59a1f10SLike Xu #define PERF_CAP_PEBS_TRAP BIT_ULL(6) 243c59a1f10SLike Xu #define PERF_CAP_ARCH_REG BIT_ULL(7) 244c59a1f10SLike Xu #define PERF_CAP_PEBS_FORMAT 0xf00 245c59a1f10SLike Xu #define PERF_CAP_PEBS_BASELINE BIT_ULL(14) 246c59a1f10SLike Xu #define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ 247c59a1f10SLike Xu PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE) 248b72e7464SBorislav Petkov 249b72e7464SBorislav Petkov #define MSR_IA32_RTIT_CTL 0x00000570 250887eda13SChao Peng #define RTIT_CTL_TRACEEN BIT(0) 251887eda13SChao Peng #define RTIT_CTL_CYCLEACC BIT(1) 252887eda13SChao Peng #define RTIT_CTL_OS BIT(2) 253887eda13SChao Peng #define RTIT_CTL_USR BIT(3) 254887eda13SChao Peng #define RTIT_CTL_PWR_EVT_EN BIT(4) 255887eda13SChao Peng #define RTIT_CTL_FUP_ON_PTW BIT(5) 25669843a91SLuwei Kang #define RTIT_CTL_FABRIC_EN BIT(6) 257887eda13SChao Peng #define RTIT_CTL_CR3EN BIT(7) 258887eda13SChao Peng #define RTIT_CTL_TOPA BIT(8) 259887eda13SChao Peng #define RTIT_CTL_MTC_EN BIT(9) 260887eda13SChao Peng #define RTIT_CTL_TSC_EN BIT(10) 261887eda13SChao Peng #define RTIT_CTL_DISRETC BIT(11) 262887eda13SChao Peng #define RTIT_CTL_PTW_EN BIT(12) 263887eda13SChao Peng #define RTIT_CTL_BRANCH_EN BIT(13) 26428c24dedSAlexander Shishkin #define RTIT_CTL_EVENT_EN BIT(31) 265161a9a33SAlexander Shishkin #define RTIT_CTL_NOTNT BIT_ULL(55) 266887eda13SChao Peng #define RTIT_CTL_MTC_RANGE_OFFSET 14 267887eda13SChao Peng #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 268887eda13SChao Peng #define RTIT_CTL_CYC_THRESH_OFFSET 19 269887eda13SChao Peng #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 270887eda13SChao Peng #define RTIT_CTL_PSB_FREQ_OFFSET 24 271887eda13SChao Peng #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 272887eda13SChao Peng #define RTIT_CTL_ADDR0_OFFSET 32 273887eda13SChao Peng #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) 274887eda13SChao Peng #define RTIT_CTL_ADDR1_OFFSET 36 275887eda13SChao Peng #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) 276887eda13SChao Peng #define RTIT_CTL_ADDR2_OFFSET 40 277887eda13SChao Peng #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) 278887eda13SChao Peng #define RTIT_CTL_ADDR3_OFFSET 44 279887eda13SChao Peng #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) 280b72e7464SBorislav Petkov #define MSR_IA32_RTIT_STATUS 0x00000571 281887eda13SChao Peng #define RTIT_STATUS_FILTEREN BIT(0) 282887eda13SChao Peng #define RTIT_STATUS_CONTEXTEN BIT(1) 283887eda13SChao Peng #define RTIT_STATUS_TRIGGEREN BIT(2) 284887eda13SChao Peng #define RTIT_STATUS_BUFFOVF BIT(3) 285887eda13SChao Peng #define RTIT_STATUS_ERROR BIT(4) 286887eda13SChao Peng #define RTIT_STATUS_STOPPED BIT(5) 28769843a91SLuwei Kang #define RTIT_STATUS_BYTECNT_OFFSET 32 28869843a91SLuwei Kang #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) 289f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR0_A 0x00000580 290f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR0_B 0x00000581 291f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR1_A 0x00000582 292f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR1_B 0x00000583 293f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR2_A 0x00000584 294f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR2_B 0x00000585 295f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR3_A 0x00000586 296f127fa09SAlexander Shishkin #define MSR_IA32_RTIT_ADDR3_B 0x00000587 297b72e7464SBorislav Petkov #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 298b72e7464SBorislav Petkov #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 299b72e7464SBorislav Petkov #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 300b72e7464SBorislav Petkov 301b72e7464SBorislav Petkov #define MSR_MTRRfix64K_00000 0x00000250 302b72e7464SBorislav Petkov #define MSR_MTRRfix16K_80000 0x00000258 303b72e7464SBorislav Petkov #define MSR_MTRRfix16K_A0000 0x00000259 304b72e7464SBorislav Petkov #define MSR_MTRRfix4K_C0000 0x00000268 305b72e7464SBorislav Petkov #define MSR_MTRRfix4K_C8000 0x00000269 306b72e7464SBorislav Petkov #define MSR_MTRRfix4K_D0000 0x0000026a 307b72e7464SBorislav Petkov #define MSR_MTRRfix4K_D8000 0x0000026b 308b72e7464SBorislav Petkov #define MSR_MTRRfix4K_E0000 0x0000026c 309b72e7464SBorislav Petkov #define MSR_MTRRfix4K_E8000 0x0000026d 310b72e7464SBorislav Petkov #define MSR_MTRRfix4K_F0000 0x0000026e 311b72e7464SBorislav Petkov #define MSR_MTRRfix4K_F8000 0x0000026f 312b72e7464SBorislav Petkov #define MSR_MTRRdefType 0x000002ff 313b72e7464SBorislav Petkov 314b72e7464SBorislav Petkov #define MSR_IA32_CR_PAT 0x00000277 315b72e7464SBorislav Petkov 316b72e7464SBorislav Petkov #define MSR_IA32_DEBUGCTLMSR 0x000001d9 317b72e7464SBorislav Petkov #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 318b72e7464SBorislav Petkov #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 319b72e7464SBorislav Petkov #define MSR_IA32_LASTINTFROMIP 0x000001dd 320b72e7464SBorislav Petkov #define MSR_IA32_LASTINTTOIP 0x000001de 321b72e7464SBorislav Petkov 322f0f2f9feSFenghua Yu #define MSR_IA32_PASID 0x00000d93 323f0f2f9feSFenghua Yu #define MSR_IA32_PASID_VALID BIT_ULL(31) 324f0f2f9feSFenghua Yu 325b72e7464SBorislav Petkov /* DEBUGCTLMSR bits (others vary by model): */ 326b72e7464SBorislav Petkov #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 327b9894a2fSKyle Huey #define DEBUGCTLMSR_BTF_SHIFT 1 328b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 329ebb1064eSFenghua Yu #define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2) 330b72e7464SBorislav Petkov #define DEBUGCTLMSR_TR (1UL << 6) 331b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTS (1UL << 7) 332b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTINT (1UL << 8) 333b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 334b72e7464SBorislav Petkov #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 335b72e7464SBorislav Petkov #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 336af3bdb99SAndi Kleen #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) 3376089327fSKan Liang #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 3386089327fSKan Liang #define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 339b72e7464SBorislav Petkov 340d0dc8494SAndi Kleen #define MSR_PEBS_FRONTEND 0x000003f7 341d0dc8494SAndi Kleen 342b72e7464SBorislav Petkov #define MSR_IA32_MC0_CTL 0x00000400 343b72e7464SBorislav Petkov #define MSR_IA32_MC0_STATUS 0x00000401 344b72e7464SBorislav Petkov #define MSR_IA32_MC0_ADDR 0x00000402 345b72e7464SBorislav Petkov #define MSR_IA32_MC0_MISC 0x00000403 346b72e7464SBorislav Petkov 347b72e7464SBorislav Petkov /* C-state Residency Counters */ 348b72e7464SBorislav Petkov #define MSR_PKG_C3_RESIDENCY 0x000003f8 349b72e7464SBorislav Petkov #define MSR_PKG_C6_RESIDENCY 0x000003f9 3500539ba11SLen Brown #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 351b72e7464SBorislav Petkov #define MSR_PKG_C7_RESIDENCY 0x000003fa 352b72e7464SBorislav Petkov #define MSR_CORE_C3_RESIDENCY 0x000003fc 353b72e7464SBorislav Petkov #define MSR_CORE_C6_RESIDENCY 0x000003fd 354b72e7464SBorislav Petkov #define MSR_CORE_C7_RESIDENCY 0x000003fe 355b72e7464SBorislav Petkov #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 356b72e7464SBorislav Petkov #define MSR_PKG_C2_RESIDENCY 0x0000060d 357b72e7464SBorislav Petkov #define MSR_PKG_C8_RESIDENCY 0x00000630 358b72e7464SBorislav Petkov #define MSR_PKG_C9_RESIDENCY 0x00000631 359b72e7464SBorislav Petkov #define MSR_PKG_C10_RESIDENCY 0x00000632 360b72e7464SBorislav Petkov 3615a63426eSLen Brown /* Interrupt Response Limit */ 3625a63426eSLen Brown #define MSR_PKGC3_IRTL 0x0000060a 3635a63426eSLen Brown #define MSR_PKGC6_IRTL 0x0000060b 3645a63426eSLen Brown #define MSR_PKGC7_IRTL 0x0000060c 3655a63426eSLen Brown #define MSR_PKGC8_IRTL 0x00000633 3665a63426eSLen Brown #define MSR_PKGC9_IRTL 0x00000634 3675a63426eSLen Brown #define MSR_PKGC10_IRTL 0x00000635 3685a63426eSLen Brown 369b72e7464SBorislav Petkov /* Run Time Average Power Limiting (RAPL) Interface */ 370b72e7464SBorislav Petkov 371f52ba931SSumeet Pawnikar #define MSR_VR_CURRENT_CONFIG 0x00000601 372b72e7464SBorislav Petkov #define MSR_RAPL_POWER_UNIT 0x00000606 373b72e7464SBorislav Petkov 374b72e7464SBorislav Petkov #define MSR_PKG_POWER_LIMIT 0x00000610 375b72e7464SBorislav Petkov #define MSR_PKG_ENERGY_STATUS 0x00000611 376b72e7464SBorislav Petkov #define MSR_PKG_PERF_STATUS 0x00000613 377b72e7464SBorislav Petkov #define MSR_PKG_POWER_INFO 0x00000614 378b72e7464SBorislav Petkov 379b72e7464SBorislav Petkov #define MSR_DRAM_POWER_LIMIT 0x00000618 380b72e7464SBorislav Petkov #define MSR_DRAM_ENERGY_STATUS 0x00000619 381b72e7464SBorislav Petkov #define MSR_DRAM_PERF_STATUS 0x0000061b 382b72e7464SBorislav Petkov #define MSR_DRAM_POWER_INFO 0x0000061c 383b72e7464SBorislav Petkov 384b72e7464SBorislav Petkov #define MSR_PP0_POWER_LIMIT 0x00000638 385b72e7464SBorislav Petkov #define MSR_PP0_ENERGY_STATUS 0x00000639 386b72e7464SBorislav Petkov #define MSR_PP0_POLICY 0x0000063a 387b72e7464SBorislav Petkov #define MSR_PP0_PERF_STATUS 0x0000063b 388b72e7464SBorislav Petkov 389b72e7464SBorislav Petkov #define MSR_PP1_POWER_LIMIT 0x00000640 390b72e7464SBorislav Petkov #define MSR_PP1_ENERGY_STATUS 0x00000641 391b72e7464SBorislav Petkov #define MSR_PP1_POLICY 0x00000642 392b72e7464SBorislav Petkov 3935cde2653SStephane Eranian #define MSR_AMD_RAPL_POWER_UNIT 0xc0010299 39443756a29SVictor Ding #define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a 395298ed2b3SVictor Ding #define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b 3965cde2653SStephane Eranian 3974a6772f5SVladimir Zapolskiy /* Config TDP MSRs */ 39882bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_NOMINAL 0x00000648 39982bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 40082bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 40182bb70c5SRafael J. Wysocki #define MSR_CONFIG_TDP_CONTROL 0x0000064B 40282bb70c5SRafael J. Wysocki #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 40382bb70c5SRafael J. Wysocki 404dcee75b3SSrinivas Pandruvada #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 4054af184eeSLen Brown #define MSR_SECONDARY_TURBO_RATIO_LIMIT 0x00000650 406dcee75b3SSrinivas Pandruvada 407b72e7464SBorislav Petkov #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 408b72e7464SBorislav Petkov #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 409b72e7464SBorislav Petkov #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 410b72e7464SBorislav Petkov #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 411b72e7464SBorislav Petkov 412b72e7464SBorislav Petkov #define MSR_CORE_C1_RES 0x00000660 4130539ba11SLen Brown #define MSR_MODULE_C6_RES_MS 0x00000664 414b72e7464SBorislav Petkov 415b72e7464SBorislav Petkov #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 416b72e7464SBorislav Petkov #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 417b72e7464SBorislav Petkov 4188a34fd02SLen Brown #define MSR_ATOM_CORE_RATIOS 0x0000066a 4198a34fd02SLen Brown #define MSR_ATOM_CORE_VIDS 0x0000066b 4208a34fd02SLen Brown #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 4218a34fd02SLen Brown #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 4228a34fd02SLen Brown 423b72e7464SBorislav Petkov #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 424b72e7464SBorislav Petkov #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 425b72e7464SBorislav Petkov #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 426b72e7464SBorislav Petkov 427991625f3SPeter Zijlstra /* Control-flow Enforcement Technology MSRs */ 428991625f3SPeter Zijlstra #define MSR_IA32_U_CET 0x000006a0 /* user mode cet */ 429991625f3SPeter Zijlstra #define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */ 430991625f3SPeter Zijlstra #define CET_SHSTK_EN BIT_ULL(0) 431991625f3SPeter Zijlstra #define CET_WRSS_EN BIT_ULL(1) 432991625f3SPeter Zijlstra #define CET_ENDBR_EN BIT_ULL(2) 433991625f3SPeter Zijlstra #define CET_LEG_IW_EN BIT_ULL(3) 434991625f3SPeter Zijlstra #define CET_NO_TRACK_EN BIT_ULL(4) 435991625f3SPeter Zijlstra #define CET_SUPPRESS_DISABLE BIT_ULL(5) 436991625f3SPeter Zijlstra #define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9)) 437991625f3SPeter Zijlstra #define CET_SUPPRESS BIT_ULL(10) 438991625f3SPeter Zijlstra #define CET_WAIT_ENDBR BIT_ULL(11) 439991625f3SPeter Zijlstra 440991625f3SPeter Zijlstra #define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */ 441991625f3SPeter Zijlstra #define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */ 442991625f3SPeter Zijlstra #define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */ 443991625f3SPeter Zijlstra #define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */ 444991625f3SPeter Zijlstra #define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */ 445991625f3SPeter Zijlstra 446b72e7464SBorislav Petkov /* Hardware P state interface */ 447b72e7464SBorislav Petkov #define MSR_PPERF 0x0000064e 448b72e7464SBorislav Petkov #define MSR_PERF_LIMIT_REASONS 0x0000064f 449b72e7464SBorislav Petkov #define MSR_PM_ENABLE 0x00000770 450b72e7464SBorislav Petkov #define MSR_HWP_CAPABILITIES 0x00000771 451b72e7464SBorislav Petkov #define MSR_HWP_REQUEST_PKG 0x00000772 452b72e7464SBorislav Petkov #define MSR_HWP_INTERRUPT 0x00000773 453b72e7464SBorislav Petkov #define MSR_HWP_REQUEST 0x00000774 454b72e7464SBorislav Petkov #define MSR_HWP_STATUS 0x00000777 455b72e7464SBorislav Petkov 456b72e7464SBorislav Petkov /* CPUID.6.EAX */ 457b72e7464SBorislav Petkov #define HWP_BASE_BIT (1<<7) 458b72e7464SBorislav Petkov #define HWP_NOTIFICATIONS_BIT (1<<8) 459b72e7464SBorislav Petkov #define HWP_ACTIVITY_WINDOW_BIT (1<<9) 460b72e7464SBorislav Petkov #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 461b72e7464SBorislav Petkov #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 462b72e7464SBorislav Petkov 463b72e7464SBorislav Petkov /* IA32_HWP_CAPABILITIES */ 464670e27d8SLen Brown #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 465670e27d8SLen Brown #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 466670e27d8SLen Brown #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 467670e27d8SLen Brown #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 468b72e7464SBorislav Petkov 469b72e7464SBorislav Petkov /* IA32_HWP_REQUEST */ 470b72e7464SBorislav Petkov #define HWP_MIN_PERF(x) (x & 0xff) 471b72e7464SBorislav Petkov #define HWP_MAX_PERF(x) ((x & 0xff) << 8) 472b72e7464SBorislav Petkov #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 4732fc49cb0SLen Brown #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) 4748d84e906SLen Brown #define HWP_EPP_PERFORMANCE 0x00 4758d84e906SLen Brown #define HWP_EPP_BALANCE_PERFORMANCE 0x80 4768d84e906SLen Brown #define HWP_EPP_BALANCE_POWERSAVE 0xC0 4778d84e906SLen Brown #define HWP_EPP_POWERSAVE 0xFF 4782fc49cb0SLen Brown #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) 4792fc49cb0SLen Brown #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) 480b72e7464SBorislav Petkov 481b72e7464SBorislav Petkov /* IA32_HWP_STATUS */ 482b72e7464SBorislav Petkov #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 483b72e7464SBorislav Petkov #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 484b72e7464SBorislav Petkov 485b72e7464SBorislav Petkov /* IA32_HWP_INTERRUPT */ 486b72e7464SBorislav Petkov #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 487b72e7464SBorislav Petkov #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 488b72e7464SBorislav Petkov 489b72e7464SBorislav Petkov #define MSR_AMD64_MC0_MASK 0xc0010044 490b72e7464SBorislav Petkov 491b72e7464SBorislav Petkov #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 492b72e7464SBorislav Petkov #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 493b72e7464SBorislav Petkov #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 494b72e7464SBorislav Petkov #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 495b72e7464SBorislav Petkov 496b72e7464SBorislav Petkov #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 497b72e7464SBorislav Petkov 498b72e7464SBorislav Petkov /* These are consecutive and not in the normal 4er MCE bank block */ 499b72e7464SBorislav Petkov #define MSR_IA32_MC0_CTL2 0x00000280 500b72e7464SBorislav Petkov #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 501b72e7464SBorislav Petkov 502b72e7464SBorislav Petkov #define MSR_P6_PERFCTR0 0x000000c1 503b72e7464SBorislav Petkov #define MSR_P6_PERFCTR1 0x000000c2 504b72e7464SBorislav Petkov #define MSR_P6_EVNTSEL0 0x00000186 505b72e7464SBorislav Petkov #define MSR_P6_EVNTSEL1 0x00000187 506b72e7464SBorislav Petkov 507b72e7464SBorislav Petkov #define MSR_KNC_PERFCTR0 0x00000020 508b72e7464SBorislav Petkov #define MSR_KNC_PERFCTR1 0x00000021 509b72e7464SBorislav Petkov #define MSR_KNC_EVNTSEL0 0x00000028 510b72e7464SBorislav Petkov #define MSR_KNC_EVNTSEL1 0x00000029 511b72e7464SBorislav Petkov 512b72e7464SBorislav Petkov /* Alternative perfctr range with full access. */ 513b72e7464SBorislav Petkov #define MSR_IA32_PMC0 0x000004c1 514b72e7464SBorislav Petkov 51542880f72SAlexander Shishkin /* Auto-reload via MSR instead of DS area */ 51642880f72SAlexander Shishkin #define MSR_RELOAD_PMC0 0x000014c1 51742880f72SAlexander Shishkin #define MSR_RELOAD_FIXED_CTR0 0x00001309 51842880f72SAlexander Shishkin 519342061c5SBorislav Petkov /* 520342061c5SBorislav Petkov * AMD64 MSRs. Not complete. See the architecture manual for a more 521342061c5SBorislav Petkov * complete list. 522342061c5SBorislav Petkov */ 523b72e7464SBorislav Petkov #define MSR_AMD64_PATCH_LEVEL 0x0000008b 524b72e7464SBorislav Petkov #define MSR_AMD64_TSC_RATIO 0xc0000104 525b72e7464SBorislav Petkov #define MSR_AMD64_NB_CFG 0xc001001f 526b72e7464SBorislav Petkov #define MSR_AMD64_PATCH_LOADER 0xc0010020 527342061c5SBorislav Petkov #define MSR_AMD_PERF_CTL 0xc0010062 528342061c5SBorislav Petkov #define MSR_AMD_PERF_STATUS 0xc0010063 529342061c5SBorislav Petkov #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 530b72e7464SBorislav Petkov #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 531b72e7464SBorislav Petkov #define MSR_AMD64_OSVW_STATUS 0xc0010141 5324e3f77d8SJan Beulich #define MSR_AMD_PPIN_CTL 0xc00102f0 5334e3f77d8SJan Beulich #define MSR_AMD_PPIN 0xc00102f1 5341068ed45SBorislav Petkov #define MSR_AMD64_CPUID_FN_1 0xc0011004 535b72e7464SBorislav Petkov #define MSR_AMD64_LS_CFG 0xc0011020 536b72e7464SBorislav Petkov #define MSR_AMD64_DC_CFG 0xc0011022 5372632daebSBorislav Petkov 5382632daebSBorislav Petkov #define MSR_AMD64_DE_CFG 0xc0011029 5392632daebSBorislav Petkov #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1 5402632daebSBorislav Petkov #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT) 5412632daebSBorislav Petkov 542b72e7464SBorislav Petkov #define MSR_AMD64_BU_CFG2 0xc001102a 543b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCHCTL 0xc0011030 544b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 545b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 546b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCH_REG_COUNT 3 547b72e7464SBorislav Petkov #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 548b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPCTL 0xc0011033 549b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPRIP 0xc0011034 550b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA 0xc0011035 551b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA2 0xc0011036 552b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA3 0xc0011037 553b72e7464SBorislav Petkov #define MSR_AMD64_IBSDCLINAD 0xc0011038 554b72e7464SBorislav Petkov #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 555b72e7464SBorislav Petkov #define MSR_AMD64_IBSOP_REG_COUNT 7 556b72e7464SBorislav Petkov #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 557b72e7464SBorislav Petkov #define MSR_AMD64_IBSCTL 0xc001103a 558b72e7464SBorislav Petkov #define MSR_AMD64_IBSBRTARGET 0xc001103b 55936e1be8aSKim Phillips #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c 560b72e7464SBorislav Petkov #define MSR_AMD64_IBSOPDATA4 0xc001103d 561b72e7464SBorislav Petkov #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 56239150352SMaxim Levitsky #define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b 56369372cf0STom Lendacky #define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e 56429dcc60fSJoerg Roedel #define MSR_AMD64_SEV_ES_GHCB 0xc0010130 5651958b5fcSTom Lendacky #define MSR_AMD64_SEV 0xc0010131 5661958b5fcSTom Lendacky #define MSR_AMD64_SEV_ENABLED_BIT 0 567b57de6cdSJoerg Roedel #define MSR_AMD64_SEV_ES_ENABLED_BIT 1 568f742b90eSBrijesh Singh #define MSR_AMD64_SEV_SNP_ENABLED_BIT 2 5691958b5fcSTom Lendacky #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) 570b57de6cdSJoerg Roedel #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) 571f742b90eSBrijesh Singh #define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) 572b72e7464SBorislav Petkov 57311fb0683STom Lendacky #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f 57411fb0683STom Lendacky 57589aa94b4SHuang Rui /* AMD Collaborative Processor Performance Control MSRs */ 57689aa94b4SHuang Rui #define MSR_AMD_CPPC_CAP1 0xc00102b0 57789aa94b4SHuang Rui #define MSR_AMD_CPPC_ENABLE 0xc00102b1 57889aa94b4SHuang Rui #define MSR_AMD_CPPC_CAP2 0xc00102b2 57989aa94b4SHuang Rui #define MSR_AMD_CPPC_REQ 0xc00102b3 58089aa94b4SHuang Rui #define MSR_AMD_CPPC_STATUS 0xc00102b4 58189aa94b4SHuang Rui 58289aa94b4SHuang Rui #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) 58389aa94b4SHuang Rui #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) 58489aa94b4SHuang Rui #define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff) 58589aa94b4SHuang Rui #define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff) 58689aa94b4SHuang Rui 58789aa94b4SHuang Rui #define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0) 58889aa94b4SHuang Rui #define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) 58989aa94b4SHuang Rui #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) 59089aa94b4SHuang Rui #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) 59189aa94b4SHuang Rui 592089be16dSSandipan Das /* AMD Performance Counter Global Status and Control MSRs */ 593089be16dSSandipan Das #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 594089be16dSSandipan Das #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 595089be16dSSandipan Das #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 596089be16dSSandipan Das 597ca5b7c0dSSandipan Das /* AMD Last Branch Record MSRs */ 598ca5b7c0dSSandipan Das #define MSR_AMD64_LBR_SELECT 0xc000010e 599ca5b7c0dSSandipan Das 600aaf24884SHuang Rui /* Fam 17h MSRs */ 601aaf24884SHuang Rui #define MSR_F17H_IRPERF 0xc00000e9 602aaf24884SHuang Rui 603d7caac99SPeter Zijlstra #define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3 604d7caac99SPeter Zijlstra #define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1) 605d7caac99SPeter Zijlstra 606b72e7464SBorislav Petkov /* Fam 16h MSRs */ 607b72e7464SBorislav Petkov #define MSR_F16H_L2I_PERF_CTL 0xc0010230 608b72e7464SBorislav Petkov #define MSR_F16H_L2I_PERF_CTR 0xc0010231 609b72e7464SBorislav Petkov #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 610b72e7464SBorislav Petkov #define MSR_F16H_DR2_ADDR_MASK 0xc001101a 611b72e7464SBorislav Petkov #define MSR_F16H_DR3_ADDR_MASK 0xc001101b 612b72e7464SBorislav Petkov #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 613b72e7464SBorislav Petkov 614b72e7464SBorislav Petkov /* Fam 15h MSRs */ 61599e40204SBorislav Petkov #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a 61699e40204SBorislav Petkov #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b 617b72e7464SBorislav Petkov #define MSR_F15H_PERF_CTL 0xc0010200 618e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 619e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 620e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 621e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 622e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 623e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 624e84b7119SJanakarajan Natarajan 625b72e7464SBorislav Petkov #define MSR_F15H_PERF_CTR 0xc0010201 626e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 627e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 628e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 629e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 630e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 631e84b7119SJanakarajan Natarajan #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 632e84b7119SJanakarajan Natarajan 633b72e7464SBorislav Petkov #define MSR_F15H_NB_PERF_CTL 0xc0010240 634b72e7464SBorislav Petkov #define MSR_F15H_NB_PERF_CTR 0xc0010241 6358a224261SHuang Rui #define MSR_F15H_PTSC 0xc0010280 636ae8b7875SBorislav Petkov #define MSR_F15H_IC_CFG 0xc0011021 6370e1b869fSEduardo Habkost #define MSR_F15H_EX_CFG 0xc001102c 638b72e7464SBorislav Petkov 639b72e7464SBorislav Petkov /* Fam 10h MSRs */ 640b72e7464SBorislav Petkov #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 641b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_ENABLE (1<<0) 642b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 643b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 644b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 645b72e7464SBorislav Petkov #define FAM10H_MMIO_CONF_BASE_SHIFT 20 646b72e7464SBorislav Petkov #define MSR_FAM10H_NODE_ID 0xc001100c 647b72e7464SBorislav Petkov 648b72e7464SBorislav Petkov /* K8 MSRs */ 649b72e7464SBorislav Petkov #define MSR_K8_TOP_MEM1 0xc001001a 650b72e7464SBorislav Petkov #define MSR_K8_TOP_MEM2 0xc001001d 651059e5c32SBrijesh Singh #define MSR_AMD64_SYSCFG 0xc0010010 652059e5c32SBrijesh Singh #define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23 653059e5c32SBrijesh Singh #define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT) 654b72e7464SBorislav Petkov #define MSR_K8_INT_PENDING_MSG 0xc0010055 655b72e7464SBorislav Petkov /* C1E active bits in int pending message */ 656b72e7464SBorislav Petkov #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 657b72e7464SBorislav Petkov #define MSR_K8_TSEG_ADDR 0xc0010112 6583afb1121SPaolo Bonzini #define MSR_K8_TSEG_MASK 0xc0010113 659b72e7464SBorislav Petkov #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 660b72e7464SBorislav Petkov #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 661b72e7464SBorislav Petkov #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 662b72e7464SBorislav Petkov 663b72e7464SBorislav Petkov /* K7 MSRs */ 664b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL0 0xc0010000 665b72e7464SBorislav Petkov #define MSR_K7_PERFCTR0 0xc0010004 666b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL1 0xc0010001 667b72e7464SBorislav Petkov #define MSR_K7_PERFCTR1 0xc0010005 668b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL2 0xc0010002 669b72e7464SBorislav Petkov #define MSR_K7_PERFCTR2 0xc0010006 670b72e7464SBorislav Petkov #define MSR_K7_EVNTSEL3 0xc0010003 671b72e7464SBorislav Petkov #define MSR_K7_PERFCTR3 0xc0010007 672b72e7464SBorislav Petkov #define MSR_K7_CLK_CTL 0xc001001b 673b72e7464SBorislav Petkov #define MSR_K7_HWCR 0xc0010015 67418c71ce9STom Lendacky #define MSR_K7_HWCR_SMMLOCK_BIT 0 67518c71ce9STom Lendacky #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) 67621b5ee59SKim Phillips #define MSR_K7_HWCR_IRPERF_EN_BIT 30 67721b5ee59SKim Phillips #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) 678b72e7464SBorislav Petkov #define MSR_K7_FID_VID_CTL 0xc0010041 679b72e7464SBorislav Petkov #define MSR_K7_FID_VID_STATUS 0xc0010042 680b72e7464SBorislav Petkov 681b72e7464SBorislav Petkov /* K6 MSRs */ 682b72e7464SBorislav Petkov #define MSR_K6_WHCR 0xc0000082 683b72e7464SBorislav Petkov #define MSR_K6_UWCCR 0xc0000085 684b72e7464SBorislav Petkov #define MSR_K6_EPMR 0xc0000086 685b72e7464SBorislav Petkov #define MSR_K6_PSOR 0xc0000087 686b72e7464SBorislav Petkov #define MSR_K6_PFIR 0xc0000088 687b72e7464SBorislav Petkov 688b72e7464SBorislav Petkov /* Centaur-Hauls/IDT defined MSRs. */ 689b72e7464SBorislav Petkov #define MSR_IDT_FCR1 0x00000107 690b72e7464SBorislav Petkov #define MSR_IDT_FCR2 0x00000108 691b72e7464SBorislav Petkov #define MSR_IDT_FCR3 0x00000109 692b72e7464SBorislav Petkov #define MSR_IDT_FCR4 0x0000010a 693b72e7464SBorislav Petkov 694b72e7464SBorislav Petkov #define MSR_IDT_MCR0 0x00000110 695b72e7464SBorislav Petkov #define MSR_IDT_MCR1 0x00000111 696b72e7464SBorislav Petkov #define MSR_IDT_MCR2 0x00000112 697b72e7464SBorislav Petkov #define MSR_IDT_MCR3 0x00000113 698b72e7464SBorislav Petkov #define MSR_IDT_MCR4 0x00000114 699b72e7464SBorislav Petkov #define MSR_IDT_MCR5 0x00000115 700b72e7464SBorislav Petkov #define MSR_IDT_MCR6 0x00000116 701b72e7464SBorislav Petkov #define MSR_IDT_MCR7 0x00000117 702b72e7464SBorislav Petkov #define MSR_IDT_MCR_CTRL 0x00000120 703b72e7464SBorislav Petkov 704b72e7464SBorislav Petkov /* VIA Cyrix defined MSRs*/ 705b72e7464SBorislav Petkov #define MSR_VIA_FCR 0x00001107 706b72e7464SBorislav Petkov #define MSR_VIA_LONGHAUL 0x0000110a 707b72e7464SBorislav Petkov #define MSR_VIA_RNG 0x0000110b 708b72e7464SBorislav Petkov #define MSR_VIA_BCR2 0x00001147 709b72e7464SBorislav Petkov 710b72e7464SBorislav Petkov /* Transmeta defined MSRs */ 711b72e7464SBorislav Petkov #define MSR_TMTA_LONGRUN_CTRL 0x80868010 712b72e7464SBorislav Petkov #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 713b72e7464SBorislav Petkov #define MSR_TMTA_LRTI_READOUT 0x80868018 714b72e7464SBorislav Petkov #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 715b72e7464SBorislav Petkov 716b72e7464SBorislav Petkov /* Intel defined MSRs. */ 717b72e7464SBorislav Petkov #define MSR_IA32_P5_MC_ADDR 0x00000000 718b72e7464SBorislav Petkov #define MSR_IA32_P5_MC_TYPE 0x00000001 719b72e7464SBorislav Petkov #define MSR_IA32_TSC 0x00000010 720b72e7464SBorislav Petkov #define MSR_IA32_PLATFORM_ID 0x00000017 721b72e7464SBorislav Petkov #define MSR_IA32_EBL_CR_POWERON 0x0000002a 722b72e7464SBorislav Petkov #define MSR_EBC_FREQUENCY_ID 0x0000002c 723b72e7464SBorislav Petkov #define MSR_SMI_COUNT 0x00000034 72432ad73dbSSean Christopherson 72532ad73dbSSean Christopherson /* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */ 72632ad73dbSSean Christopherson #define MSR_IA32_FEAT_CTL 0x0000003a 72732ad73dbSSean Christopherson #define FEAT_CTL_LOCKED BIT(0) 72832ad73dbSSean Christopherson #define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1) 72932ad73dbSSean Christopherson #define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2) 730d205e0f1SSean Christopherson #define FEAT_CTL_SGX_LC_ENABLED BIT(17) 731e7b6385bSSean Christopherson #define FEAT_CTL_SGX_ENABLED BIT(18) 73232ad73dbSSean Christopherson #define FEAT_CTL_LMCE_ENABLED BIT(20) 73332ad73dbSSean Christopherson 734b72e7464SBorislav Petkov #define MSR_IA32_TSC_ADJUST 0x0000003b 735b72e7464SBorislav Petkov #define MSR_IA32_BNDCFGS 0x00000d90 736b72e7464SBorislav Petkov 7374531662dSJim Mattson #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 7384531662dSJim Mattson 739dae1bd58SChang S. Bae #define MSR_IA32_XFD 0x000001c4 740dae1bd58SChang S. Bae #define MSR_IA32_XFD_ERR 0x000001c5 741b72e7464SBorislav Petkov #define MSR_IA32_XSS 0x00000da0 742b72e7464SBorislav Petkov 743b72e7464SBorislav Petkov #define MSR_IA32_APICBASE 0x0000001b 744b72e7464SBorislav Petkov #define MSR_IA32_APICBASE_BSP (1<<8) 745b72e7464SBorislav Petkov #define MSR_IA32_APICBASE_ENABLE (1<<11) 746b72e7464SBorislav Petkov #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 747b72e7464SBorislav Petkov 748b72e7464SBorislav Petkov #define MSR_IA32_UCODE_WRITE 0x00000079 749b72e7464SBorislav Petkov #define MSR_IA32_UCODE_REV 0x0000008b 750b72e7464SBorislav Petkov 751d205e0f1SSean Christopherson /* Intel SGX Launch Enclave Public Key Hash MSRs */ 752d205e0f1SSean Christopherson #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C 753d205e0f1SSean Christopherson #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D 754d205e0f1SSean Christopherson #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E 755d205e0f1SSean Christopherson #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F 756d205e0f1SSean Christopherson 757b72e7464SBorislav Petkov #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 758b72e7464SBorislav Petkov #define MSR_IA32_SMBASE 0x0000009e 759b72e7464SBorislav Petkov 760b72e7464SBorislav Petkov #define MSR_IA32_PERF_STATUS 0x00000198 761b72e7464SBorislav Petkov #define MSR_IA32_PERF_CTL 0x00000199 762b72e7464SBorislav Petkov #define INTEL_PERF_CTL_MASK 0xffff 763b72e7464SBorislav Petkov 764ada54345SStephane Eranian /* AMD Branch Sampling configuration */ 765ada54345SStephane Eranian #define MSR_AMD_DBG_EXTN_CFG 0xc000010f 766ada54345SStephane Eranian #define MSR_AMD_SAMP_BR_FROM 0xc0010300 767ada54345SStephane Eranian 768ca5b7c0dSSandipan Das #define DBG_EXTN_CFG_LBRV2EN BIT_ULL(6) 769ca5b7c0dSSandipan Das 770b72e7464SBorislav Petkov #define MSR_IA32_MPERF 0x000000e7 771b72e7464SBorislav Petkov #define MSR_IA32_APERF 0x000000e8 772b72e7464SBorislav Petkov 773b72e7464SBorislav Petkov #define MSR_IA32_THERM_CONTROL 0x0000019a 774b72e7464SBorislav Petkov #define MSR_IA32_THERM_INTERRUPT 0x0000019b 775b72e7464SBorislav Petkov 776b72e7464SBorislav Petkov #define THERM_INT_HIGH_ENABLE (1 << 0) 777b72e7464SBorislav Petkov #define THERM_INT_LOW_ENABLE (1 << 1) 778b72e7464SBorislav Petkov #define THERM_INT_PLN_ENABLE (1 << 24) 779b72e7464SBorislav Petkov 780b72e7464SBorislav Petkov #define MSR_IA32_THERM_STATUS 0x0000019c 781b72e7464SBorislav Petkov 782b72e7464SBorislav Petkov #define THERM_STATUS_PROCHOT (1 << 0) 783b72e7464SBorislav Petkov #define THERM_STATUS_POWER_LIMIT (1 << 10) 784b72e7464SBorislav Petkov 785b72e7464SBorislav Petkov #define MSR_THERM2_CTL 0x0000019d 786b72e7464SBorislav Petkov 787b72e7464SBorislav Petkov #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 788b72e7464SBorislav Petkov 789b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE 0x000001a0 790b72e7464SBorislav Petkov 791b72e7464SBorislav Petkov #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 792b72e7464SBorislav Petkov 79398af7459SLen Brown #define MSR_MISC_FEATURE_CONTROL 0x000001a4 794b72e7464SBorislav Petkov #define MSR_MISC_PWR_MGMT 0x000001aa 795b72e7464SBorislav Petkov 796b72e7464SBorislav Petkov #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 797b72e7464SBorislav Petkov #define ENERGY_PERF_BIAS_PERFORMANCE 0 798d0117a0eSLen Brown #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 799b72e7464SBorislav Petkov #define ENERGY_PERF_BIAS_NORMAL 6 8007420ae3bSSrinivas Pandruvada #define ENERGY_PERF_BIAS_NORMAL_POWERSAVE 7 801d0117a0eSLen Brown #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 802b72e7464SBorislav Petkov #define ENERGY_PERF_BIAS_POWERSAVE 15 803b72e7464SBorislav Petkov 804b72e7464SBorislav Petkov #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 805b72e7464SBorislav Petkov 806b72e7464SBorislav Petkov #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 807b72e7464SBorislav Petkov #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 8087b8f40b3SRicardo Neri #define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26) 809b72e7464SBorislav Petkov 810b72e7464SBorislav Petkov #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 811b72e7464SBorislav Petkov 812b72e7464SBorislav Petkov #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 813b72e7464SBorislav Petkov #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 814b72e7464SBorislav Petkov #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 8157b8f40b3SRicardo Neri #define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25) 816b72e7464SBorislav Petkov 817b72e7464SBorislav Petkov /* Thermal Thresholds Support */ 818b72e7464SBorislav Petkov #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 819b72e7464SBorislav Petkov #define THERM_SHIFT_THRESHOLD0 8 820b72e7464SBorislav Petkov #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 821b72e7464SBorislav Petkov #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 822b72e7464SBorislav Petkov #define THERM_SHIFT_THRESHOLD1 16 823b72e7464SBorislav Petkov #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 824b72e7464SBorislav Petkov #define THERM_STATUS_THRESHOLD0 (1 << 6) 825b72e7464SBorislav Petkov #define THERM_LOG_THRESHOLD0 (1 << 7) 826b72e7464SBorislav Petkov #define THERM_STATUS_THRESHOLD1 (1 << 8) 827b72e7464SBorislav Petkov #define THERM_LOG_THRESHOLD1 (1 << 9) 828b72e7464SBorislav Petkov 829b72e7464SBorislav Petkov /* MISC_ENABLE bits: architectural */ 830b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 831b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 832b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 833b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 834b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 835b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 836b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 837b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 838b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 839b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 840b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 841b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 842b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 843b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 844b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 845b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 846b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 847b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 848b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 849b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 850b72e7464SBorislav Petkov 851b72e7464SBorislav Petkov /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 852b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 853b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 854b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 855b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 856b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 857b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 858b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 859b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 860b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 861b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 862b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 863b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 864b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 865b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 866b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 867b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 868b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 869b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 870b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 871b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 872b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 873b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 874b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 875b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 876b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 877b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 878b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 879b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 880b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 881b72e7464SBorislav Petkov #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 882b72e7464SBorislav Petkov 883ab6d9468SKyle Huey /* MISC_FEATURES_ENABLES non-architectural features */ 884ab6d9468SKyle Huey #define MSR_MISC_FEATURES_ENABLES 0x00000140 885ae47eda9SGrzegorz Andrejczuk 886e9ea1e7fSKyle Huey #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 887e9ea1e7fSKyle Huey #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) 888ab6d9468SKyle Huey #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 889ae47eda9SGrzegorz Andrejczuk 890b72e7464SBorislav Petkov #define MSR_IA32_TSC_DEADLINE 0x000006E0 891b72e7464SBorislav Petkov 89252f64909SPeter Zijlstra (Intel) 89352f64909SPeter Zijlstra (Intel) #define MSR_TSX_FORCE_ABORT 0x0000010F 89452f64909SPeter Zijlstra (Intel) 89552f64909SPeter Zijlstra (Intel) #define MSR_TFA_RTM_FORCE_ABORT_BIT 0 89652f64909SPeter Zijlstra (Intel) #define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) 8971348924bSPawan Gupta #define MSR_TFA_TSX_CPUID_CLEAR_BIT 1 8981348924bSPawan Gupta #define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT) 8991348924bSPawan Gupta #define MSR_TFA_SDV_ENABLE_RTM_BIT 2 9001348924bSPawan Gupta #define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT) 90152f64909SPeter Zijlstra (Intel) 902b72e7464SBorislav Petkov /* P4/Xeon+ specific */ 903b72e7464SBorislav Petkov #define MSR_IA32_MCG_EAX 0x00000180 904b72e7464SBorislav Petkov #define MSR_IA32_MCG_EBX 0x00000181 905b72e7464SBorislav Petkov #define MSR_IA32_MCG_ECX 0x00000182 906b72e7464SBorislav Petkov #define MSR_IA32_MCG_EDX 0x00000183 907b72e7464SBorislav Petkov #define MSR_IA32_MCG_ESI 0x00000184 908b72e7464SBorislav Petkov #define MSR_IA32_MCG_EDI 0x00000185 909b72e7464SBorislav Petkov #define MSR_IA32_MCG_EBP 0x00000186 910b72e7464SBorislav Petkov #define MSR_IA32_MCG_ESP 0x00000187 911b72e7464SBorislav Petkov #define MSR_IA32_MCG_EFLAGS 0x00000188 912b72e7464SBorislav Petkov #define MSR_IA32_MCG_EIP 0x00000189 913b72e7464SBorislav Petkov #define MSR_IA32_MCG_RESERVED 0x0000018a 914b72e7464SBorislav Petkov 915b72e7464SBorislav Petkov /* Pentium IV performance counter MSRs */ 916b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR0 0x00000300 917b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR1 0x00000301 918b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR2 0x00000302 919b72e7464SBorislav Petkov #define MSR_P4_BPU_PERFCTR3 0x00000303 920b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR0 0x00000304 921b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR1 0x00000305 922b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR2 0x00000306 923b72e7464SBorislav Petkov #define MSR_P4_MS_PERFCTR3 0x00000307 924b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR0 0x00000308 925b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR1 0x00000309 926b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR2 0x0000030a 927b72e7464SBorislav Petkov #define MSR_P4_FLAME_PERFCTR3 0x0000030b 928b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR0 0x0000030c 929b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR1 0x0000030d 930b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR2 0x0000030e 931b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR3 0x0000030f 932b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR4 0x00000310 933b72e7464SBorislav Petkov #define MSR_P4_IQ_PERFCTR5 0x00000311 934b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR0 0x00000360 935b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR1 0x00000361 936b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR2 0x00000362 937b72e7464SBorislav Petkov #define MSR_P4_BPU_CCCR3 0x00000363 938b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR0 0x00000364 939b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR1 0x00000365 940b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR2 0x00000366 941b72e7464SBorislav Petkov #define MSR_P4_MS_CCCR3 0x00000367 942b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR0 0x00000368 943b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR1 0x00000369 944b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR2 0x0000036a 945b72e7464SBorislav Petkov #define MSR_P4_FLAME_CCCR3 0x0000036b 946b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR0 0x0000036c 947b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR1 0x0000036d 948b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR2 0x0000036e 949b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR3 0x0000036f 950b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR4 0x00000370 951b72e7464SBorislav Petkov #define MSR_P4_IQ_CCCR5 0x00000371 952b72e7464SBorislav Petkov #define MSR_P4_ALF_ESCR0 0x000003ca 953b72e7464SBorislav Petkov #define MSR_P4_ALF_ESCR1 0x000003cb 954b72e7464SBorislav Petkov #define MSR_P4_BPU_ESCR0 0x000003b2 955b72e7464SBorislav Petkov #define MSR_P4_BPU_ESCR1 0x000003b3 956b72e7464SBorislav Petkov #define MSR_P4_BSU_ESCR0 0x000003a0 957b72e7464SBorislav Petkov #define MSR_P4_BSU_ESCR1 0x000003a1 958b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR0 0x000003b8 959b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR1 0x000003b9 960b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR2 0x000003cc 961b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR3 0x000003cd 962b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR4 0x000003e0 963b72e7464SBorislav Petkov #define MSR_P4_CRU_ESCR5 0x000003e1 964b72e7464SBorislav Petkov #define MSR_P4_DAC_ESCR0 0x000003a8 965b72e7464SBorislav Petkov #define MSR_P4_DAC_ESCR1 0x000003a9 966b72e7464SBorislav Petkov #define MSR_P4_FIRM_ESCR0 0x000003a4 967b72e7464SBorislav Petkov #define MSR_P4_FIRM_ESCR1 0x000003a5 968b72e7464SBorislav Petkov #define MSR_P4_FLAME_ESCR0 0x000003a6 969b72e7464SBorislav Petkov #define MSR_P4_FLAME_ESCR1 0x000003a7 970b72e7464SBorislav Petkov #define MSR_P4_FSB_ESCR0 0x000003a2 971b72e7464SBorislav Petkov #define MSR_P4_FSB_ESCR1 0x000003a3 972b72e7464SBorislav Petkov #define MSR_P4_IQ_ESCR0 0x000003ba 973b72e7464SBorislav Petkov #define MSR_P4_IQ_ESCR1 0x000003bb 974b72e7464SBorislav Petkov #define MSR_P4_IS_ESCR0 0x000003b4 975b72e7464SBorislav Petkov #define MSR_P4_IS_ESCR1 0x000003b5 976b72e7464SBorislav Petkov #define MSR_P4_ITLB_ESCR0 0x000003b6 977b72e7464SBorislav Petkov #define MSR_P4_ITLB_ESCR1 0x000003b7 978b72e7464SBorislav Petkov #define MSR_P4_IX_ESCR0 0x000003c8 979b72e7464SBorislav Petkov #define MSR_P4_IX_ESCR1 0x000003c9 980b72e7464SBorislav Petkov #define MSR_P4_MOB_ESCR0 0x000003aa 981b72e7464SBorislav Petkov #define MSR_P4_MOB_ESCR1 0x000003ab 982b72e7464SBorislav Petkov #define MSR_P4_MS_ESCR0 0x000003c0 983b72e7464SBorislav Petkov #define MSR_P4_MS_ESCR1 0x000003c1 984b72e7464SBorislav Petkov #define MSR_P4_PMH_ESCR0 0x000003ac 985b72e7464SBorislav Petkov #define MSR_P4_PMH_ESCR1 0x000003ad 986b72e7464SBorislav Petkov #define MSR_P4_RAT_ESCR0 0x000003bc 987b72e7464SBorislav Petkov #define MSR_P4_RAT_ESCR1 0x000003bd 988b72e7464SBorislav Petkov #define MSR_P4_SAAT_ESCR0 0x000003ae 989b72e7464SBorislav Petkov #define MSR_P4_SAAT_ESCR1 0x000003af 990b72e7464SBorislav Petkov #define MSR_P4_SSU_ESCR0 0x000003be 991b72e7464SBorislav Petkov #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 992b72e7464SBorislav Petkov 993b72e7464SBorislav Petkov #define MSR_P4_TBPU_ESCR0 0x000003c2 994b72e7464SBorislav Petkov #define MSR_P4_TBPU_ESCR1 0x000003c3 995b72e7464SBorislav Petkov #define MSR_P4_TC_ESCR0 0x000003c4 996b72e7464SBorislav Petkov #define MSR_P4_TC_ESCR1 0x000003c5 997b72e7464SBorislav Petkov #define MSR_P4_U2L_ESCR0 0x000003b0 998b72e7464SBorislav Petkov #define MSR_P4_U2L_ESCR1 0x000003b1 999b72e7464SBorislav Petkov 1000b72e7464SBorislav Petkov #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 1001b72e7464SBorislav Petkov 1002b72e7464SBorislav Petkov /* Intel Core-based CPU performance counters */ 1003b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 1004b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 1005b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 10067b2c05a1SKan Liang #define MSR_CORE_PERF_FIXED_CTR3 0x0000030c 1007b72e7464SBorislav Petkov #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 1008b72e7464SBorislav Petkov #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 1009b72e7464SBorislav Petkov #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 1010b72e7464SBorislav Petkov #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 1011b72e7464SBorislav Petkov 101259a854e2SKan Liang #define MSR_PERF_METRICS 0x00000329 101359a854e2SKan Liang 10148479e04eSLuwei Kang /* PERF_GLOBAL_OVF_CTL bits */ 10158479e04eSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55 10168479e04eSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT) 1017c715eb9fSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62 1018c715eb9fSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT) 1019c715eb9fSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 1020c715eb9fSLuwei Kang #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) 10218479e04eSLuwei Kang 1022b72e7464SBorislav Petkov /* Geode defined MSRs */ 1023b72e7464SBorislav Petkov #define MSR_GEODE_BUSCONT_CONF0 0x00001900 1024b72e7464SBorislav Petkov 1025b72e7464SBorislav Petkov /* Intel VT MSRs */ 1026b72e7464SBorislav Petkov #define MSR_IA32_VMX_BASIC 0x00000480 1027b72e7464SBorislav Petkov #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 1028b72e7464SBorislav Petkov #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 1029b72e7464SBorislav Petkov #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 1030b72e7464SBorislav Petkov #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 1031b72e7464SBorislav Petkov #define MSR_IA32_VMX_MISC 0x00000485 1032b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 1033b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 1034b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 1035b72e7464SBorislav Petkov #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 1036b72e7464SBorislav Petkov #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 1037b72e7464SBorislav Petkov #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 1038b72e7464SBorislav Petkov #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 1039b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 1040b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 1041b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 1042b72e7464SBorislav Petkov #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 1043b72e7464SBorislav Petkov #define MSR_IA32_VMX_VMFUNC 0x00000491 1044465932dbSRobert Hoo #define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492 1045b72e7464SBorislav Petkov 1046b72e7464SBorislav Petkov /* VMX_BASIC bits and bitmasks */ 1047b72e7464SBorislav Petkov #define VMX_BASIC_VMCS_SIZE_SHIFT 32 1048b72e7464SBorislav Petkov #define VMX_BASIC_TRUE_CTLS (1ULL << 55) 1049b72e7464SBorislav Petkov #define VMX_BASIC_64 0x0001000000000000LLU 1050b72e7464SBorislav Petkov #define VMX_BASIC_MEM_TYPE_SHIFT 50 1051b72e7464SBorislav Petkov #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 1052b72e7464SBorislav Petkov #define VMX_BASIC_MEM_TYPE_WB 6LLU 1053b72e7464SBorislav Petkov #define VMX_BASIC_INOUT 0x0040000000000000LLU 1054b72e7464SBorislav Petkov 105597fa21f6SBorislav Petkov /* Resctrl MSRs: */ 105697fa21f6SBorislav Petkov /* - Intel: */ 105797fa21f6SBorislav Petkov #define MSR_IA32_L3_QOS_CFG 0xc81 105897fa21f6SBorislav Petkov #define MSR_IA32_L2_QOS_CFG 0xc82 105997fa21f6SBorislav Petkov #define MSR_IA32_QM_EVTSEL 0xc8d 106097fa21f6SBorislav Petkov #define MSR_IA32_QM_CTR 0xc8e 106197fa21f6SBorislav Petkov #define MSR_IA32_PQR_ASSOC 0xc8f 106297fa21f6SBorislav Petkov #define MSR_IA32_L3_CBM_BASE 0xc90 106397fa21f6SBorislav Petkov #define MSR_IA32_L2_CBM_BASE 0xd10 106497fa21f6SBorislav Petkov #define MSR_IA32_MBA_THRTL_BASE 0xd50 106597fa21f6SBorislav Petkov 106697fa21f6SBorislav Petkov /* - AMD: */ 106797fa21f6SBorislav Petkov #define MSR_IA32_MBA_BW_BASE 0xc0000200 106897fa21f6SBorislav Petkov 1069b72e7464SBorislav Petkov /* MSR_IA32_VMX_MISC bits */ 1070f99e3dafSChao Peng #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) 1071b72e7464SBorislav Petkov #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 1072b72e7464SBorislav Petkov #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 1073b72e7464SBorislav Petkov /* AMD-V MSRs */ 1074b72e7464SBorislav Petkov 1075b72e7464SBorislav Petkov #define MSR_VM_CR 0xc0010114 1076b72e7464SBorislav Petkov #define MSR_VM_IGNNE 0xc0010115 1077b72e7464SBorislav Petkov #define MSR_VM_HSAVE_PA 0xc0010117 1078b72e7464SBorislav Petkov 10797b8f40b3SRicardo Neri /* Hardware Feedback Interface */ 10807b8f40b3SRicardo Neri #define MSR_IA32_HW_FEEDBACK_PTR 0x17d0 10817b8f40b3SRicardo Neri #define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1 10827b8f40b3SRicardo Neri 1083b8d1d163SDaniel Sneddon /* x2APIC locked status */ 1084b8d1d163SDaniel Sneddon #define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD 1085b8d1d163SDaniel Sneddon #define LEGACY_XAPIC_DISABLED BIT(0) /* 1086b8d1d163SDaniel Sneddon * x2APIC mode is locked and 1087b8d1d163SDaniel Sneddon * disabling x2APIC will cause 1088b8d1d163SDaniel Sneddon * a #GP 1089b8d1d163SDaniel Sneddon */ 1090b8d1d163SDaniel Sneddon 1091b72e7464SBorislav Petkov #endif /* _ASM_X86_MSR_INDEX_H */ 1092