1 #ifndef _ASM_X86_MPSPEC_DEF_H 2 #define _ASM_X86_MPSPEC_DEF_H 3 4 /* 5 * Structure definitions for SMP machines following the 6 * Intel Multiprocessing Specification 1.1 and 1.4. 7 */ 8 9 /* 10 * This tag identifies where the SMP configuration 11 * information is. 12 */ 13 14 #define SMP_MAGIC_IDENT (('_'<<24) | ('P'<<16) | ('M'<<8) | '_') 15 16 #ifdef CONFIG_X86_32 17 # define MAX_MPC_ENTRY 1024 18 # define MAX_APICS 256 19 #else 20 # if NR_CPUS <= 255 21 # define MAX_APICS 255 22 # else 23 # define MAX_APICS 32768 24 # endif 25 #endif 26 27 /* Intel MP Floating Pointer Structure */ 28 struct mpf_intel { 29 char signature[4]; /* "_MP_" */ 30 unsigned int physptr; /* Configuration table address */ 31 unsigned char length; /* Our length (paragraphs) */ 32 unsigned char specification; /* Specification version */ 33 unsigned char checksum; /* Checksum (makes sum 0) */ 34 unsigned char feature1; /* Standard or configuration ? */ 35 unsigned char feature2; /* Bit7 set for IMCR|PIC */ 36 unsigned char feature3; /* Unused (0) */ 37 unsigned char feature4; /* Unused (0) */ 38 unsigned char feature5; /* Unused (0) */ 39 }; 40 41 #define MPC_SIGNATURE "PCMP" 42 43 struct mpc_table { 44 char signature[4]; 45 unsigned short length; /* Size of table */ 46 char spec; /* 0x01 */ 47 char checksum; 48 char oem[8]; 49 char productid[12]; 50 unsigned int oemptr; /* 0 if not present */ 51 unsigned short oemsize; /* 0 if not present */ 52 unsigned short oemcount; 53 unsigned int lapic; /* APIC address */ 54 unsigned int reserved; 55 }; 56 57 /* Followed by entries */ 58 59 #define MP_PROCESSOR 0 60 #define MP_BUS 1 61 #define MP_IOAPIC 2 62 #define MP_INTSRC 3 63 #define MP_LINTSRC 4 64 /* Used by IBM NUMA-Q to describe node locality */ 65 #define MP_TRANSLATION 192 66 67 #define CPU_ENABLED 1 /* Processor is available */ 68 #define CPU_BOOTPROCESSOR 2 /* Processor is the BP */ 69 70 #define CPU_STEPPING_MASK 0x000F 71 #define CPU_MODEL_MASK 0x00F0 72 #define CPU_FAMILY_MASK 0x0F00 73 74 struct mpc_cpu { 75 unsigned char type; 76 unsigned char apicid; /* Local APIC number */ 77 unsigned char apicver; /* Its versions */ 78 unsigned char cpuflag; 79 unsigned int cpufeature; 80 unsigned int featureflag; /* CPUID feature value */ 81 unsigned int reserved[2]; 82 }; 83 84 struct mpc_bus { 85 unsigned char type; 86 unsigned char busid; 87 unsigned char bustype[6]; 88 }; 89 90 /* List of Bus Type string values, Intel MP Spec. */ 91 #define BUSTYPE_EISA "EISA" 92 #define BUSTYPE_ISA "ISA" 93 #define BUSTYPE_INTERN "INTERN" /* Internal BUS */ 94 #define BUSTYPE_MCA "MCA" 95 #define BUSTYPE_VL "VL" /* Local bus */ 96 #define BUSTYPE_PCI "PCI" 97 #define BUSTYPE_PCMCIA "PCMCIA" 98 #define BUSTYPE_CBUS "CBUS" 99 #define BUSTYPE_CBUSII "CBUSII" 100 #define BUSTYPE_FUTURE "FUTURE" 101 #define BUSTYPE_MBI "MBI" 102 #define BUSTYPE_MBII "MBII" 103 #define BUSTYPE_MPI "MPI" 104 #define BUSTYPE_MPSA "MPSA" 105 #define BUSTYPE_NUBUS "NUBUS" 106 #define BUSTYPE_TC "TC" 107 #define BUSTYPE_VME "VME" 108 #define BUSTYPE_XPRESS "XPRESS" 109 110 #define MPC_APIC_USABLE 0x01 111 112 struct mpc_ioapic { 113 unsigned char type; 114 unsigned char apicid; 115 unsigned char apicver; 116 unsigned char flags; 117 unsigned int apicaddr; 118 }; 119 120 struct mpc_intsrc { 121 unsigned char type; 122 unsigned char irqtype; 123 unsigned short irqflag; 124 unsigned char srcbus; 125 unsigned char srcbusirq; 126 unsigned char dstapic; 127 unsigned char dstirq; 128 }; 129 130 enum mp_irq_source_types { 131 mp_INT = 0, 132 mp_NMI = 1, 133 mp_SMI = 2, 134 mp_ExtINT = 3 135 }; 136 137 #define MP_IRQDIR_DEFAULT 0 138 #define MP_IRQDIR_HIGH 1 139 #define MP_IRQDIR_LOW 3 140 141 #define MP_APIC_ALL 0xFF 142 143 struct mpc_lintsrc { 144 unsigned char type; 145 unsigned char irqtype; 146 unsigned short irqflag; 147 unsigned char srcbusid; 148 unsigned char srcbusirq; 149 unsigned char destapic; 150 unsigned char destapiclint; 151 }; 152 153 #define MPC_OEM_SIGNATURE "_OEM" 154 155 struct mpc_oemtable { 156 char signature[4]; 157 unsigned short length; /* Size of table */ 158 char rev; /* 0x01 */ 159 char checksum; 160 char mpc[8]; 161 }; 162 163 /* 164 * Default configurations 165 * 166 * 1 2 CPU ISA 82489DX 167 * 2 2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining 168 * 3 2 CPU EISA 82489DX 169 * 4 2 CPU MCA 82489DX 170 * 5 2 CPU ISA+PCI 171 * 6 2 CPU EISA+PCI 172 * 7 2 CPU MCA+PCI 173 */ 174 175 enum mp_bustype { 176 MP_BUS_ISA = 1, 177 MP_BUS_EISA, 178 MP_BUS_PCI, 179 MP_BUS_MCA, 180 }; 181 #endif /* _ASM_X86_MPSPEC_DEF_H */ 182