1 #ifndef _ASM_X86_MPSPEC_H 2 #define _ASM_X86_MPSPEC_H 3 4 #include <linux/init.h> 5 6 #include <asm/mpspec_def.h> 7 8 extern int apic_version[MAX_APICS]; 9 10 #ifdef CONFIG_X86_32 11 #include <mach_mpspec.h> 12 13 extern unsigned int def_to_bigsmp; 14 extern u8 apicid_2_node[]; 15 extern int pic_mode; 16 17 #ifdef CONFIG_X86_NUMAQ 18 extern int mp_bus_id_to_node[MAX_MP_BUSSES]; 19 extern int mp_bus_id_to_local[MAX_MP_BUSSES]; 20 extern int quad_local_to_mp_bus_id [NR_CPUS/4][4]; 21 #endif 22 23 #define MAX_APICID 256 24 25 #else 26 27 #define MAX_MP_BUSSES 256 28 /* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */ 29 #define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4) 30 31 #endif 32 33 extern void early_find_smp_config(void); 34 extern void early_get_smp_config(void); 35 36 #if defined(CONFIG_MCA) || defined(CONFIG_EISA) 37 extern int mp_bus_id_to_type[MAX_MP_BUSSES]; 38 #endif 39 40 extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); 41 42 extern unsigned int boot_cpu_physical_apicid; 43 extern unsigned int max_physical_apicid; 44 extern int smp_found_config; 45 extern int mpc_default_type; 46 extern unsigned long mp_lapic_addr; 47 48 extern void find_smp_config(void); 49 extern void get_smp_config(void); 50 #ifdef CONFIG_X86_MPPARSE 51 extern void early_reserve_e820_mpc_new(void); 52 #else 53 static inline void early_reserve_e820_mpc_new(void) { } 54 #endif 55 56 void __cpuinit generic_processor_info(int apicid, int version); 57 #ifdef CONFIG_ACPI 58 extern void mp_register_ioapic(int id, u32 address, u32 gsi_base); 59 extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, 60 u32 gsi); 61 extern void mp_config_acpi_legacy_irqs(void); 62 extern int mp_register_gsi(u32 gsi, int edge_level, int active_high_low); 63 #ifdef CONFIG_X86_IO_APIC 64 extern int mp_config_acpi_gsi(unsigned char number, unsigned int devfn, u8 pin, 65 u32 gsi, int triggering, int polarity); 66 #else 67 static inline int 68 mp_config_acpi_gsi(unsigned char number, unsigned int devfn, u8 pin, 69 u32 gsi, int triggering, int polarity) 70 { 71 return 0; 72 } 73 #endif 74 #endif /* CONFIG_ACPI */ 75 76 #define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS) 77 78 struct physid_mask { 79 unsigned long mask[PHYSID_ARRAY_SIZE]; 80 }; 81 82 typedef struct physid_mask physid_mask_t; 83 84 #define physid_set(physid, map) set_bit(physid, (map).mask) 85 #define physid_clear(physid, map) clear_bit(physid, (map).mask) 86 #define physid_isset(physid, map) test_bit(physid, (map).mask) 87 #define physid_test_and_set(physid, map) \ 88 test_and_set_bit(physid, (map).mask) 89 90 #define physids_and(dst, src1, src2) \ 91 bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS) 92 93 #define physids_or(dst, src1, src2) \ 94 bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS) 95 96 #define physids_clear(map) \ 97 bitmap_zero((map).mask, MAX_APICS) 98 99 #define physids_complement(dst, src) \ 100 bitmap_complement((dst).mask, (src).mask, MAX_APICS) 101 102 #define physids_empty(map) \ 103 bitmap_empty((map).mask, MAX_APICS) 104 105 #define physids_equal(map1, map2) \ 106 bitmap_equal((map1).mask, (map2).mask, MAX_APICS) 107 108 #define physids_weight(map) \ 109 bitmap_weight((map).mask, MAX_APICS) 110 111 #define physids_shift_right(d, s, n) \ 112 bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS) 113 114 #define physids_shift_left(d, s, n) \ 115 bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS) 116 117 #define physids_coerce(map) ((map).mask[0]) 118 119 #define physids_promote(physids) \ 120 ({ \ 121 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ 122 __physid_mask.mask[0] = physids; \ 123 __physid_mask; \ 124 }) 125 126 /* Note: will create very large stack frames if physid_mask_t is big */ 127 #define physid_mask_of_physid(physid) \ 128 ({ \ 129 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ 130 physid_set(physid, __physid_mask); \ 131 __physid_mask; \ 132 }) 133 134 static inline void physid_set_mask_of_physid(int physid, physid_mask_t *map) 135 { 136 physids_clear(*map); 137 physid_set(physid, *map); 138 } 139 140 #define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} } 141 #define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} } 142 143 extern physid_mask_t phys_cpu_present_map; 144 145 #endif /* _ASM_X86_MPSPEC_H */ 146