1 #ifndef _ASM_X86_MPSPEC_H 2 #define _ASM_X86_MPSPEC_H 3 4 #include <linux/init.h> 5 6 #include <asm/mpspec_def.h> 7 8 extern int apic_version[MAX_APICS]; 9 extern int pic_mode; 10 11 #ifdef CONFIG_X86_32 12 13 /* 14 * Summit or generic (i.e. installer) kernels need lots of bus entries. 15 * Maximum 256 PCI busses, plus 1 ISA bus in each of 4 cabinets. 16 */ 17 #if CONFIG_BASE_SMALL == 0 18 # define MAX_MP_BUSSES 260 19 #else 20 # define MAX_MP_BUSSES 32 21 #endif 22 23 #define MAX_IRQ_SOURCES 256 24 25 extern unsigned int def_to_bigsmp; 26 extern u8 apicid_2_node[]; 27 28 #ifdef CONFIG_X86_NUMAQ 29 extern int mp_bus_id_to_node[MAX_MP_BUSSES]; 30 extern int mp_bus_id_to_local[MAX_MP_BUSSES]; 31 extern int quad_local_to_mp_bus_id [NR_CPUS/4][4]; 32 #endif 33 34 #define MAX_APICID 256 35 36 #else /* CONFIG_X86_64: */ 37 38 #define MAX_MP_BUSSES 256 39 /* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */ 40 #define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4) 41 42 #endif /* CONFIG_X86_64 */ 43 44 extern void early_find_smp_config(void); 45 extern void early_get_smp_config(void); 46 47 #if defined(CONFIG_MCA) || defined(CONFIG_EISA) 48 extern int mp_bus_id_to_type[MAX_MP_BUSSES]; 49 #endif 50 51 extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); 52 53 extern unsigned int boot_cpu_physical_apicid; 54 extern unsigned int max_physical_apicid; 55 extern int smp_found_config; 56 extern int mpc_default_type; 57 extern unsigned long mp_lapic_addr; 58 59 extern void get_smp_config(void); 60 61 #ifdef CONFIG_X86_MPPARSE 62 extern void find_smp_config(void); 63 extern void early_reserve_e820_mpc_new(void); 64 #else 65 static inline void find_smp_config(void) { } 66 static inline void early_reserve_e820_mpc_new(void) { } 67 #endif 68 69 void __cpuinit generic_processor_info(int apicid, int version); 70 #ifdef CONFIG_ACPI 71 extern void mp_register_ioapic(int id, u32 address, u32 gsi_base); 72 extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, 73 u32 gsi); 74 extern void mp_config_acpi_legacy_irqs(void); 75 extern int mp_register_gsi(u32 gsi, int edge_level, int active_high_low); 76 extern int acpi_probe_gsi(void); 77 #ifdef CONFIG_X86_IO_APIC 78 extern int mp_config_acpi_gsi(unsigned char number, unsigned int devfn, u8 pin, 79 u32 gsi, int triggering, int polarity); 80 extern int mp_find_ioapic(int gsi); 81 extern int mp_find_ioapic_pin(int ioapic, int gsi); 82 #else 83 static inline int 84 mp_config_acpi_gsi(unsigned char number, unsigned int devfn, u8 pin, 85 u32 gsi, int triggering, int polarity) 86 { 87 return 0; 88 } 89 #endif 90 #else /* !CONFIG_ACPI: */ 91 static inline int acpi_probe_gsi(void) 92 { 93 return 0; 94 } 95 #endif /* CONFIG_ACPI */ 96 97 #define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS) 98 99 struct physid_mask { 100 unsigned long mask[PHYSID_ARRAY_SIZE]; 101 }; 102 103 typedef struct physid_mask physid_mask_t; 104 105 #define physid_set(physid, map) set_bit(physid, (map).mask) 106 #define physid_clear(physid, map) clear_bit(physid, (map).mask) 107 #define physid_isset(physid, map) test_bit(physid, (map).mask) 108 #define physid_test_and_set(physid, map) \ 109 test_and_set_bit(physid, (map).mask) 110 111 #define physids_and(dst, src1, src2) \ 112 bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS) 113 114 #define physids_or(dst, src1, src2) \ 115 bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS) 116 117 #define physids_clear(map) \ 118 bitmap_zero((map).mask, MAX_APICS) 119 120 #define physids_complement(dst, src) \ 121 bitmap_complement((dst).mask, (src).mask, MAX_APICS) 122 123 #define physids_empty(map) \ 124 bitmap_empty((map).mask, MAX_APICS) 125 126 #define physids_equal(map1, map2) \ 127 bitmap_equal((map1).mask, (map2).mask, MAX_APICS) 128 129 #define physids_weight(map) \ 130 bitmap_weight((map).mask, MAX_APICS) 131 132 #define physids_shift_right(d, s, n) \ 133 bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS) 134 135 #define physids_shift_left(d, s, n) \ 136 bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS) 137 138 #define physids_coerce(map) ((map).mask[0]) 139 140 #define physids_promote(physids) \ 141 ({ \ 142 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ 143 __physid_mask.mask[0] = physids; \ 144 __physid_mask; \ 145 }) 146 147 /* Note: will create very large stack frames if physid_mask_t is big */ 148 #define physid_mask_of_physid(physid) \ 149 ({ \ 150 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ 151 physid_set(physid, __physid_mask); \ 152 __physid_mask; \ 153 }) 154 155 static inline void physid_set_mask_of_physid(int physid, physid_mask_t *map) 156 { 157 physids_clear(*map); 158 physid_set(physid, *map); 159 } 160 161 #define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} } 162 #define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} } 163 164 extern physid_mask_t phys_cpu_present_map; 165 166 extern int generic_mps_oem_check(struct mpc_table *, char *, char *); 167 168 extern int default_acpi_madt_oem_check(char *, char *); 169 170 #endif /* _ASM_X86_MPSPEC_H */ 171