1 #ifndef _ASM_X86_MPSPEC_H 2 #define _ASM_X86_MPSPEC_H 3 4 #include <linux/init.h> 5 6 #include <asm/mpspec_def.h> 7 8 extern int apic_version[MAX_APICS]; 9 extern int pic_mode; 10 11 #ifdef CONFIG_X86_32 12 13 /* 14 * Summit or generic (i.e. installer) kernels need lots of bus entries. 15 * Maximum 256 PCI busses, plus 1 ISA bus in each of 4 cabinets. 16 */ 17 #if CONFIG_BASE_SMALL == 0 18 # define MAX_MP_BUSSES 260 19 #else 20 # define MAX_MP_BUSSES 32 21 #endif 22 23 #define MAX_IRQ_SOURCES 256 24 25 extern unsigned int def_to_bigsmp; 26 extern u8 apicid_2_node[]; 27 28 #ifdef CONFIG_X86_NUMAQ 29 extern int mp_bus_id_to_node[MAX_MP_BUSSES]; 30 extern int mp_bus_id_to_local[MAX_MP_BUSSES]; 31 extern int quad_local_to_mp_bus_id [NR_CPUS/4][4]; 32 #endif 33 34 #define MAX_APICID 256 35 36 #else /* CONFIG_X86_64: */ 37 38 #define MAX_MP_BUSSES 256 39 /* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */ 40 #define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4) 41 42 #endif /* CONFIG_X86_64 */ 43 44 extern void early_find_smp_config(void); 45 extern void early_get_smp_config(void); 46 47 #if defined(CONFIG_MCA) || defined(CONFIG_EISA) 48 extern int mp_bus_id_to_type[MAX_MP_BUSSES]; 49 #endif 50 51 extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); 52 53 extern unsigned int boot_cpu_physical_apicid; 54 extern unsigned int max_physical_apicid; 55 extern int smp_found_config; 56 extern int mpc_default_type; 57 extern unsigned long mp_lapic_addr; 58 59 extern void get_smp_config(void); 60 61 #ifdef CONFIG_X86_MPPARSE 62 extern void find_smp_config(void); 63 extern void early_reserve_e820_mpc_new(void); 64 extern int enable_update_mptable; 65 #else 66 static inline void find_smp_config(void) { } 67 static inline void early_reserve_e820_mpc_new(void) { } 68 #define enable_update_mptable 0 69 #endif 70 71 void __cpuinit generic_processor_info(int apicid, int version); 72 #ifdef CONFIG_ACPI 73 extern void mp_register_ioapic(int id, u32 address, u32 gsi_base); 74 extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, 75 u32 gsi); 76 extern void mp_config_acpi_legacy_irqs(void); 77 struct device; 78 extern int mp_register_gsi(struct device *dev, u32 gsi, int edge_level, 79 int active_high_low); 80 extern int acpi_probe_gsi(void); 81 #ifdef CONFIG_X86_IO_APIC 82 extern int mp_find_ioapic(int gsi); 83 extern int mp_find_ioapic_pin(int ioapic, int gsi); 84 #endif 85 #else /* !CONFIG_ACPI: */ 86 static inline int acpi_probe_gsi(void) 87 { 88 return 0; 89 } 90 #endif /* CONFIG_ACPI */ 91 92 #define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS) 93 94 struct physid_mask { 95 unsigned long mask[PHYSID_ARRAY_SIZE]; 96 }; 97 98 typedef struct physid_mask physid_mask_t; 99 100 #define physid_set(physid, map) set_bit(physid, (map).mask) 101 #define physid_clear(physid, map) clear_bit(physid, (map).mask) 102 #define physid_isset(physid, map) test_bit(physid, (map).mask) 103 #define physid_test_and_set(physid, map) \ 104 test_and_set_bit(physid, (map).mask) 105 106 #define physids_and(dst, src1, src2) \ 107 bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS) 108 109 #define physids_or(dst, src1, src2) \ 110 bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS) 111 112 #define physids_clear(map) \ 113 bitmap_zero((map).mask, MAX_APICS) 114 115 #define physids_complement(dst, src) \ 116 bitmap_complement((dst).mask, (src).mask, MAX_APICS) 117 118 #define physids_empty(map) \ 119 bitmap_empty((map).mask, MAX_APICS) 120 121 #define physids_equal(map1, map2) \ 122 bitmap_equal((map1).mask, (map2).mask, MAX_APICS) 123 124 #define physids_weight(map) \ 125 bitmap_weight((map).mask, MAX_APICS) 126 127 #define physids_shift_right(d, s, n) \ 128 bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS) 129 130 #define physids_shift_left(d, s, n) \ 131 bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS) 132 133 #define physids_coerce(map) ((map).mask[0]) 134 135 #define physids_promote(physids) \ 136 ({ \ 137 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ 138 __physid_mask.mask[0] = physids; \ 139 __physid_mask; \ 140 }) 141 142 /* Note: will create very large stack frames if physid_mask_t is big */ 143 #define physid_mask_of_physid(physid) \ 144 ({ \ 145 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ 146 physid_set(physid, __physid_mask); \ 147 __physid_mask; \ 148 }) 149 150 static inline void physid_set_mask_of_physid(int physid, physid_mask_t *map) 151 { 152 physids_clear(*map); 153 physid_set(physid, *map); 154 } 155 156 #define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} } 157 #define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} } 158 159 extern physid_mask_t phys_cpu_present_map; 160 161 extern int generic_mps_oem_check(struct mpc_table *, char *, char *); 162 163 extern int default_acpi_madt_oem_check(char *, char *); 164 165 #endif /* _ASM_X86_MPSPEC_H */ 166