xref: /openbmc/linux/arch/x86/include/asm/mpspec.h (revision 4800cd83)
1 #ifndef _ASM_X86_MPSPEC_H
2 #define _ASM_X86_MPSPEC_H
3 
4 #include <linux/init.h>
5 
6 #include <asm/mpspec_def.h>
7 #include <asm/x86_init.h>
8 #include <asm/apicdef.h>
9 
10 extern int apic_version[];
11 extern int pic_mode;
12 
13 #ifdef CONFIG_X86_32
14 
15 /*
16  * Summit or generic (i.e. installer) kernels need lots of bus entries.
17  * Maximum 256 PCI busses, plus 1 ISA bus in each of 4 cabinets.
18  */
19 #if CONFIG_BASE_SMALL == 0
20 # define MAX_MP_BUSSES		260
21 #else
22 # define MAX_MP_BUSSES		32
23 #endif
24 
25 #define MAX_IRQ_SOURCES		256
26 
27 extern unsigned int def_to_bigsmp;
28 extern u8 apicid_2_node[];
29 
30 #ifdef CONFIG_X86_NUMAQ
31 extern int mp_bus_id_to_node[MAX_MP_BUSSES];
32 extern int mp_bus_id_to_local[MAX_MP_BUSSES];
33 extern int quad_local_to_mp_bus_id [NR_CPUS/4][4];
34 #endif
35 
36 #define MAX_APICID		256
37 
38 #else /* CONFIG_X86_64: */
39 
40 #define MAX_MP_BUSSES		256
41 /* Each PCI slot may be a combo card with its own bus.  4 IRQ pins per slot. */
42 #define MAX_IRQ_SOURCES		(MAX_MP_BUSSES * 4)
43 
44 #endif /* CONFIG_X86_64 */
45 
46 #if defined(CONFIG_MCA) || defined(CONFIG_EISA)
47 extern int mp_bus_id_to_type[MAX_MP_BUSSES];
48 #endif
49 
50 extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
51 
52 extern unsigned int boot_cpu_physical_apicid;
53 extern unsigned int max_physical_apicid;
54 extern int mpc_default_type;
55 extern unsigned long mp_lapic_addr;
56 
57 #ifdef CONFIG_X86_LOCAL_APIC
58 extern int smp_found_config;
59 #else
60 # define smp_found_config 0
61 #endif
62 
63 static inline void get_smp_config(void)
64 {
65 	x86_init.mpparse.get_smp_config(0);
66 }
67 
68 static inline void early_get_smp_config(void)
69 {
70 	x86_init.mpparse.get_smp_config(1);
71 }
72 
73 static inline void find_smp_config(void)
74 {
75 	x86_init.mpparse.find_smp_config();
76 }
77 
78 #ifdef CONFIG_X86_MPPARSE
79 extern void early_reserve_e820_mpc_new(void);
80 extern int enable_update_mptable;
81 extern int default_mpc_apic_id(struct mpc_cpu *m);
82 extern void default_smp_read_mpc_oem(struct mpc_table *mpc);
83 # ifdef CONFIG_X86_IO_APIC
84 extern void default_mpc_oem_bus_info(struct mpc_bus *m, char *str);
85 # else
86 #  define default_mpc_oem_bus_info NULL
87 # endif
88 extern void default_find_smp_config(void);
89 extern void default_get_smp_config(unsigned int early);
90 #else
91 static inline void early_reserve_e820_mpc_new(void) { }
92 #define enable_update_mptable 0
93 #define default_mpc_apic_id NULL
94 #define default_smp_read_mpc_oem NULL
95 #define default_mpc_oem_bus_info NULL
96 #define default_find_smp_config x86_init_noop
97 #define default_get_smp_config x86_init_uint_noop
98 #endif
99 
100 void __cpuinit generic_processor_info(int apicid, int version);
101 #ifdef CONFIG_ACPI
102 extern void mp_register_ioapic(int id, u32 address, u32 gsi_base);
103 extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger,
104 				   u32 gsi);
105 extern void mp_config_acpi_legacy_irqs(void);
106 struct device;
107 extern int mp_register_gsi(struct device *dev, u32 gsi, int edge_level,
108 				 int active_high_low);
109 #endif /* CONFIG_ACPI */
110 
111 #define PHYSID_ARRAY_SIZE	BITS_TO_LONGS(MAX_LOCAL_APIC)
112 
113 struct physid_mask {
114 	unsigned long mask[PHYSID_ARRAY_SIZE];
115 };
116 
117 typedef struct physid_mask physid_mask_t;
118 
119 #define physid_set(physid, map)			set_bit(physid, (map).mask)
120 #define physid_clear(physid, map)		clear_bit(physid, (map).mask)
121 #define physid_isset(physid, map)		test_bit(physid, (map).mask)
122 #define physid_test_and_set(physid, map)			\
123 	test_and_set_bit(physid, (map).mask)
124 
125 #define physids_and(dst, src1, src2)					\
126 	bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC)
127 
128 #define physids_or(dst, src1, src2)					\
129 	bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC)
130 
131 #define physids_clear(map)					\
132 	bitmap_zero((map).mask, MAX_LOCAL_APIC)
133 
134 #define physids_complement(dst, src)				\
135 	bitmap_complement((dst).mask, (src).mask, MAX_LOCAL_APIC)
136 
137 #define physids_empty(map)					\
138 	bitmap_empty((map).mask, MAX_LOCAL_APIC)
139 
140 #define physids_equal(map1, map2)				\
141 	bitmap_equal((map1).mask, (map2).mask, MAX_LOCAL_APIC)
142 
143 #define physids_weight(map)					\
144 	bitmap_weight((map).mask, MAX_LOCAL_APIC)
145 
146 #define physids_shift_right(d, s, n)				\
147 	bitmap_shift_right((d).mask, (s).mask, n, MAX_LOCAL_APIC)
148 
149 #define physids_shift_left(d, s, n)				\
150 	bitmap_shift_left((d).mask, (s).mask, n, MAX_LOCAL_APIC)
151 
152 static inline unsigned long physids_coerce(physid_mask_t *map)
153 {
154 	return map->mask[0];
155 }
156 
157 static inline void physids_promote(unsigned long physids, physid_mask_t *map)
158 {
159 	physids_clear(*map);
160 	map->mask[0] = physids;
161 }
162 
163 static inline void physid_set_mask_of_physid(int physid, physid_mask_t *map)
164 {
165 	physids_clear(*map);
166 	physid_set(physid, *map);
167 }
168 
169 #define PHYSID_MASK_ALL		{ {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
170 #define PHYSID_MASK_NONE	{ {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
171 
172 extern physid_mask_t phys_cpu_present_map;
173 
174 extern int generic_mps_oem_check(struct mpc_table *, char *, char *);
175 
176 extern int default_acpi_madt_oem_check(char *, char *);
177 
178 #endif /* _ASM_X86_MPSPEC_H */
179