1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_MICROCODE_H 3 #define _ASM_X86_MICROCODE_H 4 5 #include <asm/cpu.h> 6 #include <linux/earlycpio.h> 7 #include <linux/initrd.h> 8 9 struct ucode_patch { 10 struct list_head plist; 11 void *data; /* Intel uses only this one */ 12 unsigned int size; 13 u32 patch_id; 14 u16 equiv_cpu; 15 }; 16 17 extern struct list_head microcode_cache; 18 19 struct cpu_signature { 20 unsigned int sig; 21 unsigned int pf; 22 unsigned int rev; 23 }; 24 25 struct device; 26 27 enum ucode_state { 28 UCODE_OK = 0, 29 UCODE_NEW, 30 UCODE_UPDATED, 31 UCODE_NFOUND, 32 UCODE_ERROR, 33 }; 34 35 struct microcode_ops { 36 enum ucode_state (*request_microcode_fw) (int cpu, struct device *, 37 bool refresh_fw); 38 39 void (*microcode_fini_cpu) (int cpu); 40 41 /* 42 * The generic 'microcode_core' part guarantees that 43 * the callbacks below run on a target cpu when they 44 * are being called. 45 * See also the "Synchronization" section in microcode_core.c. 46 */ 47 enum ucode_state (*apply_microcode) (int cpu); 48 int (*collect_cpu_info) (int cpu, struct cpu_signature *csig); 49 }; 50 51 struct ucode_cpu_info { 52 struct cpu_signature cpu_sig; 53 int valid; 54 void *mc; 55 }; 56 extern struct ucode_cpu_info ucode_cpu_info[]; 57 struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa); 58 59 #ifdef CONFIG_MICROCODE_INTEL 60 extern struct microcode_ops * __init init_intel_microcode(void); 61 #else 62 static inline struct microcode_ops * __init init_intel_microcode(void) 63 { 64 return NULL; 65 } 66 #endif /* CONFIG_MICROCODE_INTEL */ 67 68 #ifdef CONFIG_MICROCODE_AMD 69 extern struct microcode_ops * __init init_amd_microcode(void); 70 extern void __exit exit_amd_microcode(void); 71 #else 72 static inline struct microcode_ops * __init init_amd_microcode(void) 73 { 74 return NULL; 75 } 76 static inline void __exit exit_amd_microcode(void) {} 77 #endif 78 79 #define MAX_UCODE_COUNT 128 80 81 #define QCHAR(a, b, c, d) ((a) + ((b) << 8) + ((c) << 16) + ((d) << 24)) 82 #define CPUID_INTEL1 QCHAR('G', 'e', 'n', 'u') 83 #define CPUID_INTEL2 QCHAR('i', 'n', 'e', 'I') 84 #define CPUID_INTEL3 QCHAR('n', 't', 'e', 'l') 85 #define CPUID_AMD1 QCHAR('A', 'u', 't', 'h') 86 #define CPUID_AMD2 QCHAR('e', 'n', 't', 'i') 87 #define CPUID_AMD3 QCHAR('c', 'A', 'M', 'D') 88 89 #define CPUID_IS(a, b, c, ebx, ecx, edx) \ 90 (!((ebx ^ (a))|(edx ^ (b))|(ecx ^ (c)))) 91 92 /* 93 * In early loading microcode phase on BSP, boot_cpu_data is not set up yet. 94 * x86_cpuid_vendor() gets vendor id for BSP. 95 * 96 * In 32 bit AP case, accessing boot_cpu_data needs linear address. To simplify 97 * coding, we still use x86_cpuid_vendor() to get vendor id for AP. 98 * 99 * x86_cpuid_vendor() gets vendor information directly from CPUID. 100 */ 101 static inline int x86_cpuid_vendor(void) 102 { 103 u32 eax = 0x00000000; 104 u32 ebx, ecx = 0, edx; 105 106 native_cpuid(&eax, &ebx, &ecx, &edx); 107 108 if (CPUID_IS(CPUID_INTEL1, CPUID_INTEL2, CPUID_INTEL3, ebx, ecx, edx)) 109 return X86_VENDOR_INTEL; 110 111 if (CPUID_IS(CPUID_AMD1, CPUID_AMD2, CPUID_AMD3, ebx, ecx, edx)) 112 return X86_VENDOR_AMD; 113 114 return X86_VENDOR_UNKNOWN; 115 } 116 117 static inline unsigned int x86_cpuid_family(void) 118 { 119 u32 eax = 0x00000001; 120 u32 ebx, ecx = 0, edx; 121 122 native_cpuid(&eax, &ebx, &ecx, &edx); 123 124 return x86_family(eax); 125 } 126 127 #ifdef CONFIG_MICROCODE 128 extern void __init load_ucode_bsp(void); 129 extern void load_ucode_ap(void); 130 void reload_early_microcode(void); 131 extern bool initrd_gone; 132 void microcode_bsp_resume(void); 133 #else 134 static inline void __init load_ucode_bsp(void) { } 135 static inline void load_ucode_ap(void) { } 136 static inline void reload_early_microcode(void) { } 137 static inline void microcode_bsp_resume(void) { } 138 #endif 139 140 #endif /* _ASM_X86_MICROCODE_H */ 141