1 #ifndef _ASM_X86_MCE_H 2 #define _ASM_X86_MCE_H 3 4 #include <linux/types.h> 5 #include <asm/ioctls.h> 6 7 /* 8 * Machine Check support for x86 9 */ 10 11 /* MCG_CAP register defines */ 12 #define MCG_BANKCNT_MASK 0xff /* Number of Banks */ 13 #define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */ 14 #define MCG_EXT_P (1ULL<<9) /* Extended registers available */ 15 #define MCG_CMCI_P (1ULL<<10) /* CMCI supported */ 16 #define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */ 17 #define MCG_EXT_CNT_SHIFT 16 18 #define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT) 19 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 20 21 /* MCG_STATUS register defines */ 22 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 23 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 24 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 25 26 /* MCi_STATUS register defines */ 27 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 28 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 29 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 30 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 31 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 32 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 33 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 34 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 35 #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 36 #define MCACOD 0xffff /* MCA Error Code */ 37 38 /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */ 39 #define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */ 40 #define MCACOD_SCRUBMSK 0xfff0 41 #define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */ 42 #define MCACOD_DATA 0x0134 /* Data Load */ 43 #define MCACOD_INSTR 0x0150 /* Instruction Fetch */ 44 45 /* MCi_MISC register defines */ 46 #define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f) 47 #define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7) 48 #define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */ 49 #define MCI_MISC_ADDR_LINEAR 1 /* linear address */ 50 #define MCI_MISC_ADDR_PHYS 2 /* physical address */ 51 #define MCI_MISC_ADDR_MEM 3 /* memory address */ 52 #define MCI_MISC_ADDR_GENERIC 7 /* generic */ 53 54 /* CTL2 register defines */ 55 #define MCI_CTL2_CMCI_EN (1ULL << 30) 56 #define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL 57 58 #define MCJ_CTX_MASK 3 59 #define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK) 60 #define MCJ_CTX_RANDOM 0 /* inject context: random */ 61 #define MCJ_CTX_PROCESS 0x1 /* inject context: process */ 62 #define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */ 63 #define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */ 64 #define MCJ_EXCEPTION 0x8 /* raise as exception */ 65 #define MCJ_IRQ_BRAODCAST 0x10 /* do IRQ broadcasting */ 66 67 /* Fields are zero when not available */ 68 struct mce { 69 __u64 status; 70 __u64 misc; 71 __u64 addr; 72 __u64 mcgstatus; 73 __u64 ip; 74 __u64 tsc; /* cpu time stamp counter */ 75 __u64 time; /* wall time_t when error was detected */ 76 __u8 cpuvendor; /* cpu vendor as encoded in system.h */ 77 __u8 inject_flags; /* software inject flags */ 78 __u16 pad; 79 __u32 cpuid; /* CPUID 1 EAX */ 80 __u8 cs; /* code segment */ 81 __u8 bank; /* machine check bank */ 82 __u8 cpu; /* cpu number; obsolete; use extcpu now */ 83 __u8 finished; /* entry is valid */ 84 __u32 extcpu; /* linux cpu number that detected the error */ 85 __u32 socketid; /* CPU socket ID */ 86 __u32 apicid; /* CPU initial apic ID */ 87 __u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */ 88 }; 89 90 /* 91 * This structure contains all data related to the MCE log. Also 92 * carries a signature to make it easier to find from external 93 * debugging tools. Each entry is only valid when its finished flag 94 * is set. 95 */ 96 97 #define MCE_LOG_LEN 32 98 99 struct mce_log { 100 char signature[12]; /* "MACHINECHECK" */ 101 unsigned len; /* = MCE_LOG_LEN */ 102 unsigned next; 103 unsigned flags; 104 unsigned recordlen; /* length of struct mce */ 105 struct mce entry[MCE_LOG_LEN]; 106 }; 107 108 #define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */ 109 110 #define MCE_LOG_SIGNATURE "MACHINECHECK" 111 112 #define MCE_GET_RECORD_LEN _IOR('M', 1, int) 113 #define MCE_GET_LOG_LEN _IOR('M', 2, int) 114 #define MCE_GETCLEAR_FLAGS _IOR('M', 3, int) 115 116 /* Software defined banks */ 117 #define MCE_EXTENDED_BANK 128 118 #define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0 119 120 #define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) /* MCE_AMD */ 121 #define K8_MCE_THRESHOLD_BANK_0 (MCE_THRESHOLD_BASE + 0 * 9) 122 #define K8_MCE_THRESHOLD_BANK_1 (MCE_THRESHOLD_BASE + 1 * 9) 123 #define K8_MCE_THRESHOLD_BANK_2 (MCE_THRESHOLD_BASE + 2 * 9) 124 #define K8_MCE_THRESHOLD_BANK_3 (MCE_THRESHOLD_BASE + 3 * 9) 125 #define K8_MCE_THRESHOLD_BANK_4 (MCE_THRESHOLD_BASE + 4 * 9) 126 #define K8_MCE_THRESHOLD_BANK_5 (MCE_THRESHOLD_BASE + 5 * 9) 127 #define K8_MCE_THRESHOLD_DRAM_ECC (MCE_THRESHOLD_BANK_4 + 0) 128 129 130 #ifdef __KERNEL__ 131 132 extern void mce_register_decode_chain(struct notifier_block *nb); 133 extern void mce_unregister_decode_chain(struct notifier_block *nb); 134 135 #include <linux/percpu.h> 136 #include <linux/init.h> 137 #include <linux/atomic.h> 138 139 extern int mce_disabled; 140 extern int mce_p5_enabled; 141 142 #ifdef CONFIG_X86_MCE 143 int mcheck_init(void); 144 void mcheck_cpu_init(struct cpuinfo_x86 *c); 145 #else 146 static inline int mcheck_init(void) { return 0; } 147 static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {} 148 #endif 149 150 #ifdef CONFIG_X86_ANCIENT_MCE 151 void intel_p5_mcheck_init(struct cpuinfo_x86 *c); 152 void winchip_mcheck_init(struct cpuinfo_x86 *c); 153 static inline void enable_p5_mce(void) { mce_p5_enabled = 1; } 154 #else 155 static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {} 156 static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {} 157 static inline void enable_p5_mce(void) {} 158 #endif 159 160 void mce_setup(struct mce *m); 161 void mce_log(struct mce *m); 162 DECLARE_PER_CPU(struct device *, mce_device); 163 164 /* 165 * Maximum banks number. 166 * This is the limit of the current register layout on 167 * Intel CPUs. 168 */ 169 #define MAX_NR_BANKS 32 170 171 #ifdef CONFIG_X86_MCE_INTEL 172 extern int mce_cmci_disabled; 173 extern int mce_ignore_ce; 174 void mce_intel_feature_init(struct cpuinfo_x86 *c); 175 void cmci_clear(void); 176 void cmci_reenable(void); 177 void cmci_rediscover(int dying); 178 void cmci_recheck(void); 179 #else 180 static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { } 181 static inline void cmci_clear(void) {} 182 static inline void cmci_reenable(void) {} 183 static inline void cmci_rediscover(int dying) {} 184 static inline void cmci_recheck(void) {} 185 #endif 186 187 #ifdef CONFIG_X86_MCE_AMD 188 void mce_amd_feature_init(struct cpuinfo_x86 *c); 189 #else 190 static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } 191 #endif 192 193 int mce_available(struct cpuinfo_x86 *c); 194 195 DECLARE_PER_CPU(unsigned, mce_exception_count); 196 DECLARE_PER_CPU(unsigned, mce_poll_count); 197 198 extern atomic_t mce_entry; 199 200 typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS); 201 DECLARE_PER_CPU(mce_banks_t, mce_poll_banks); 202 203 enum mcp_flags { 204 MCP_TIMESTAMP = (1 << 0), /* log time stamp */ 205 MCP_UC = (1 << 1), /* log uncorrected errors */ 206 MCP_DONTLOG = (1 << 2), /* only clear, don't log */ 207 }; 208 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b); 209 210 int mce_notify_irq(void); 211 void mce_notify_process(void); 212 213 DECLARE_PER_CPU(struct mce, injectm); 214 215 extern void register_mce_write_callback(ssize_t (*)(struct file *filp, 216 const char __user *ubuf, 217 size_t usize, loff_t *off)); 218 219 /* 220 * Exception handler 221 */ 222 223 /* Call the installed machine check handler for this CPU setup. */ 224 extern void (*machine_check_vector)(struct pt_regs *, long error_code); 225 void do_machine_check(struct pt_regs *, long); 226 227 /* 228 * Threshold handler 229 */ 230 231 extern void (*mce_threshold_vector)(void); 232 extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); 233 234 /* 235 * Thermal handler 236 */ 237 238 void intel_init_thermal(struct cpuinfo_x86 *c); 239 240 void mce_log_therm_throt_event(__u64 status); 241 242 /* Interrupt Handler for core thermal thresholds */ 243 extern int (*platform_thermal_notify)(__u64 msr_val); 244 245 #ifdef CONFIG_X86_THERMAL_VECTOR 246 extern void mcheck_intel_therm_init(void); 247 #else 248 static inline void mcheck_intel_therm_init(void) { } 249 #endif 250 251 /* 252 * Used by APEI to report memory error via /dev/mcelog 253 */ 254 255 struct cper_sec_mem_err; 256 extern void apei_mce_report_mem_error(int corrected, 257 struct cper_sec_mem_err *mem_err); 258 259 #endif /* __KERNEL__ */ 260 #endif /* _ASM_X86_MCE_H */ 261