xref: /openbmc/linux/arch/x86/include/asm/mce.h (revision 82003e04)
1 #ifndef _ASM_X86_MCE_H
2 #define _ASM_X86_MCE_H
3 
4 #include <uapi/asm/mce.h>
5 
6 /*
7  * Machine Check support for x86
8  */
9 
10 /* MCG_CAP register defines */
11 #define MCG_BANKCNT_MASK	0xff         /* Number of Banks */
12 #define MCG_CTL_P		(1ULL<<8)    /* MCG_CTL register available */
13 #define MCG_EXT_P		(1ULL<<9)    /* Extended registers available */
14 #define MCG_CMCI_P		(1ULL<<10)   /* CMCI supported */
15 #define MCG_EXT_CNT_MASK	0xff0000     /* Number of Extended registers */
16 #define MCG_EXT_CNT_SHIFT	16
17 #define MCG_EXT_CNT(c)		(((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
18 #define MCG_SER_P		(1ULL<<24)   /* MCA recovery/new status bits */
19 #define MCG_ELOG_P		(1ULL<<26)   /* Extended error log supported */
20 #define MCG_LMCE_P		(1ULL<<27)   /* Local machine check supported */
21 
22 /* MCG_STATUS register defines */
23 #define MCG_STATUS_RIPV  (1ULL<<0)   /* restart ip valid */
24 #define MCG_STATUS_EIPV  (1ULL<<1)   /* ip points to correct instruction */
25 #define MCG_STATUS_MCIP  (1ULL<<2)   /* machine check in progress */
26 #define MCG_STATUS_LMCES (1ULL<<3)   /* LMCE signaled */
27 
28 /* MCG_EXT_CTL register defines */
29 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Enable LMCE */
30 
31 /* MCi_STATUS register defines */
32 #define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
33 #define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
34 #define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
35 #define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
36 #define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
37 #define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
38 #define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
39 #define MCI_STATUS_S	 (1ULL<<56)  /* Signaled machine check */
40 #define MCI_STATUS_AR	 (1ULL<<55)  /* Action required */
41 
42 /* AMD-specific bits */
43 #define MCI_STATUS_TCC		(1ULL<<55)  /* Task context corrupt */
44 #define MCI_STATUS_SYNDV	(1ULL<<53)  /* synd reg. valid */
45 #define MCI_STATUS_DEFERRED	(1ULL<<44)  /* uncorrected error, deferred exception */
46 #define MCI_STATUS_POISON	(1ULL<<43)  /* access poisonous data */
47 
48 /*
49  * McaX field if set indicates a given bank supports MCA extensions:
50  *  - Deferred error interrupt type is specifiable by bank.
51  *  - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers,
52  *    But should not be used to determine MSR numbers.
53  *  - TCC bit is present in MCx_STATUS.
54  */
55 #define MCI_CONFIG_MCAX		0x1
56 #define MCI_IPID_MCATYPE	0xFFFF0000
57 #define MCI_IPID_HWID		0xFFF
58 
59 /*
60  * Note that the full MCACOD field of IA32_MCi_STATUS MSR is
61  * bits 15:0.  But bit 12 is the 'F' bit, defined for corrected
62  * errors to indicate that errors are being filtered by hardware.
63  * We should mask out bit 12 when looking for specific signatures
64  * of uncorrected errors - so the F bit is deliberately skipped
65  * in this #define.
66  */
67 #define MCACOD		  0xefff     /* MCA Error Code */
68 
69 /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
70 #define MCACOD_SCRUB	0x00C0	/* 0xC0-0xCF Memory Scrubbing */
71 #define MCACOD_SCRUBMSK	0xeff0	/* Skip bit 12 ('F' bit) */
72 #define MCACOD_L3WB	0x017A	/* L3 Explicit Writeback */
73 #define MCACOD_DATA	0x0134	/* Data Load */
74 #define MCACOD_INSTR	0x0150	/* Instruction Fetch */
75 
76 /* MCi_MISC register defines */
77 #define MCI_MISC_ADDR_LSB(m)	((m) & 0x3f)
78 #define MCI_MISC_ADDR_MODE(m)	(((m) >> 6) & 7)
79 #define  MCI_MISC_ADDR_SEGOFF	0	/* segment offset */
80 #define  MCI_MISC_ADDR_LINEAR	1	/* linear address */
81 #define  MCI_MISC_ADDR_PHYS	2	/* physical address */
82 #define  MCI_MISC_ADDR_MEM	3	/* memory address */
83 #define  MCI_MISC_ADDR_GENERIC	7	/* generic */
84 
85 /* CTL2 register defines */
86 #define MCI_CTL2_CMCI_EN		(1ULL << 30)
87 #define MCI_CTL2_CMCI_THRESHOLD_MASK	0x7fffULL
88 
89 #define MCJ_CTX_MASK		3
90 #define MCJ_CTX(flags)		((flags) & MCJ_CTX_MASK)
91 #define MCJ_CTX_RANDOM		0    /* inject context: random */
92 #define MCJ_CTX_PROCESS		0x1  /* inject context: process */
93 #define MCJ_CTX_IRQ		0x2  /* inject context: IRQ */
94 #define MCJ_NMI_BROADCAST	0x4  /* do NMI broadcasting */
95 #define MCJ_EXCEPTION		0x8  /* raise as exception */
96 #define MCJ_IRQ_BROADCAST	0x10 /* do IRQ broadcasting */
97 
98 #define MCE_OVERFLOW 0		/* bit 0 in flags means overflow */
99 
100 /* Software defined banks */
101 #define MCE_EXTENDED_BANK	128
102 #define MCE_THERMAL_BANK	(MCE_EXTENDED_BANK + 0)
103 
104 #define MCE_LOG_LEN 32
105 #define MCE_LOG_SIGNATURE	"MACHINECHECK"
106 
107 /* AMD Scalable MCA */
108 #define MSR_AMD64_SMCA_MC0_CTL		0xc0002000
109 #define MSR_AMD64_SMCA_MC0_STATUS	0xc0002001
110 #define MSR_AMD64_SMCA_MC0_ADDR		0xc0002002
111 #define MSR_AMD64_SMCA_MC0_MISC0	0xc0002003
112 #define MSR_AMD64_SMCA_MC0_CONFIG	0xc0002004
113 #define MSR_AMD64_SMCA_MC0_IPID		0xc0002005
114 #define MSR_AMD64_SMCA_MC0_SYND		0xc0002006
115 #define MSR_AMD64_SMCA_MC0_DESTAT	0xc0002008
116 #define MSR_AMD64_SMCA_MC0_DEADDR	0xc0002009
117 #define MSR_AMD64_SMCA_MC0_MISC1	0xc000200a
118 #define MSR_AMD64_SMCA_MCx_CTL(x)	(MSR_AMD64_SMCA_MC0_CTL + 0x10*(x))
119 #define MSR_AMD64_SMCA_MCx_STATUS(x)	(MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x))
120 #define MSR_AMD64_SMCA_MCx_ADDR(x)	(MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x))
121 #define MSR_AMD64_SMCA_MCx_MISC(x)	(MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x))
122 #define MSR_AMD64_SMCA_MCx_CONFIG(x)	(MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))
123 #define MSR_AMD64_SMCA_MCx_IPID(x)	(MSR_AMD64_SMCA_MC0_IPID + 0x10*(x))
124 #define MSR_AMD64_SMCA_MCx_SYND(x)	(MSR_AMD64_SMCA_MC0_SYND + 0x10*(x))
125 #define MSR_AMD64_SMCA_MCx_DESTAT(x)	(MSR_AMD64_SMCA_MC0_DESTAT + 0x10*(x))
126 #define MSR_AMD64_SMCA_MCx_DEADDR(x)	(MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x))
127 #define MSR_AMD64_SMCA_MCx_MISCy(x, y)	((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x)))
128 
129 /*
130  * This structure contains all data related to the MCE log.  Also
131  * carries a signature to make it easier to find from external
132  * debugging tools.  Each entry is only valid when its finished flag
133  * is set.
134  */
135 struct mce_log {
136 	char signature[12]; /* "MACHINECHECK" */
137 	unsigned len;	    /* = MCE_LOG_LEN */
138 	unsigned next;
139 	unsigned flags;
140 	unsigned recordlen;	/* length of struct mce */
141 	struct mce entry[MCE_LOG_LEN];
142 };
143 
144 struct mca_config {
145 	bool dont_log_ce;
146 	bool cmci_disabled;
147 	bool lmce_disabled;
148 	bool ignore_ce;
149 	bool disabled;
150 	bool ser;
151 	bool recovery;
152 	bool bios_cmci_threshold;
153 	u8 banks;
154 	s8 bootlog;
155 	int tolerant;
156 	int monarch_timeout;
157 	int panic_timeout;
158 	u32 rip_msr;
159 };
160 
161 struct mce_vendor_flags {
162 	/*
163 	 * Indicates that overflow conditions are not fatal, when set.
164 	 */
165 	__u64 overflow_recov	: 1,
166 
167 	/*
168 	 * (AMD) SUCCOR stands for S/W UnCorrectable error COntainment and
169 	 * Recovery. It indicates support for data poisoning in HW and deferred
170 	 * error interrupts.
171 	 */
172 	      succor		: 1,
173 
174 	/*
175 	 * (AMD) SMCA: This bit indicates support for Scalable MCA which expands
176 	 * the register space for each MCA bank and also increases number of
177 	 * banks. Also, to accommodate the new banks and registers, the MCA
178 	 * register space is moved to a new MSR range.
179 	 */
180 	      smca		: 1,
181 
182 	      __reserved_0	: 61;
183 };
184 
185 struct mca_msr_regs {
186 	u32 (*ctl)	(int bank);
187 	u32 (*status)	(int bank);
188 	u32 (*addr)	(int bank);
189 	u32 (*misc)	(int bank);
190 };
191 
192 extern struct mce_vendor_flags mce_flags;
193 
194 extern struct mca_config mca_cfg;
195 extern struct mca_msr_regs msr_ops;
196 extern void mce_register_decode_chain(struct notifier_block *nb);
197 extern void mce_unregister_decode_chain(struct notifier_block *nb);
198 
199 #include <linux/percpu.h>
200 #include <linux/atomic.h>
201 
202 extern int mce_p5_enabled;
203 
204 #ifdef CONFIG_X86_MCE
205 int mcheck_init(void);
206 void mcheck_cpu_init(struct cpuinfo_x86 *c);
207 void mcheck_cpu_clear(struct cpuinfo_x86 *c);
208 void mcheck_vendor_init_severity(void);
209 #else
210 static inline int mcheck_init(void) { return 0; }
211 static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
212 static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {}
213 static inline void mcheck_vendor_init_severity(void) {}
214 #endif
215 
216 #ifdef CONFIG_X86_ANCIENT_MCE
217 void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
218 void winchip_mcheck_init(struct cpuinfo_x86 *c);
219 static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
220 #else
221 static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
222 static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
223 static inline void enable_p5_mce(void) {}
224 #endif
225 
226 void mce_setup(struct mce *m);
227 void mce_log(struct mce *m);
228 DECLARE_PER_CPU(struct device *, mce_device);
229 
230 /*
231  * Maximum banks number.
232  * This is the limit of the current register layout on
233  * Intel CPUs.
234  */
235 #define MAX_NR_BANKS 32
236 
237 #ifdef CONFIG_X86_MCE_INTEL
238 void mce_intel_feature_init(struct cpuinfo_x86 *c);
239 void mce_intel_feature_clear(struct cpuinfo_x86 *c);
240 void cmci_clear(void);
241 void cmci_reenable(void);
242 void cmci_rediscover(void);
243 void cmci_recheck(void);
244 #else
245 static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
246 static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { }
247 static inline void cmci_clear(void) {}
248 static inline void cmci_reenable(void) {}
249 static inline void cmci_rediscover(void) {}
250 static inline void cmci_recheck(void) {}
251 #endif
252 
253 #ifdef CONFIG_X86_MCE_AMD
254 void mce_amd_feature_init(struct cpuinfo_x86 *c);
255 #else
256 static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
257 #endif
258 
259 int mce_available(struct cpuinfo_x86 *c);
260 
261 DECLARE_PER_CPU(unsigned, mce_exception_count);
262 DECLARE_PER_CPU(unsigned, mce_poll_count);
263 
264 typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
265 DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
266 
267 enum mcp_flags {
268 	MCP_TIMESTAMP	= BIT(0),	/* log time stamp */
269 	MCP_UC		= BIT(1),	/* log uncorrected errors */
270 	MCP_DONTLOG	= BIT(2),	/* only clear, don't log */
271 };
272 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
273 
274 int mce_notify_irq(void);
275 
276 DECLARE_PER_CPU(struct mce, injectm);
277 
278 extern void register_mce_write_callback(ssize_t (*)(struct file *filp,
279 				    const char __user *ubuf,
280 				    size_t usize, loff_t *off));
281 
282 /* Disable CMCI/polling for MCA bank claimed by firmware */
283 extern void mce_disable_bank(int bank);
284 
285 /*
286  * Exception handler
287  */
288 
289 /* Call the installed machine check handler for this CPU setup. */
290 extern void (*machine_check_vector)(struct pt_regs *, long error_code);
291 void do_machine_check(struct pt_regs *, long);
292 
293 /*
294  * Threshold handler
295  */
296 
297 extern void (*mce_threshold_vector)(void);
298 extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
299 
300 /* Deferred error interrupt handler */
301 extern void (*deferred_error_int_vector)(void);
302 
303 /*
304  * Thermal handler
305  */
306 
307 void intel_init_thermal(struct cpuinfo_x86 *c);
308 
309 void mce_log_therm_throt_event(__u64 status);
310 
311 /* Interrupt Handler for core thermal thresholds */
312 extern int (*platform_thermal_notify)(__u64 msr_val);
313 
314 /* Interrupt Handler for package thermal thresholds */
315 extern int (*platform_thermal_package_notify)(__u64 msr_val);
316 
317 /* Callback support of rate control, return true, if
318  * callback has rate control */
319 extern bool (*platform_thermal_package_rate_control)(void);
320 
321 #ifdef CONFIG_X86_THERMAL_VECTOR
322 extern void mcheck_intel_therm_init(void);
323 #else
324 static inline void mcheck_intel_therm_init(void) { }
325 #endif
326 
327 /*
328  * Used by APEI to report memory error via /dev/mcelog
329  */
330 
331 struct cper_sec_mem_err;
332 extern void apei_mce_report_mem_error(int corrected,
333 				      struct cper_sec_mem_err *mem_err);
334 
335 /*
336  * Enumerate new IP types and HWID values in AMD processors which support
337  * Scalable MCA.
338  */
339 #ifdef CONFIG_X86_MCE_AMD
340 
341 /* These may be used by multiple smca_hwid_mcatypes */
342 enum smca_bank_types {
343 	SMCA_LS = 0,	/* Load Store */
344 	SMCA_IF,	/* Instruction Fetch */
345 	SMCA_L2_CACHE,	/* L2 Cache */
346 	SMCA_DE,	/* Decoder Unit */
347 	SMCA_EX,	/* Execution Unit */
348 	SMCA_FP,	/* Floating Point */
349 	SMCA_L3_CACHE,	/* L3 Cache */
350 	SMCA_CS,	/* Coherent Slave */
351 	SMCA_PIE,	/* Power, Interrupts, etc. */
352 	SMCA_UMC,	/* Unified Memory Controller */
353 	SMCA_PB,	/* Parameter Block */
354 	SMCA_PSP,	/* Platform Security Processor */
355 	SMCA_SMU,	/* System Management Unit */
356 	N_SMCA_BANK_TYPES
357 };
358 
359 struct smca_bank_name {
360 	const char *name;	/* Short name for sysfs */
361 	const char *long_name;	/* Long name for pretty-printing */
362 };
363 
364 extern struct smca_bank_name smca_bank_names[N_SMCA_BANK_TYPES];
365 
366 #define HWID_MCATYPE(hwid, mcatype) ((hwid << 16) | mcatype)
367 
368 struct smca_hwid_mcatype {
369 	unsigned int bank_type;	/* Use with smca_bank_types for easy indexing. */
370 	u32 hwid_mcatype;	/* (hwid,mcatype) tuple */
371 	u32 xec_bitmap;		/* Bitmap of valid ExtErrorCodes; current max is 21. */
372 };
373 
374 struct smca_bank_info {
375 	struct smca_hwid_mcatype *type;
376 	u32 type_instance;
377 };
378 
379 extern struct smca_bank_info smca_banks[MAX_NR_BANKS];
380 
381 #endif
382 
383 #endif /* _ASM_X86_MCE_H */
384