1 #ifndef _ASM_X86_MCE_H 2 #define _ASM_X86_MCE_H 3 4 #include <linux/types.h> 5 #include <asm/ioctls.h> 6 7 /* 8 * Machine Check support for x86 9 */ 10 11 /* MCG_CAP register defines */ 12 #define MCG_BANKCNT_MASK 0xff /* Number of Banks */ 13 #define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */ 14 #define MCG_EXT_P (1ULL<<9) /* Extended registers available */ 15 #define MCG_CMCI_P (1ULL<<10) /* CMCI supported */ 16 #define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */ 17 #define MCG_EXT_CNT_SHIFT 16 18 #define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT) 19 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 20 21 /* MCG_STATUS register defines */ 22 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 23 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 24 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 25 26 /* MCi_STATUS register defines */ 27 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 28 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 29 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 30 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 31 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 32 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 33 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 34 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 35 #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 36 37 /* MCi_MISC register defines */ 38 #define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f) 39 #define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7) 40 #define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */ 41 #define MCI_MISC_ADDR_LINEAR 1 /* linear address */ 42 #define MCI_MISC_ADDR_PHYS 2 /* physical address */ 43 #define MCI_MISC_ADDR_MEM 3 /* memory address */ 44 #define MCI_MISC_ADDR_GENERIC 7 /* generic */ 45 46 /* CTL2 register defines */ 47 #define MCI_CTL2_CMCI_EN (1ULL << 30) 48 #define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL 49 50 #define MCJ_CTX_MASK 3 51 #define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK) 52 #define MCJ_CTX_RANDOM 0 /* inject context: random */ 53 #define MCJ_CTX_PROCESS 1 /* inject context: process */ 54 #define MCJ_CTX_IRQ 2 /* inject context: IRQ */ 55 #define MCJ_NMI_BROADCAST 4 /* do NMI broadcasting */ 56 #define MCJ_EXCEPTION 8 /* raise as exception */ 57 58 /* Fields are zero when not available */ 59 struct mce { 60 __u64 status; 61 __u64 misc; 62 __u64 addr; 63 __u64 mcgstatus; 64 __u64 ip; 65 __u64 tsc; /* cpu time stamp counter */ 66 __u64 time; /* wall time_t when error was detected */ 67 __u8 cpuvendor; /* cpu vendor as encoded in system.h */ 68 __u8 inject_flags; /* software inject flags */ 69 __u16 pad; 70 __u32 cpuid; /* CPUID 1 EAX */ 71 __u8 cs; /* code segment */ 72 __u8 bank; /* machine check bank */ 73 __u8 cpu; /* cpu number; obsolete; use extcpu now */ 74 __u8 finished; /* entry is valid */ 75 __u32 extcpu; /* linux cpu number that detected the error */ 76 __u32 socketid; /* CPU socket ID */ 77 __u32 apicid; /* CPU initial apic ID */ 78 __u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */ 79 }; 80 81 /* 82 * This structure contains all data related to the MCE log. Also 83 * carries a signature to make it easier to find from external 84 * debugging tools. Each entry is only valid when its finished flag 85 * is set. 86 */ 87 88 #define MCE_LOG_LEN 32 89 90 struct mce_log { 91 char signature[12]; /* "MACHINECHECK" */ 92 unsigned len; /* = MCE_LOG_LEN */ 93 unsigned next; 94 unsigned flags; 95 unsigned recordlen; /* length of struct mce */ 96 struct mce entry[MCE_LOG_LEN]; 97 }; 98 99 #define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */ 100 101 #define MCE_LOG_SIGNATURE "MACHINECHECK" 102 103 #define MCE_GET_RECORD_LEN _IOR('M', 1, int) 104 #define MCE_GET_LOG_LEN _IOR('M', 2, int) 105 #define MCE_GETCLEAR_FLAGS _IOR('M', 3, int) 106 107 /* Software defined banks */ 108 #define MCE_EXTENDED_BANK 128 109 #define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0 110 111 #define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) /* MCE_AMD */ 112 #define K8_MCE_THRESHOLD_BANK_0 (MCE_THRESHOLD_BASE + 0 * 9) 113 #define K8_MCE_THRESHOLD_BANK_1 (MCE_THRESHOLD_BASE + 1 * 9) 114 #define K8_MCE_THRESHOLD_BANK_2 (MCE_THRESHOLD_BASE + 2 * 9) 115 #define K8_MCE_THRESHOLD_BANK_3 (MCE_THRESHOLD_BASE + 3 * 9) 116 #define K8_MCE_THRESHOLD_BANK_4 (MCE_THRESHOLD_BASE + 4 * 9) 117 #define K8_MCE_THRESHOLD_BANK_5 (MCE_THRESHOLD_BASE + 5 * 9) 118 #define K8_MCE_THRESHOLD_DRAM_ECC (MCE_THRESHOLD_BANK_4 + 0) 119 120 121 #ifdef __KERNEL__ 122 123 extern struct atomic_notifier_head x86_mce_decoder_chain; 124 125 #include <linux/percpu.h> 126 #include <linux/init.h> 127 #include <linux/atomic.h> 128 129 extern int mce_disabled; 130 extern int mce_p5_enabled; 131 132 #ifdef CONFIG_X86_MCE 133 int mcheck_init(void); 134 void mcheck_cpu_init(struct cpuinfo_x86 *c); 135 #else 136 static inline int mcheck_init(void) { return 0; } 137 static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {} 138 #endif 139 140 #ifdef CONFIG_X86_ANCIENT_MCE 141 void intel_p5_mcheck_init(struct cpuinfo_x86 *c); 142 void winchip_mcheck_init(struct cpuinfo_x86 *c); 143 static inline void enable_p5_mce(void) { mce_p5_enabled = 1; } 144 #else 145 static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {} 146 static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {} 147 static inline void enable_p5_mce(void) {} 148 #endif 149 150 void mce_setup(struct mce *m); 151 void mce_log(struct mce *m); 152 DECLARE_PER_CPU(struct sys_device, mce_sysdev); 153 154 /* 155 * Maximum banks number. 156 * This is the limit of the current register layout on 157 * Intel CPUs. 158 */ 159 #define MAX_NR_BANKS 32 160 161 #ifdef CONFIG_X86_MCE_INTEL 162 extern int mce_cmci_disabled; 163 extern int mce_ignore_ce; 164 void mce_intel_feature_init(struct cpuinfo_x86 *c); 165 void cmci_clear(void); 166 void cmci_reenable(void); 167 void cmci_rediscover(int dying); 168 void cmci_recheck(void); 169 #else 170 static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { } 171 static inline void cmci_clear(void) {} 172 static inline void cmci_reenable(void) {} 173 static inline void cmci_rediscover(int dying) {} 174 static inline void cmci_recheck(void) {} 175 #endif 176 177 #ifdef CONFIG_X86_MCE_AMD 178 void mce_amd_feature_init(struct cpuinfo_x86 *c); 179 #else 180 static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } 181 #endif 182 183 int mce_available(struct cpuinfo_x86 *c); 184 185 DECLARE_PER_CPU(unsigned, mce_exception_count); 186 DECLARE_PER_CPU(unsigned, mce_poll_count); 187 188 extern atomic_t mce_entry; 189 190 typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS); 191 DECLARE_PER_CPU(mce_banks_t, mce_poll_banks); 192 193 enum mcp_flags { 194 MCP_TIMESTAMP = (1 << 0), /* log time stamp */ 195 MCP_UC = (1 << 1), /* log uncorrected errors */ 196 MCP_DONTLOG = (1 << 2), /* only clear, don't log */ 197 }; 198 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b); 199 200 int mce_notify_irq(void); 201 void mce_notify_process(void); 202 203 DECLARE_PER_CPU(struct mce, injectm); 204 extern struct file_operations mce_chrdev_ops; 205 206 /* 207 * Exception handler 208 */ 209 210 /* Call the installed machine check handler for this CPU setup. */ 211 extern void (*machine_check_vector)(struct pt_regs *, long error_code); 212 void do_machine_check(struct pt_regs *, long); 213 214 /* 215 * Threshold handler 216 */ 217 218 extern void (*mce_threshold_vector)(void); 219 extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); 220 221 /* 222 * Thermal handler 223 */ 224 225 void intel_init_thermal(struct cpuinfo_x86 *c); 226 227 void mce_log_therm_throt_event(__u64 status); 228 229 /* Interrupt Handler for core thermal thresholds */ 230 extern int (*platform_thermal_notify)(__u64 msr_val); 231 232 #ifdef CONFIG_X86_THERMAL_VECTOR 233 extern void mcheck_intel_therm_init(void); 234 #else 235 static inline void mcheck_intel_therm_init(void) { } 236 #endif 237 238 /* 239 * Used by APEI to report memory error via /dev/mcelog 240 */ 241 242 struct cper_sec_mem_err; 243 extern void apei_mce_report_mem_error(int corrected, 244 struct cper_sec_mem_err *mem_err); 245 246 #endif /* __KERNEL__ */ 247 #endif /* _ASM_X86_MCE_H */ 248