1 #ifndef _ASM_X86_MCE_H 2 #define _ASM_X86_MCE_H 3 4 #include <uapi/asm/mce.h> 5 6 /* 7 * Machine Check support for x86 8 */ 9 10 /* MCG_CAP register defines */ 11 #define MCG_BANKCNT_MASK 0xff /* Number of Banks */ 12 #define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */ 13 #define MCG_EXT_P (1ULL<<9) /* Extended registers available */ 14 #define MCG_CMCI_P (1ULL<<10) /* CMCI supported */ 15 #define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */ 16 #define MCG_EXT_CNT_SHIFT 16 17 #define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT) 18 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 19 #define MCG_ELOG_P (1ULL<<26) /* Extended error log supported */ 20 #define MCG_LMCE_P (1ULL<<27) /* Local machine check supported */ 21 22 /* MCG_STATUS register defines */ 23 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 24 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 25 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 26 #define MCG_STATUS_LMCES (1ULL<<3) /* LMCE signaled */ 27 28 /* MCG_EXT_CTL register defines */ 29 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Enable LMCE */ 30 31 /* MCi_STATUS register defines */ 32 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 33 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 34 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 35 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ 36 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 37 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 38 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 39 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 40 #define MCI_STATUS_AR (1ULL<<55) /* Action required */ 41 42 /* AMD-specific bits */ 43 #define MCI_STATUS_DEFERRED (1ULL<<44) /* uncorrected error, deferred exception */ 44 #define MCI_STATUS_POISON (1ULL<<43) /* access poisonous data */ 45 #define MCI_STATUS_TCC (1ULL<<55) /* Task context corrupt */ 46 47 /* 48 * McaX field if set indicates a given bank supports MCA extensions: 49 * - Deferred error interrupt type is specifiable by bank. 50 * - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers, 51 * But should not be used to determine MSR numbers. 52 * - TCC bit is present in MCx_STATUS. 53 */ 54 #define MCI_CONFIG_MCAX 0x1 55 #define MCI_IPID_MCATYPE 0xFFFF0000 56 #define MCI_IPID_HWID 0xFFF 57 58 /* 59 * Note that the full MCACOD field of IA32_MCi_STATUS MSR is 60 * bits 15:0. But bit 12 is the 'F' bit, defined for corrected 61 * errors to indicate that errors are being filtered by hardware. 62 * We should mask out bit 12 when looking for specific signatures 63 * of uncorrected errors - so the F bit is deliberately skipped 64 * in this #define. 65 */ 66 #define MCACOD 0xefff /* MCA Error Code */ 67 68 /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */ 69 #define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */ 70 #define MCACOD_SCRUBMSK 0xeff0 /* Skip bit 12 ('F' bit) */ 71 #define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */ 72 #define MCACOD_DATA 0x0134 /* Data Load */ 73 #define MCACOD_INSTR 0x0150 /* Instruction Fetch */ 74 75 /* MCi_MISC register defines */ 76 #define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f) 77 #define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7) 78 #define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */ 79 #define MCI_MISC_ADDR_LINEAR 1 /* linear address */ 80 #define MCI_MISC_ADDR_PHYS 2 /* physical address */ 81 #define MCI_MISC_ADDR_MEM 3 /* memory address */ 82 #define MCI_MISC_ADDR_GENERIC 7 /* generic */ 83 84 /* CTL2 register defines */ 85 #define MCI_CTL2_CMCI_EN (1ULL << 30) 86 #define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL 87 88 #define MCJ_CTX_MASK 3 89 #define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK) 90 #define MCJ_CTX_RANDOM 0 /* inject context: random */ 91 #define MCJ_CTX_PROCESS 0x1 /* inject context: process */ 92 #define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */ 93 #define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */ 94 #define MCJ_EXCEPTION 0x8 /* raise as exception */ 95 #define MCJ_IRQ_BROADCAST 0x10 /* do IRQ broadcasting */ 96 97 #define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */ 98 99 /* Software defined banks */ 100 #define MCE_EXTENDED_BANK 128 101 #define MCE_THERMAL_BANK (MCE_EXTENDED_BANK + 0) 102 103 #define MCE_LOG_LEN 32 104 #define MCE_LOG_SIGNATURE "MACHINECHECK" 105 106 /* AMD Scalable MCA */ 107 #define MSR_AMD64_SMCA_MC0_CTL 0xc0002000 108 #define MSR_AMD64_SMCA_MC0_STATUS 0xc0002001 109 #define MSR_AMD64_SMCA_MC0_ADDR 0xc0002002 110 #define MSR_AMD64_SMCA_MC0_MISC0 0xc0002003 111 #define MSR_AMD64_SMCA_MC0_CONFIG 0xc0002004 112 #define MSR_AMD64_SMCA_MC0_IPID 0xc0002005 113 #define MSR_AMD64_SMCA_MC0_DESTAT 0xc0002008 114 #define MSR_AMD64_SMCA_MC0_DEADDR 0xc0002009 115 #define MSR_AMD64_SMCA_MC0_MISC1 0xc000200a 116 #define MSR_AMD64_SMCA_MCx_CTL(x) (MSR_AMD64_SMCA_MC0_CTL + 0x10*(x)) 117 #define MSR_AMD64_SMCA_MCx_STATUS(x) (MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x)) 118 #define MSR_AMD64_SMCA_MCx_ADDR(x) (MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x)) 119 #define MSR_AMD64_SMCA_MCx_MISC(x) (MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x)) 120 #define MSR_AMD64_SMCA_MCx_CONFIG(x) (MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x)) 121 #define MSR_AMD64_SMCA_MCx_IPID(x) (MSR_AMD64_SMCA_MC0_IPID + 0x10*(x)) 122 #define MSR_AMD64_SMCA_MCx_DESTAT(x) (MSR_AMD64_SMCA_MC0_DESTAT + 0x10*(x)) 123 #define MSR_AMD64_SMCA_MCx_DEADDR(x) (MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x)) 124 #define MSR_AMD64_SMCA_MCx_MISCy(x, y) ((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x))) 125 126 /* 127 * This structure contains all data related to the MCE log. Also 128 * carries a signature to make it easier to find from external 129 * debugging tools. Each entry is only valid when its finished flag 130 * is set. 131 */ 132 struct mce_log { 133 char signature[12]; /* "MACHINECHECK" */ 134 unsigned len; /* = MCE_LOG_LEN */ 135 unsigned next; 136 unsigned flags; 137 unsigned recordlen; /* length of struct mce */ 138 struct mce entry[MCE_LOG_LEN]; 139 }; 140 141 struct mca_config { 142 bool dont_log_ce; 143 bool cmci_disabled; 144 bool lmce_disabled; 145 bool ignore_ce; 146 bool disabled; 147 bool ser; 148 bool recovery; 149 bool bios_cmci_threshold; 150 u8 banks; 151 s8 bootlog; 152 int tolerant; 153 int monarch_timeout; 154 int panic_timeout; 155 u32 rip_msr; 156 }; 157 158 struct mce_vendor_flags { 159 /* 160 * Indicates that overflow conditions are not fatal, when set. 161 */ 162 __u64 overflow_recov : 1, 163 164 /* 165 * (AMD) SUCCOR stands for S/W UnCorrectable error COntainment and 166 * Recovery. It indicates support for data poisoning in HW and deferred 167 * error interrupts. 168 */ 169 succor : 1, 170 171 /* 172 * (AMD) SMCA: This bit indicates support for Scalable MCA which expands 173 * the register space for each MCA bank and also increases number of 174 * banks. Also, to accommodate the new banks and registers, the MCA 175 * register space is moved to a new MSR range. 176 */ 177 smca : 1, 178 179 __reserved_0 : 61; 180 }; 181 182 struct mca_msr_regs { 183 u32 (*ctl) (int bank); 184 u32 (*status) (int bank); 185 u32 (*addr) (int bank); 186 u32 (*misc) (int bank); 187 }; 188 189 extern struct mce_vendor_flags mce_flags; 190 191 extern struct mca_config mca_cfg; 192 extern struct mca_msr_regs msr_ops; 193 extern void mce_register_decode_chain(struct notifier_block *nb); 194 extern void mce_unregister_decode_chain(struct notifier_block *nb); 195 196 #include <linux/percpu.h> 197 #include <linux/atomic.h> 198 199 extern int mce_p5_enabled; 200 201 #ifdef CONFIG_X86_MCE 202 int mcheck_init(void); 203 void mcheck_cpu_init(struct cpuinfo_x86 *c); 204 void mcheck_cpu_clear(struct cpuinfo_x86 *c); 205 void mcheck_vendor_init_severity(void); 206 #else 207 static inline int mcheck_init(void) { return 0; } 208 static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {} 209 static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {} 210 static inline void mcheck_vendor_init_severity(void) {} 211 #endif 212 213 #ifdef CONFIG_X86_ANCIENT_MCE 214 void intel_p5_mcheck_init(struct cpuinfo_x86 *c); 215 void winchip_mcheck_init(struct cpuinfo_x86 *c); 216 static inline void enable_p5_mce(void) { mce_p5_enabled = 1; } 217 #else 218 static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {} 219 static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {} 220 static inline void enable_p5_mce(void) {} 221 #endif 222 223 void mce_setup(struct mce *m); 224 void mce_log(struct mce *m); 225 DECLARE_PER_CPU(struct device *, mce_device); 226 227 /* 228 * Maximum banks number. 229 * This is the limit of the current register layout on 230 * Intel CPUs. 231 */ 232 #define MAX_NR_BANKS 32 233 234 #ifdef CONFIG_X86_MCE_INTEL 235 void mce_intel_feature_init(struct cpuinfo_x86 *c); 236 void mce_intel_feature_clear(struct cpuinfo_x86 *c); 237 void cmci_clear(void); 238 void cmci_reenable(void); 239 void cmci_rediscover(void); 240 void cmci_recheck(void); 241 #else 242 static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { } 243 static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { } 244 static inline void cmci_clear(void) {} 245 static inline void cmci_reenable(void) {} 246 static inline void cmci_rediscover(void) {} 247 static inline void cmci_recheck(void) {} 248 #endif 249 250 #ifdef CONFIG_X86_MCE_AMD 251 void mce_amd_feature_init(struct cpuinfo_x86 *c); 252 #else 253 static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } 254 #endif 255 256 int mce_available(struct cpuinfo_x86 *c); 257 258 DECLARE_PER_CPU(unsigned, mce_exception_count); 259 DECLARE_PER_CPU(unsigned, mce_poll_count); 260 261 typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS); 262 DECLARE_PER_CPU(mce_banks_t, mce_poll_banks); 263 264 enum mcp_flags { 265 MCP_TIMESTAMP = BIT(0), /* log time stamp */ 266 MCP_UC = BIT(1), /* log uncorrected errors */ 267 MCP_DONTLOG = BIT(2), /* only clear, don't log */ 268 }; 269 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b); 270 271 int mce_notify_irq(void); 272 273 DECLARE_PER_CPU(struct mce, injectm); 274 275 extern void register_mce_write_callback(ssize_t (*)(struct file *filp, 276 const char __user *ubuf, 277 size_t usize, loff_t *off)); 278 279 /* Disable CMCI/polling for MCA bank claimed by firmware */ 280 extern void mce_disable_bank(int bank); 281 282 /* 283 * Exception handler 284 */ 285 286 /* Call the installed machine check handler for this CPU setup. */ 287 extern void (*machine_check_vector)(struct pt_regs *, long error_code); 288 void do_machine_check(struct pt_regs *, long); 289 290 /* 291 * Threshold handler 292 */ 293 294 extern void (*mce_threshold_vector)(void); 295 extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); 296 297 /* Deferred error interrupt handler */ 298 extern void (*deferred_error_int_vector)(void); 299 300 /* 301 * Thermal handler 302 */ 303 304 void intel_init_thermal(struct cpuinfo_x86 *c); 305 306 void mce_log_therm_throt_event(__u64 status); 307 308 /* Interrupt Handler for core thermal thresholds */ 309 extern int (*platform_thermal_notify)(__u64 msr_val); 310 311 /* Interrupt Handler for package thermal thresholds */ 312 extern int (*platform_thermal_package_notify)(__u64 msr_val); 313 314 /* Callback support of rate control, return true, if 315 * callback has rate control */ 316 extern bool (*platform_thermal_package_rate_control)(void); 317 318 #ifdef CONFIG_X86_THERMAL_VECTOR 319 extern void mcheck_intel_therm_init(void); 320 #else 321 static inline void mcheck_intel_therm_init(void) { } 322 #endif 323 324 /* 325 * Used by APEI to report memory error via /dev/mcelog 326 */ 327 328 struct cper_sec_mem_err; 329 extern void apei_mce_report_mem_error(int corrected, 330 struct cper_sec_mem_err *mem_err); 331 332 /* 333 * Enumerate new IP types and HWID values in AMD processors which support 334 * Scalable MCA. 335 */ 336 #ifdef CONFIG_X86_MCE_AMD 337 enum amd_ip_types { 338 SMCA_F17H_CORE = 0, /* Core errors */ 339 SMCA_DF, /* Data Fabric */ 340 SMCA_UMC, /* Unified Memory Controller */ 341 SMCA_PB, /* Parameter Block */ 342 SMCA_PSP, /* Platform Security Processor */ 343 SMCA_SMU, /* System Management Unit */ 344 N_AMD_IP_TYPES 345 }; 346 347 struct amd_hwid { 348 const char *name; 349 unsigned int hwid; 350 }; 351 352 extern struct amd_hwid amd_hwids[N_AMD_IP_TYPES]; 353 354 enum amd_core_mca_blocks { 355 SMCA_LS = 0, /* Load Store */ 356 SMCA_IF, /* Instruction Fetch */ 357 SMCA_L2_CACHE, /* L2 cache */ 358 SMCA_DE, /* Decoder unit */ 359 RES, /* Reserved */ 360 SMCA_EX, /* Execution unit */ 361 SMCA_FP, /* Floating Point */ 362 SMCA_L3_CACHE, /* L3 cache */ 363 N_CORE_MCA_BLOCKS 364 }; 365 366 extern const char * const amd_core_mcablock_names[N_CORE_MCA_BLOCKS]; 367 368 enum amd_df_mca_blocks { 369 SMCA_CS = 0, /* Coherent Slave */ 370 SMCA_PIE, /* Power management, Interrupts, etc */ 371 N_DF_BLOCKS 372 }; 373 374 extern const char * const amd_df_mcablock_names[N_DF_BLOCKS]; 375 #endif 376 377 #endif /* _ASM_X86_MCE_H */ 378