1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * This header defines architecture specific interfaces, x86 version 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2. See 7 * the COPYING file in the top-level directory. 8 * 9 */ 10 11 #ifndef _ASM_X86_KVM_HOST_H 12 #define _ASM_X86_KVM_HOST_H 13 14 #include <linux/types.h> 15 #include <linux/mm.h> 16 #include <linux/mmu_notifier.h> 17 #include <linux/tracepoint.h> 18 #include <linux/cpumask.h> 19 #include <linux/irq_work.h> 20 21 #include <linux/kvm.h> 22 #include <linux/kvm_para.h> 23 #include <linux/kvm_types.h> 24 #include <linux/perf_event.h> 25 #include <linux/pvclock_gtod.h> 26 #include <linux/clocksource.h> 27 #include <linux/irqbypass.h> 28 #include <linux/hyperv.h> 29 30 #include <asm/apic.h> 31 #include <asm/pvclock-abi.h> 32 #include <asm/desc.h> 33 #include <asm/mtrr.h> 34 #include <asm/msr-index.h> 35 #include <asm/asm.h> 36 #include <asm/kvm_page_track.h> 37 38 #define KVM_MAX_VCPUS 288 39 #define KVM_SOFT_MAX_VCPUS 240 40 #define KVM_MAX_VCPU_ID 1023 41 #define KVM_USER_MEM_SLOTS 509 42 /* memory slots that are not exposed to userspace */ 43 #define KVM_PRIVATE_MEM_SLOTS 3 44 #define KVM_MEM_SLOTS_NUM (KVM_USER_MEM_SLOTS + KVM_PRIVATE_MEM_SLOTS) 45 46 #define KVM_HALT_POLL_NS_DEFAULT 200000 47 48 #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS 49 50 /* x86-specific vcpu->requests bit members */ 51 #define KVM_REQ_MIGRATE_TIMER KVM_ARCH_REQ(0) 52 #define KVM_REQ_REPORT_TPR_ACCESS KVM_ARCH_REQ(1) 53 #define KVM_REQ_TRIPLE_FAULT KVM_ARCH_REQ(2) 54 #define KVM_REQ_MMU_SYNC KVM_ARCH_REQ(3) 55 #define KVM_REQ_CLOCK_UPDATE KVM_ARCH_REQ(4) 56 #define KVM_REQ_EVENT KVM_ARCH_REQ(6) 57 #define KVM_REQ_APF_HALT KVM_ARCH_REQ(7) 58 #define KVM_REQ_STEAL_UPDATE KVM_ARCH_REQ(8) 59 #define KVM_REQ_NMI KVM_ARCH_REQ(9) 60 #define KVM_REQ_PMU KVM_ARCH_REQ(10) 61 #define KVM_REQ_PMI KVM_ARCH_REQ(11) 62 #define KVM_REQ_SMI KVM_ARCH_REQ(12) 63 #define KVM_REQ_MASTERCLOCK_UPDATE KVM_ARCH_REQ(13) 64 #define KVM_REQ_MCLOCK_INPROGRESS \ 65 KVM_ARCH_REQ_FLAGS(14, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 66 #define KVM_REQ_SCAN_IOAPIC \ 67 KVM_ARCH_REQ_FLAGS(15, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 68 #define KVM_REQ_GLOBAL_CLOCK_UPDATE KVM_ARCH_REQ(16) 69 #define KVM_REQ_APIC_PAGE_RELOAD \ 70 KVM_ARCH_REQ_FLAGS(17, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 71 #define KVM_REQ_HV_CRASH KVM_ARCH_REQ(18) 72 #define KVM_REQ_IOAPIC_EOI_EXIT KVM_ARCH_REQ(19) 73 #define KVM_REQ_HV_RESET KVM_ARCH_REQ(20) 74 #define KVM_REQ_HV_EXIT KVM_ARCH_REQ(21) 75 #define KVM_REQ_HV_STIMER KVM_ARCH_REQ(22) 76 77 #define CR0_RESERVED_BITS \ 78 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ 79 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ 80 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) 81 82 #define CR3_PCID_INVD BIT_64(63) 83 #define CR4_RESERVED_BITS \ 84 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ 85 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ 86 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ 87 | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ 88 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \ 89 | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP)) 90 91 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) 92 93 94 95 #define INVALID_PAGE (~(hpa_t)0) 96 #define VALID_PAGE(x) ((x) != INVALID_PAGE) 97 98 #define UNMAPPED_GVA (~(gpa_t)0) 99 100 /* KVM Hugepage definitions for x86 */ 101 #define KVM_NR_PAGE_SIZES 3 102 #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9) 103 #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x)) 104 #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x)) 105 #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1)) 106 #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE) 107 108 static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level) 109 { 110 /* KVM_HPAGE_GFN_SHIFT(PT_PAGE_TABLE_LEVEL) must be 0. */ 111 return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - 112 (base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); 113 } 114 115 #define KVM_PERMILLE_MMU_PAGES 20 116 #define KVM_MIN_ALLOC_MMU_PAGES 64 117 #define KVM_MMU_HASH_SHIFT 12 118 #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) 119 #define KVM_MIN_FREE_MMU_PAGES 5 120 #define KVM_REFILL_PAGES 25 121 #define KVM_MAX_CPUID_ENTRIES 80 122 #define KVM_NR_FIXED_MTRR_REGION 88 123 #define KVM_NR_VAR_MTRR 8 124 125 #define ASYNC_PF_PER_VCPU 64 126 127 enum kvm_reg { 128 VCPU_REGS_RAX = 0, 129 VCPU_REGS_RCX = 1, 130 VCPU_REGS_RDX = 2, 131 VCPU_REGS_RBX = 3, 132 VCPU_REGS_RSP = 4, 133 VCPU_REGS_RBP = 5, 134 VCPU_REGS_RSI = 6, 135 VCPU_REGS_RDI = 7, 136 #ifdef CONFIG_X86_64 137 VCPU_REGS_R8 = 8, 138 VCPU_REGS_R9 = 9, 139 VCPU_REGS_R10 = 10, 140 VCPU_REGS_R11 = 11, 141 VCPU_REGS_R12 = 12, 142 VCPU_REGS_R13 = 13, 143 VCPU_REGS_R14 = 14, 144 VCPU_REGS_R15 = 15, 145 #endif 146 VCPU_REGS_RIP, 147 NR_VCPU_REGS 148 }; 149 150 enum kvm_reg_ex { 151 VCPU_EXREG_PDPTR = NR_VCPU_REGS, 152 VCPU_EXREG_CR3, 153 VCPU_EXREG_RFLAGS, 154 VCPU_EXREG_SEGMENTS, 155 }; 156 157 enum { 158 VCPU_SREG_ES, 159 VCPU_SREG_CS, 160 VCPU_SREG_SS, 161 VCPU_SREG_DS, 162 VCPU_SREG_FS, 163 VCPU_SREG_GS, 164 VCPU_SREG_TR, 165 VCPU_SREG_LDTR, 166 }; 167 168 #include <asm/kvm_emulate.h> 169 170 #define KVM_NR_MEM_OBJS 40 171 172 #define KVM_NR_DB_REGS 4 173 174 #define DR6_BD (1 << 13) 175 #define DR6_BS (1 << 14) 176 #define DR6_RTM (1 << 16) 177 #define DR6_FIXED_1 0xfffe0ff0 178 #define DR6_INIT 0xffff0ff0 179 #define DR6_VOLATILE 0x0001e00f 180 181 #define DR7_BP_EN_MASK 0x000000ff 182 #define DR7_GE (1 << 9) 183 #define DR7_GD (1 << 13) 184 #define DR7_FIXED_1 0x00000400 185 #define DR7_VOLATILE 0xffff2bff 186 187 #define PFERR_PRESENT_BIT 0 188 #define PFERR_WRITE_BIT 1 189 #define PFERR_USER_BIT 2 190 #define PFERR_RSVD_BIT 3 191 #define PFERR_FETCH_BIT 4 192 #define PFERR_PK_BIT 5 193 #define PFERR_GUEST_FINAL_BIT 32 194 #define PFERR_GUEST_PAGE_BIT 33 195 196 #define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT) 197 #define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT) 198 #define PFERR_USER_MASK (1U << PFERR_USER_BIT) 199 #define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT) 200 #define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT) 201 #define PFERR_PK_MASK (1U << PFERR_PK_BIT) 202 #define PFERR_GUEST_FINAL_MASK (1ULL << PFERR_GUEST_FINAL_BIT) 203 #define PFERR_GUEST_PAGE_MASK (1ULL << PFERR_GUEST_PAGE_BIT) 204 205 #define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \ 206 PFERR_WRITE_MASK | \ 207 PFERR_PRESENT_MASK) 208 209 /* 210 * The mask used to denote special SPTEs, which can be either MMIO SPTEs or 211 * Access Tracking SPTEs. We use bit 62 instead of bit 63 to avoid conflicting 212 * with the SVE bit in EPT PTEs. 213 */ 214 #define SPTE_SPECIAL_MASK (1ULL << 62) 215 216 /* apic attention bits */ 217 #define KVM_APIC_CHECK_VAPIC 0 218 /* 219 * The following bit is set with PV-EOI, unset on EOI. 220 * We detect PV-EOI changes by guest by comparing 221 * this bit with PV-EOI in guest memory. 222 * See the implementation in apic_update_pv_eoi. 223 */ 224 #define KVM_APIC_PV_EOI_PENDING 1 225 226 struct kvm_kernel_irq_routing_entry; 227 228 /* 229 * We don't want allocation failures within the mmu code, so we preallocate 230 * enough memory for a single page fault in a cache. 231 */ 232 struct kvm_mmu_memory_cache { 233 int nobjs; 234 void *objects[KVM_NR_MEM_OBJS]; 235 }; 236 237 /* 238 * the pages used as guest page table on soft mmu are tracked by 239 * kvm_memory_slot.arch.gfn_track which is 16 bits, so the role bits used 240 * by indirect shadow page can not be more than 15 bits. 241 * 242 * Currently, we used 14 bits that are @level, @cr4_pae, @quadrant, @access, 243 * @nxe, @cr0_wp, @smep_andnot_wp and @smap_andnot_wp. 244 */ 245 union kvm_mmu_page_role { 246 unsigned word; 247 struct { 248 unsigned level:4; 249 unsigned cr4_pae:1; 250 unsigned quadrant:2; 251 unsigned direct:1; 252 unsigned access:3; 253 unsigned invalid:1; 254 unsigned nxe:1; 255 unsigned cr0_wp:1; 256 unsigned smep_andnot_wp:1; 257 unsigned smap_andnot_wp:1; 258 unsigned ad_disabled:1; 259 unsigned :7; 260 261 /* 262 * This is left at the top of the word so that 263 * kvm_memslots_for_spte_role can extract it with a 264 * simple shift. While there is room, give it a whole 265 * byte so it is also faster to load it from memory. 266 */ 267 unsigned smm:8; 268 }; 269 }; 270 271 struct kvm_rmap_head { 272 unsigned long val; 273 }; 274 275 struct kvm_mmu_page { 276 struct list_head link; 277 struct hlist_node hash_link; 278 279 /* 280 * The following two entries are used to key the shadow page in the 281 * hash table. 282 */ 283 gfn_t gfn; 284 union kvm_mmu_page_role role; 285 286 u64 *spt; 287 /* hold the gfn of each spte inside spt */ 288 gfn_t *gfns; 289 bool unsync; 290 int root_count; /* Currently serving as active root */ 291 unsigned int unsync_children; 292 struct kvm_rmap_head parent_ptes; /* rmap pointers to parent sptes */ 293 294 /* The page is obsolete if mmu_valid_gen != kvm->arch.mmu_valid_gen. */ 295 unsigned long mmu_valid_gen; 296 297 DECLARE_BITMAP(unsync_child_bitmap, 512); 298 299 #ifdef CONFIG_X86_32 300 /* 301 * Used out of the mmu-lock to avoid reading spte values while an 302 * update is in progress; see the comments in __get_spte_lockless(). 303 */ 304 int clear_spte_count; 305 #endif 306 307 /* Number of writes since the last time traversal visited this page. */ 308 atomic_t write_flooding_count; 309 }; 310 311 struct kvm_pio_request { 312 unsigned long count; 313 int in; 314 int port; 315 int size; 316 }; 317 318 #define PT64_ROOT_MAX_LEVEL 5 319 320 struct rsvd_bits_validate { 321 u64 rsvd_bits_mask[2][PT64_ROOT_MAX_LEVEL]; 322 u64 bad_mt_xwr; 323 }; 324 325 /* 326 * x86 supports 4 paging modes (5-level 64-bit, 4-level 64-bit, 3-level 32-bit, 327 * and 2-level 32-bit). The kvm_mmu structure abstracts the details of the 328 * current mmu mode. 329 */ 330 struct kvm_mmu { 331 void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root); 332 unsigned long (*get_cr3)(struct kvm_vcpu *vcpu); 333 u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index); 334 int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err, 335 bool prefault); 336 void (*inject_page_fault)(struct kvm_vcpu *vcpu, 337 struct x86_exception *fault); 338 gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access, 339 struct x86_exception *exception); 340 gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 341 struct x86_exception *exception); 342 int (*sync_page)(struct kvm_vcpu *vcpu, 343 struct kvm_mmu_page *sp); 344 void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva); 345 void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, 346 u64 *spte, const void *pte); 347 hpa_t root_hpa; 348 union kvm_mmu_page_role base_role; 349 u8 root_level; 350 u8 shadow_root_level; 351 u8 ept_ad; 352 bool direct_map; 353 354 /* 355 * Bitmap; bit set = permission fault 356 * Byte index: page fault error code [4:1] 357 * Bit index: pte permissions in ACC_* format 358 */ 359 u8 permissions[16]; 360 361 /* 362 * The pkru_mask indicates if protection key checks are needed. It 363 * consists of 16 domains indexed by page fault error code bits [4:1], 364 * with PFEC.RSVD replaced by ACC_USER_MASK from the page tables. 365 * Each domain has 2 bits which are ANDed with AD and WD from PKRU. 366 */ 367 u32 pkru_mask; 368 369 u64 *pae_root; 370 u64 *lm_root; 371 372 /* 373 * check zero bits on shadow page table entries, these 374 * bits include not only hardware reserved bits but also 375 * the bits spte never used. 376 */ 377 struct rsvd_bits_validate shadow_zero_check; 378 379 struct rsvd_bits_validate guest_rsvd_check; 380 381 /* Can have large pages at levels 2..last_nonleaf_level-1. */ 382 u8 last_nonleaf_level; 383 384 bool nx; 385 386 u64 pdptrs[4]; /* pae */ 387 }; 388 389 enum pmc_type { 390 KVM_PMC_GP = 0, 391 KVM_PMC_FIXED, 392 }; 393 394 struct kvm_pmc { 395 enum pmc_type type; 396 u8 idx; 397 u64 counter; 398 u64 eventsel; 399 struct perf_event *perf_event; 400 struct kvm_vcpu *vcpu; 401 }; 402 403 struct kvm_pmu { 404 unsigned nr_arch_gp_counters; 405 unsigned nr_arch_fixed_counters; 406 unsigned available_event_types; 407 u64 fixed_ctr_ctrl; 408 u64 global_ctrl; 409 u64 global_status; 410 u64 global_ovf_ctrl; 411 u64 counter_bitmask[2]; 412 u64 global_ctrl_mask; 413 u64 reserved_bits; 414 u8 version; 415 struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC]; 416 struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED]; 417 struct irq_work irq_work; 418 u64 reprogram_pmi; 419 }; 420 421 struct kvm_pmu_ops; 422 423 enum { 424 KVM_DEBUGREG_BP_ENABLED = 1, 425 KVM_DEBUGREG_WONT_EXIT = 2, 426 KVM_DEBUGREG_RELOAD = 4, 427 }; 428 429 struct kvm_mtrr_range { 430 u64 base; 431 u64 mask; 432 struct list_head node; 433 }; 434 435 struct kvm_mtrr { 436 struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR]; 437 mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION]; 438 u64 deftype; 439 440 struct list_head head; 441 }; 442 443 /* Hyper-V SynIC timer */ 444 struct kvm_vcpu_hv_stimer { 445 struct hrtimer timer; 446 int index; 447 u64 config; 448 u64 count; 449 u64 exp_time; 450 struct hv_message msg; 451 bool msg_pending; 452 }; 453 454 /* Hyper-V synthetic interrupt controller (SynIC)*/ 455 struct kvm_vcpu_hv_synic { 456 u64 version; 457 u64 control; 458 u64 msg_page; 459 u64 evt_page; 460 atomic64_t sint[HV_SYNIC_SINT_COUNT]; 461 atomic_t sint_to_gsi[HV_SYNIC_SINT_COUNT]; 462 DECLARE_BITMAP(auto_eoi_bitmap, 256); 463 DECLARE_BITMAP(vec_bitmap, 256); 464 bool active; 465 bool dont_zero_synic_pages; 466 }; 467 468 /* Hyper-V per vcpu emulation context */ 469 struct kvm_vcpu_hv { 470 u32 vp_index; 471 u64 hv_vapic; 472 s64 runtime_offset; 473 struct kvm_vcpu_hv_synic synic; 474 struct kvm_hyperv_exit exit; 475 struct kvm_vcpu_hv_stimer stimer[HV_SYNIC_STIMER_COUNT]; 476 DECLARE_BITMAP(stimer_pending_bitmap, HV_SYNIC_STIMER_COUNT); 477 }; 478 479 struct kvm_vcpu_arch { 480 /* 481 * rip and regs accesses must go through 482 * kvm_{register,rip}_{read,write} functions. 483 */ 484 unsigned long regs[NR_VCPU_REGS]; 485 u32 regs_avail; 486 u32 regs_dirty; 487 488 unsigned long cr0; 489 unsigned long cr0_guest_owned_bits; 490 unsigned long cr2; 491 unsigned long cr3; 492 unsigned long cr4; 493 unsigned long cr4_guest_owned_bits; 494 unsigned long cr8; 495 u32 pkru; 496 u32 hflags; 497 u64 efer; 498 u64 apic_base; 499 struct kvm_lapic *apic; /* kernel irqchip context */ 500 bool apicv_active; 501 DECLARE_BITMAP(ioapic_handled_vectors, 256); 502 unsigned long apic_attention; 503 int32_t apic_arb_prio; 504 int mp_state; 505 u64 ia32_misc_enable_msr; 506 u64 smbase; 507 u64 smi_count; 508 bool tpr_access_reporting; 509 u64 ia32_xss; 510 u64 microcode_version; 511 512 /* 513 * Paging state of the vcpu 514 * 515 * If the vcpu runs in guest mode with two level paging this still saves 516 * the paging mode of the l1 guest. This context is always used to 517 * handle faults. 518 */ 519 struct kvm_mmu mmu; 520 521 /* 522 * Paging state of an L2 guest (used for nested npt) 523 * 524 * This context will save all necessary information to walk page tables 525 * of the an L2 guest. This context is only initialized for page table 526 * walking and not for faulting since we never handle l2 page faults on 527 * the host. 528 */ 529 struct kvm_mmu nested_mmu; 530 531 /* 532 * Pointer to the mmu context currently used for 533 * gva_to_gpa translations. 534 */ 535 struct kvm_mmu *walk_mmu; 536 537 struct kvm_mmu_memory_cache mmu_pte_list_desc_cache; 538 struct kvm_mmu_memory_cache mmu_page_cache; 539 struct kvm_mmu_memory_cache mmu_page_header_cache; 540 541 /* 542 * QEMU userspace and the guest each have their own FPU state. 543 * In vcpu_run, we switch between the user and guest FPU contexts. 544 * While running a VCPU, the VCPU thread will have the guest FPU 545 * context. 546 * 547 * Note that while the PKRU state lives inside the fpu registers, 548 * it is switched out separately at VMENTER and VMEXIT time. The 549 * "guest_fpu" state here contains the guest FPU context, with the 550 * host PRKU bits. 551 */ 552 struct fpu user_fpu; 553 struct fpu guest_fpu; 554 555 u64 xcr0; 556 u64 guest_supported_xcr0; 557 u32 guest_xstate_size; 558 559 struct kvm_pio_request pio; 560 void *pio_data; 561 562 u8 event_exit_inst_len; 563 564 struct kvm_queued_exception { 565 bool pending; 566 bool injected; 567 bool has_error_code; 568 u8 nr; 569 u32 error_code; 570 u8 nested_apf; 571 } exception; 572 573 struct kvm_queued_interrupt { 574 bool pending; 575 bool soft; 576 u8 nr; 577 } interrupt; 578 579 int halt_request; /* real mode on Intel only */ 580 581 int cpuid_nent; 582 struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES]; 583 584 int maxphyaddr; 585 586 /* emulate context */ 587 588 struct x86_emulate_ctxt emulate_ctxt; 589 bool emulate_regs_need_sync_to_vcpu; 590 bool emulate_regs_need_sync_from_vcpu; 591 int (*complete_userspace_io)(struct kvm_vcpu *vcpu); 592 593 gpa_t time; 594 struct pvclock_vcpu_time_info hv_clock; 595 unsigned int hw_tsc_khz; 596 struct gfn_to_hva_cache pv_time; 597 bool pv_time_enabled; 598 /* set guest stopped flag in pvclock flags field */ 599 bool pvclock_set_guest_stopped_request; 600 601 struct { 602 u64 msr_val; 603 u64 last_steal; 604 struct gfn_to_hva_cache stime; 605 struct kvm_steal_time steal; 606 } st; 607 608 u64 tsc_offset; 609 u64 last_guest_tsc; 610 u64 last_host_tsc; 611 u64 tsc_offset_adjustment; 612 u64 this_tsc_nsec; 613 u64 this_tsc_write; 614 u64 this_tsc_generation; 615 bool tsc_catchup; 616 bool tsc_always_catchup; 617 s8 virtual_tsc_shift; 618 u32 virtual_tsc_mult; 619 u32 virtual_tsc_khz; 620 s64 ia32_tsc_adjust_msr; 621 u64 tsc_scaling_ratio; 622 623 atomic_t nmi_queued; /* unprocessed asynchronous NMIs */ 624 unsigned nmi_pending; /* NMI queued after currently running handler */ 625 bool nmi_injected; /* Trying to inject an NMI this entry */ 626 bool smi_pending; /* SMI queued after currently running handler */ 627 628 struct kvm_mtrr mtrr_state; 629 u64 pat; 630 631 unsigned switch_db_regs; 632 unsigned long db[KVM_NR_DB_REGS]; 633 unsigned long dr6; 634 unsigned long dr7; 635 unsigned long eff_db[KVM_NR_DB_REGS]; 636 unsigned long guest_debug_dr7; 637 u64 msr_platform_info; 638 u64 msr_misc_features_enables; 639 640 u64 mcg_cap; 641 u64 mcg_status; 642 u64 mcg_ctl; 643 u64 mcg_ext_ctl; 644 u64 *mce_banks; 645 646 /* Cache MMIO info */ 647 u64 mmio_gva; 648 unsigned access; 649 gfn_t mmio_gfn; 650 u64 mmio_gen; 651 652 struct kvm_pmu pmu; 653 654 /* used for guest single stepping over the given code position */ 655 unsigned long singlestep_rip; 656 657 struct kvm_vcpu_hv hyperv; 658 659 cpumask_var_t wbinvd_dirty_mask; 660 661 unsigned long last_retry_eip; 662 unsigned long last_retry_addr; 663 664 struct { 665 bool halted; 666 gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)]; 667 struct gfn_to_hva_cache data; 668 u64 msr_val; 669 u32 id; 670 bool send_user_only; 671 u32 host_apf_reason; 672 unsigned long nested_apf_token; 673 bool delivery_as_pf_vmexit; 674 } apf; 675 676 /* OSVW MSRs (AMD only) */ 677 struct { 678 u64 length; 679 u64 status; 680 } osvw; 681 682 struct { 683 u64 msr_val; 684 struct gfn_to_hva_cache data; 685 } pv_eoi; 686 687 /* 688 * Indicate whether the access faults on its page table in guest 689 * which is set when fix page fault and used to detect unhandeable 690 * instruction. 691 */ 692 bool write_fault_to_shadow_pgtable; 693 694 /* set at EPT violation at this point */ 695 unsigned long exit_qualification; 696 697 /* pv related host specific info */ 698 struct { 699 bool pv_unhalted; 700 } pv; 701 702 int pending_ioapic_eoi; 703 int pending_external_vector; 704 705 /* GPA available */ 706 bool gpa_available; 707 gpa_t gpa_val; 708 709 /* be preempted when it's in kernel-mode(cpl=0) */ 710 bool preempted_in_kernel; 711 }; 712 713 struct kvm_lpage_info { 714 int disallow_lpage; 715 }; 716 717 struct kvm_arch_memory_slot { 718 struct kvm_rmap_head *rmap[KVM_NR_PAGE_SIZES]; 719 struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1]; 720 unsigned short *gfn_track[KVM_PAGE_TRACK_MAX]; 721 }; 722 723 /* 724 * We use as the mode the number of bits allocated in the LDR for the 725 * logical processor ID. It happens that these are all powers of two. 726 * This makes it is very easy to detect cases where the APICs are 727 * configured for multiple modes; in that case, we cannot use the map and 728 * hence cannot use kvm_irq_delivery_to_apic_fast either. 729 */ 730 #define KVM_APIC_MODE_XAPIC_CLUSTER 4 731 #define KVM_APIC_MODE_XAPIC_FLAT 8 732 #define KVM_APIC_MODE_X2APIC 16 733 734 struct kvm_apic_map { 735 struct rcu_head rcu; 736 u8 mode; 737 u32 max_apic_id; 738 union { 739 struct kvm_lapic *xapic_flat_map[8]; 740 struct kvm_lapic *xapic_cluster_map[16][4]; 741 }; 742 struct kvm_lapic *phys_map[]; 743 }; 744 745 /* Hyper-V emulation context */ 746 struct kvm_hv { 747 struct mutex hv_lock; 748 u64 hv_guest_os_id; 749 u64 hv_hypercall; 750 u64 hv_tsc_page; 751 752 /* Hyper-v based guest crash (NT kernel bugcheck) parameters */ 753 u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS]; 754 u64 hv_crash_ctl; 755 756 HV_REFERENCE_TSC_PAGE tsc_ref; 757 }; 758 759 enum kvm_irqchip_mode { 760 KVM_IRQCHIP_NONE, 761 KVM_IRQCHIP_KERNEL, /* created with KVM_CREATE_IRQCHIP */ 762 KVM_IRQCHIP_SPLIT, /* created with KVM_CAP_SPLIT_IRQCHIP */ 763 }; 764 765 struct kvm_sev_info { 766 bool active; /* SEV enabled guest */ 767 unsigned int asid; /* ASID used for this guest */ 768 unsigned int handle; /* SEV firmware handle */ 769 int fd; /* SEV device fd */ 770 unsigned long pages_locked; /* Number of pages locked */ 771 struct list_head regions_list; /* List of registered regions */ 772 }; 773 774 struct kvm_arch { 775 unsigned int n_used_mmu_pages; 776 unsigned int n_requested_mmu_pages; 777 unsigned int n_max_mmu_pages; 778 unsigned int indirect_shadow_pages; 779 unsigned long mmu_valid_gen; 780 struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; 781 /* 782 * Hash table of struct kvm_mmu_page. 783 */ 784 struct list_head active_mmu_pages; 785 struct list_head zapped_obsolete_pages; 786 struct kvm_page_track_notifier_node mmu_sp_tracker; 787 struct kvm_page_track_notifier_head track_notifier_head; 788 789 struct list_head assigned_dev_head; 790 struct iommu_domain *iommu_domain; 791 bool iommu_noncoherent; 792 #define __KVM_HAVE_ARCH_NONCOHERENT_DMA 793 atomic_t noncoherent_dma_count; 794 #define __KVM_HAVE_ARCH_ASSIGNED_DEVICE 795 atomic_t assigned_device_count; 796 struct kvm_pic *vpic; 797 struct kvm_ioapic *vioapic; 798 struct kvm_pit *vpit; 799 atomic_t vapics_in_nmi_mode; 800 struct mutex apic_map_lock; 801 struct kvm_apic_map *apic_map; 802 803 unsigned int tss_addr; 804 bool apic_access_page_done; 805 806 gpa_t wall_clock; 807 808 bool ept_identity_pagetable_done; 809 gpa_t ept_identity_map_addr; 810 811 unsigned long irq_sources_bitmap; 812 s64 kvmclock_offset; 813 raw_spinlock_t tsc_write_lock; 814 u64 last_tsc_nsec; 815 u64 last_tsc_write; 816 u32 last_tsc_khz; 817 u64 cur_tsc_nsec; 818 u64 cur_tsc_write; 819 u64 cur_tsc_offset; 820 u64 cur_tsc_generation; 821 int nr_vcpus_matched_tsc; 822 823 spinlock_t pvclock_gtod_sync_lock; 824 bool use_master_clock; 825 u64 master_kernel_ns; 826 u64 master_cycle_now; 827 struct delayed_work kvmclock_update_work; 828 struct delayed_work kvmclock_sync_work; 829 830 struct kvm_xen_hvm_config xen_hvm_config; 831 832 /* reads protected by irq_srcu, writes by irq_lock */ 833 struct hlist_head mask_notifier_list; 834 835 struct kvm_hv hyperv; 836 837 #ifdef CONFIG_KVM_MMU_AUDIT 838 int audit_point; 839 #endif 840 841 bool backwards_tsc_observed; 842 bool boot_vcpu_runs_old_kvmclock; 843 u32 bsp_vcpu_id; 844 845 u64 disabled_quirks; 846 847 enum kvm_irqchip_mode irqchip_mode; 848 u8 nr_reserved_ioapic_pins; 849 850 bool disabled_lapic_found; 851 852 /* Struct members for AVIC */ 853 u32 avic_vm_id; 854 u32 ldr_mode; 855 struct page *avic_logical_id_table_page; 856 struct page *avic_physical_id_table_page; 857 struct hlist_node hnode; 858 859 bool x2apic_format; 860 bool x2apic_broadcast_quirk_disabled; 861 862 struct kvm_sev_info sev_info; 863 }; 864 865 struct kvm_vm_stat { 866 ulong mmu_shadow_zapped; 867 ulong mmu_pte_write; 868 ulong mmu_pte_updated; 869 ulong mmu_pde_zapped; 870 ulong mmu_flooded; 871 ulong mmu_recycled; 872 ulong mmu_cache_miss; 873 ulong mmu_unsync; 874 ulong remote_tlb_flush; 875 ulong lpages; 876 ulong max_mmu_page_hash_collisions; 877 }; 878 879 struct kvm_vcpu_stat { 880 u64 pf_fixed; 881 u64 pf_guest; 882 u64 tlb_flush; 883 u64 invlpg; 884 885 u64 exits; 886 u64 io_exits; 887 u64 mmio_exits; 888 u64 signal_exits; 889 u64 irq_window_exits; 890 u64 nmi_window_exits; 891 u64 halt_exits; 892 u64 halt_successful_poll; 893 u64 halt_attempted_poll; 894 u64 halt_poll_invalid; 895 u64 halt_wakeup; 896 u64 request_irq_exits; 897 u64 irq_exits; 898 u64 host_state_reload; 899 u64 fpu_reload; 900 u64 insn_emulation; 901 u64 insn_emulation_fail; 902 u64 hypercalls; 903 u64 irq_injections; 904 u64 nmi_injections; 905 u64 req_event; 906 }; 907 908 struct x86_instruction_info; 909 910 struct msr_data { 911 bool host_initiated; 912 u32 index; 913 u64 data; 914 }; 915 916 struct kvm_lapic_irq { 917 u32 vector; 918 u16 delivery_mode; 919 u16 dest_mode; 920 bool level; 921 u16 trig_mode; 922 u32 shorthand; 923 u32 dest_id; 924 bool msi_redir_hint; 925 }; 926 927 struct kvm_x86_ops { 928 int (*cpu_has_kvm_support)(void); /* __init */ 929 int (*disabled_by_bios)(void); /* __init */ 930 int (*hardware_enable)(void); 931 void (*hardware_disable)(void); 932 void (*check_processor_compatibility)(void *rtn); 933 int (*hardware_setup)(void); /* __init */ 934 void (*hardware_unsetup)(void); /* __exit */ 935 bool (*cpu_has_accelerated_tpr)(void); 936 bool (*cpu_has_high_real_mode_segbase)(void); 937 void (*cpuid_update)(struct kvm_vcpu *vcpu); 938 939 int (*vm_init)(struct kvm *kvm); 940 void (*vm_destroy)(struct kvm *kvm); 941 942 /* Create, but do not attach this VCPU */ 943 struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id); 944 void (*vcpu_free)(struct kvm_vcpu *vcpu); 945 void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event); 946 947 void (*prepare_guest_switch)(struct kvm_vcpu *vcpu); 948 void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); 949 void (*vcpu_put)(struct kvm_vcpu *vcpu); 950 951 void (*update_bp_intercept)(struct kvm_vcpu *vcpu); 952 int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); 953 int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); 954 u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg); 955 void (*get_segment)(struct kvm_vcpu *vcpu, 956 struct kvm_segment *var, int seg); 957 int (*get_cpl)(struct kvm_vcpu *vcpu); 958 void (*set_segment)(struct kvm_vcpu *vcpu, 959 struct kvm_segment *var, int seg); 960 void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); 961 void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu); 962 void (*decache_cr3)(struct kvm_vcpu *vcpu); 963 void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu); 964 void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); 965 void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); 966 int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); 967 void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); 968 void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 969 void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 970 void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 971 void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 972 u64 (*get_dr6)(struct kvm_vcpu *vcpu); 973 void (*set_dr6)(struct kvm_vcpu *vcpu, unsigned long value); 974 void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu); 975 void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value); 976 void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); 977 unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); 978 void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); 979 980 void (*tlb_flush)(struct kvm_vcpu *vcpu, bool invalidate_gpa); 981 982 void (*run)(struct kvm_vcpu *vcpu); 983 int (*handle_exit)(struct kvm_vcpu *vcpu); 984 void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu); 985 void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); 986 u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu); 987 void (*patch_hypercall)(struct kvm_vcpu *vcpu, 988 unsigned char *hypercall_addr); 989 void (*set_irq)(struct kvm_vcpu *vcpu); 990 void (*set_nmi)(struct kvm_vcpu *vcpu); 991 void (*queue_exception)(struct kvm_vcpu *vcpu); 992 void (*cancel_injection)(struct kvm_vcpu *vcpu); 993 int (*interrupt_allowed)(struct kvm_vcpu *vcpu); 994 int (*nmi_allowed)(struct kvm_vcpu *vcpu); 995 bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); 996 void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked); 997 void (*enable_nmi_window)(struct kvm_vcpu *vcpu); 998 void (*enable_irq_window)(struct kvm_vcpu *vcpu); 999 void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr); 1000 bool (*get_enable_apicv)(struct kvm_vcpu *vcpu); 1001 void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu); 1002 void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr); 1003 void (*hwapic_isr_update)(struct kvm_vcpu *vcpu, int isr); 1004 void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); 1005 void (*set_virtual_x2apic_mode)(struct kvm_vcpu *vcpu, bool set); 1006 void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu, hpa_t hpa); 1007 void (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector); 1008 int (*sync_pir_to_irr)(struct kvm_vcpu *vcpu); 1009 int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); 1010 int (*get_tdp_level)(struct kvm_vcpu *vcpu); 1011 u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio); 1012 int (*get_lpage_level)(void); 1013 bool (*rdtscp_supported)(void); 1014 bool (*invpcid_supported)(void); 1015 1016 void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); 1017 1018 void (*set_supported_cpuid)(u32 func, struct kvm_cpuid_entry2 *entry); 1019 1020 bool (*has_wbinvd_exit)(void); 1021 1022 void (*write_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset); 1023 1024 void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2); 1025 1026 int (*check_intercept)(struct kvm_vcpu *vcpu, 1027 struct x86_instruction_info *info, 1028 enum x86_intercept_stage stage); 1029 void (*handle_external_intr)(struct kvm_vcpu *vcpu); 1030 bool (*mpx_supported)(void); 1031 bool (*xsaves_supported)(void); 1032 bool (*umip_emulated)(void); 1033 1034 int (*check_nested_events)(struct kvm_vcpu *vcpu, bool external_intr); 1035 1036 void (*sched_in)(struct kvm_vcpu *kvm, int cpu); 1037 1038 /* 1039 * Arch-specific dirty logging hooks. These hooks are only supposed to 1040 * be valid if the specific arch has hardware-accelerated dirty logging 1041 * mechanism. Currently only for PML on VMX. 1042 * 1043 * - slot_enable_log_dirty: 1044 * called when enabling log dirty mode for the slot. 1045 * - slot_disable_log_dirty: 1046 * called when disabling log dirty mode for the slot. 1047 * also called when slot is created with log dirty disabled. 1048 * - flush_log_dirty: 1049 * called before reporting dirty_bitmap to userspace. 1050 * - enable_log_dirty_pt_masked: 1051 * called when reenabling log dirty for the GFNs in the mask after 1052 * corresponding bits are cleared in slot->dirty_bitmap. 1053 */ 1054 void (*slot_enable_log_dirty)(struct kvm *kvm, 1055 struct kvm_memory_slot *slot); 1056 void (*slot_disable_log_dirty)(struct kvm *kvm, 1057 struct kvm_memory_slot *slot); 1058 void (*flush_log_dirty)(struct kvm *kvm); 1059 void (*enable_log_dirty_pt_masked)(struct kvm *kvm, 1060 struct kvm_memory_slot *slot, 1061 gfn_t offset, unsigned long mask); 1062 int (*write_log_dirty)(struct kvm_vcpu *vcpu); 1063 1064 /* pmu operations of sub-arch */ 1065 const struct kvm_pmu_ops *pmu_ops; 1066 1067 /* 1068 * Architecture specific hooks for vCPU blocking due to 1069 * HLT instruction. 1070 * Returns for .pre_block(): 1071 * - 0 means continue to block the vCPU. 1072 * - 1 means we cannot block the vCPU since some event 1073 * happens during this period, such as, 'ON' bit in 1074 * posted-interrupts descriptor is set. 1075 */ 1076 int (*pre_block)(struct kvm_vcpu *vcpu); 1077 void (*post_block)(struct kvm_vcpu *vcpu); 1078 1079 void (*vcpu_blocking)(struct kvm_vcpu *vcpu); 1080 void (*vcpu_unblocking)(struct kvm_vcpu *vcpu); 1081 1082 int (*update_pi_irte)(struct kvm *kvm, unsigned int host_irq, 1083 uint32_t guest_irq, bool set); 1084 void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu); 1085 1086 int (*set_hv_timer)(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc); 1087 void (*cancel_hv_timer)(struct kvm_vcpu *vcpu); 1088 1089 void (*setup_mce)(struct kvm_vcpu *vcpu); 1090 1091 int (*smi_allowed)(struct kvm_vcpu *vcpu); 1092 int (*pre_enter_smm)(struct kvm_vcpu *vcpu, char *smstate); 1093 int (*pre_leave_smm)(struct kvm_vcpu *vcpu, u64 smbase); 1094 int (*enable_smi_window)(struct kvm_vcpu *vcpu); 1095 1096 int (*mem_enc_op)(struct kvm *kvm, void __user *argp); 1097 int (*mem_enc_reg_region)(struct kvm *kvm, struct kvm_enc_region *argp); 1098 int (*mem_enc_unreg_region)(struct kvm *kvm, struct kvm_enc_region *argp); 1099 1100 int (*get_msr_feature)(struct kvm_msr_entry *entry); 1101 }; 1102 1103 struct kvm_arch_async_pf { 1104 u32 token; 1105 gfn_t gfn; 1106 unsigned long cr3; 1107 bool direct_map; 1108 }; 1109 1110 extern struct kvm_x86_ops *kvm_x86_ops; 1111 1112 int kvm_mmu_module_init(void); 1113 void kvm_mmu_module_exit(void); 1114 1115 void kvm_mmu_destroy(struct kvm_vcpu *vcpu); 1116 int kvm_mmu_create(struct kvm_vcpu *vcpu); 1117 void kvm_mmu_setup(struct kvm_vcpu *vcpu); 1118 void kvm_mmu_init_vm(struct kvm *kvm); 1119 void kvm_mmu_uninit_vm(struct kvm *kvm); 1120 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, 1121 u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask, 1122 u64 acc_track_mask, u64 me_mask); 1123 1124 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu); 1125 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, 1126 struct kvm_memory_slot *memslot); 1127 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, 1128 const struct kvm_memory_slot *memslot); 1129 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, 1130 struct kvm_memory_slot *memslot); 1131 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, 1132 struct kvm_memory_slot *memslot); 1133 void kvm_mmu_slot_set_dirty(struct kvm *kvm, 1134 struct kvm_memory_slot *memslot); 1135 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, 1136 struct kvm_memory_slot *slot, 1137 gfn_t gfn_offset, unsigned long mask); 1138 void kvm_mmu_zap_all(struct kvm *kvm); 1139 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots); 1140 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm); 1141 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages); 1142 1143 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3); 1144 bool pdptrs_changed(struct kvm_vcpu *vcpu); 1145 1146 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 1147 const void *val, int bytes); 1148 1149 struct kvm_irq_mask_notifier { 1150 void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked); 1151 int irq; 1152 struct hlist_node link; 1153 }; 1154 1155 void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq, 1156 struct kvm_irq_mask_notifier *kimn); 1157 void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq, 1158 struct kvm_irq_mask_notifier *kimn); 1159 void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin, 1160 bool mask); 1161 1162 extern bool tdp_enabled; 1163 1164 u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu); 1165 1166 /* control of guest tsc rate supported? */ 1167 extern bool kvm_has_tsc_control; 1168 /* maximum supported tsc_khz for guests */ 1169 extern u32 kvm_max_guest_tsc_khz; 1170 /* number of bits of the fractional part of the TSC scaling ratio */ 1171 extern u8 kvm_tsc_scaling_ratio_frac_bits; 1172 /* maximum allowed value of TSC scaling ratio */ 1173 extern u64 kvm_max_tsc_scaling_ratio; 1174 /* 1ull << kvm_tsc_scaling_ratio_frac_bits */ 1175 extern u64 kvm_default_tsc_scaling_ratio; 1176 1177 extern u64 kvm_mce_cap_supported; 1178 1179 enum emulation_result { 1180 EMULATE_DONE, /* no further processing */ 1181 EMULATE_USER_EXIT, /* kvm_run ready for userspace exit */ 1182 EMULATE_FAIL, /* can't emulate this instruction */ 1183 }; 1184 1185 #define EMULTYPE_NO_DECODE (1 << 0) 1186 #define EMULTYPE_TRAP_UD (1 << 1) 1187 #define EMULTYPE_SKIP (1 << 2) 1188 #define EMULTYPE_RETRY (1 << 3) 1189 #define EMULTYPE_NO_REEXECUTE (1 << 4) 1190 int x86_emulate_instruction(struct kvm_vcpu *vcpu, unsigned long cr2, 1191 int emulation_type, void *insn, int insn_len); 1192 1193 static inline int emulate_instruction(struct kvm_vcpu *vcpu, 1194 int emulation_type) 1195 { 1196 return x86_emulate_instruction(vcpu, 0, 1197 emulation_type | EMULTYPE_NO_REEXECUTE, NULL, 0); 1198 } 1199 1200 void kvm_enable_efer_bits(u64); 1201 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer); 1202 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); 1203 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); 1204 1205 struct x86_emulate_ctxt; 1206 1207 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port); 1208 int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port); 1209 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu); 1210 int kvm_emulate_halt(struct kvm_vcpu *vcpu); 1211 int kvm_vcpu_halt(struct kvm_vcpu *vcpu); 1212 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu); 1213 1214 void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 1215 int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg); 1216 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); 1217 1218 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 1219 int reason, bool has_error_code, u32 error_code); 1220 1221 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 1222 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); 1223 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 1224 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); 1225 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); 1226 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); 1227 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); 1228 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); 1229 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l); 1230 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr); 1231 1232 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); 1233 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); 1234 1235 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu); 1236 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 1237 bool kvm_rdpmc(struct kvm_vcpu *vcpu); 1238 1239 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); 1240 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); 1241 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr); 1242 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); 1243 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); 1244 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 1245 gfn_t gfn, void *data, int offset, int len, 1246 u32 access); 1247 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); 1248 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr); 1249 1250 static inline int __kvm_irq_line_state(unsigned long *irq_state, 1251 int irq_source_id, int level) 1252 { 1253 /* Logical OR for level trig interrupt */ 1254 if (level) 1255 __set_bit(irq_source_id, irq_state); 1256 else 1257 __clear_bit(irq_source_id, irq_state); 1258 1259 return !!(*irq_state); 1260 } 1261 1262 int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level); 1263 void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id); 1264 1265 void kvm_inject_nmi(struct kvm_vcpu *vcpu); 1266 1267 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn); 1268 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva); 1269 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu); 1270 int kvm_mmu_load(struct kvm_vcpu *vcpu); 1271 void kvm_mmu_unload(struct kvm_vcpu *vcpu); 1272 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); 1273 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 1274 struct x86_exception *exception); 1275 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 1276 struct x86_exception *exception); 1277 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 1278 struct x86_exception *exception); 1279 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 1280 struct x86_exception *exception); 1281 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 1282 struct x86_exception *exception); 1283 1284 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu); 1285 1286 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); 1287 1288 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u64 error_code, 1289 void *insn, int insn_len); 1290 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva); 1291 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu); 1292 1293 void kvm_enable_tdp(void); 1294 void kvm_disable_tdp(void); 1295 1296 static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 1297 struct x86_exception *exception) 1298 { 1299 return gpa; 1300 } 1301 1302 static inline struct kvm_mmu_page *page_header(hpa_t shadow_page) 1303 { 1304 struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT); 1305 1306 return (struct kvm_mmu_page *)page_private(page); 1307 } 1308 1309 static inline u16 kvm_read_ldt(void) 1310 { 1311 u16 ldt; 1312 asm("sldt %0" : "=g"(ldt)); 1313 return ldt; 1314 } 1315 1316 static inline void kvm_load_ldt(u16 sel) 1317 { 1318 asm("lldt %0" : : "rm"(sel)); 1319 } 1320 1321 #ifdef CONFIG_X86_64 1322 static inline unsigned long read_msr(unsigned long msr) 1323 { 1324 u64 value; 1325 1326 rdmsrl(msr, value); 1327 return value; 1328 } 1329 #endif 1330 1331 static inline u32 get_rdx_init_val(void) 1332 { 1333 return 0x600; /* P6 family */ 1334 } 1335 1336 static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) 1337 { 1338 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); 1339 } 1340 1341 #define TSS_IOPB_BASE_OFFSET 0x66 1342 #define TSS_BASE_SIZE 0x68 1343 #define TSS_IOPB_SIZE (65536 / 8) 1344 #define TSS_REDIRECTION_SIZE (256 / 8) 1345 #define RMODE_TSS_SIZE \ 1346 (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1) 1347 1348 enum { 1349 TASK_SWITCH_CALL = 0, 1350 TASK_SWITCH_IRET = 1, 1351 TASK_SWITCH_JMP = 2, 1352 TASK_SWITCH_GATE = 3, 1353 }; 1354 1355 #define HF_GIF_MASK (1 << 0) 1356 #define HF_HIF_MASK (1 << 1) 1357 #define HF_VINTR_MASK (1 << 2) 1358 #define HF_NMI_MASK (1 << 3) 1359 #define HF_IRET_MASK (1 << 4) 1360 #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */ 1361 #define HF_SMM_MASK (1 << 6) 1362 #define HF_SMM_INSIDE_NMI_MASK (1 << 7) 1363 1364 #define __KVM_VCPU_MULTIPLE_ADDRESS_SPACE 1365 #define KVM_ADDRESS_SPACE_NUM 2 1366 1367 #define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0) 1368 #define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm) 1369 1370 /* 1371 * Hardware virtualization extension instructions may fault if a 1372 * reboot turns off virtualization while processes are running. 1373 * Trap the fault and ignore the instruction if that happens. 1374 */ 1375 asmlinkage void kvm_spurious_fault(void); 1376 1377 #define ____kvm_handle_fault_on_reboot(insn, cleanup_insn) \ 1378 "666: " insn "\n\t" \ 1379 "668: \n\t" \ 1380 ".pushsection .fixup, \"ax\" \n" \ 1381 "667: \n\t" \ 1382 cleanup_insn "\n\t" \ 1383 "cmpb $0, kvm_rebooting \n\t" \ 1384 "jne 668b \n\t" \ 1385 __ASM_SIZE(push) " $666b \n\t" \ 1386 "call kvm_spurious_fault \n\t" \ 1387 ".popsection \n\t" \ 1388 _ASM_EXTABLE(666b, 667b) 1389 1390 #define __kvm_handle_fault_on_reboot(insn) \ 1391 ____kvm_handle_fault_on_reboot(insn, "") 1392 1393 #define KVM_ARCH_WANT_MMU_NOTIFIER 1394 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva); 1395 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end); 1396 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); 1397 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); 1398 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); 1399 int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v); 1400 int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); 1401 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu); 1402 int kvm_cpu_get_interrupt(struct kvm_vcpu *v); 1403 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event); 1404 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu); 1405 1406 void kvm_define_shared_msr(unsigned index, u32 msr); 1407 int kvm_set_shared_msr(unsigned index, u64 val, u64 mask); 1408 1409 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc); 1410 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc); 1411 1412 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu); 1413 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); 1414 1415 void kvm_make_mclock_inprogress_request(struct kvm *kvm); 1416 void kvm_make_scan_ioapic_request(struct kvm *kvm); 1417 1418 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 1419 struct kvm_async_pf *work); 1420 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 1421 struct kvm_async_pf *work); 1422 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, 1423 struct kvm_async_pf *work); 1424 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu); 1425 extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn); 1426 1427 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu); 1428 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err); 1429 1430 int kvm_is_in_guest(void); 1431 1432 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size); 1433 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size); 1434 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu); 1435 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu); 1436 1437 bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq, 1438 struct kvm_vcpu **dest_vcpu); 1439 1440 void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, 1441 struct kvm_lapic_irq *irq); 1442 1443 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) 1444 { 1445 if (kvm_x86_ops->vcpu_blocking) 1446 kvm_x86_ops->vcpu_blocking(vcpu); 1447 } 1448 1449 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) 1450 { 1451 if (kvm_x86_ops->vcpu_unblocking) 1452 kvm_x86_ops->vcpu_unblocking(vcpu); 1453 } 1454 1455 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} 1456 1457 static inline int kvm_cpu_get_apicid(int mps_cpu) 1458 { 1459 #ifdef CONFIG_X86_LOCAL_APIC 1460 return default_cpu_present_to_apicid(mps_cpu); 1461 #else 1462 WARN_ON_ONCE(1); 1463 return BAD_APICID; 1464 #endif 1465 } 1466 1467 #define put_smstate(type, buf, offset, val) \ 1468 *(type *)((buf) + (offset) - 0x7e00) = val 1469 1470 #endif /* _ASM_X86_KVM_HOST_H */ 1471