1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * This header defines architecture specific interfaces, x86 version 6 */ 7 8 #ifndef _ASM_X86_KVM_HOST_H 9 #define _ASM_X86_KVM_HOST_H 10 11 #include <linux/types.h> 12 #include <linux/mm.h> 13 #include <linux/mmu_notifier.h> 14 #include <linux/tracepoint.h> 15 #include <linux/cpumask.h> 16 #include <linux/irq_work.h> 17 #include <linux/irq.h> 18 #include <linux/workqueue.h> 19 20 #include <linux/kvm.h> 21 #include <linux/kvm_para.h> 22 #include <linux/kvm_types.h> 23 #include <linux/perf_event.h> 24 #include <linux/pvclock_gtod.h> 25 #include <linux/clocksource.h> 26 #include <linux/irqbypass.h> 27 #include <linux/hyperv.h> 28 29 #include <asm/apic.h> 30 #include <asm/pvclock-abi.h> 31 #include <asm/desc.h> 32 #include <asm/mtrr.h> 33 #include <asm/msr-index.h> 34 #include <asm/asm.h> 35 #include <asm/kvm_page_track.h> 36 #include <asm/kvm_vcpu_regs.h> 37 #include <asm/hyperv-tlfs.h> 38 39 #define __KVM_HAVE_ARCH_VCPU_DEBUGFS 40 41 #define KVM_MAX_VCPUS 1024 42 43 /* 44 * In x86, the VCPU ID corresponds to the APIC ID, and APIC IDs 45 * might be larger than the actual number of VCPUs because the 46 * APIC ID encodes CPU topology information. 47 * 48 * In the worst case, we'll need less than one extra bit for the 49 * Core ID, and less than one extra bit for the Package (Die) ID, 50 * so ratio of 4 should be enough. 51 */ 52 #define KVM_VCPU_ID_RATIO 4 53 #define KVM_MAX_VCPU_IDS (KVM_MAX_VCPUS * KVM_VCPU_ID_RATIO) 54 55 /* memory slots that are not exposed to userspace */ 56 #define KVM_INTERNAL_MEM_SLOTS 3 57 58 #define KVM_HALT_POLL_NS_DEFAULT 200000 59 60 #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS 61 62 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \ 63 KVM_DIRTY_LOG_INITIALLY_SET) 64 65 #define KVM_BUS_LOCK_DETECTION_VALID_MODE (KVM_BUS_LOCK_DETECTION_OFF | \ 66 KVM_BUS_LOCK_DETECTION_EXIT) 67 68 #define KVM_X86_NOTIFY_VMEXIT_VALID_BITS (KVM_X86_NOTIFY_VMEXIT_ENABLED | \ 69 KVM_X86_NOTIFY_VMEXIT_USER) 70 71 /* x86-specific vcpu->requests bit members */ 72 #define KVM_REQ_MIGRATE_TIMER KVM_ARCH_REQ(0) 73 #define KVM_REQ_REPORT_TPR_ACCESS KVM_ARCH_REQ(1) 74 #define KVM_REQ_TRIPLE_FAULT KVM_ARCH_REQ(2) 75 #define KVM_REQ_MMU_SYNC KVM_ARCH_REQ(3) 76 #define KVM_REQ_CLOCK_UPDATE KVM_ARCH_REQ(4) 77 #define KVM_REQ_LOAD_MMU_PGD KVM_ARCH_REQ(5) 78 #define KVM_REQ_EVENT KVM_ARCH_REQ(6) 79 #define KVM_REQ_APF_HALT KVM_ARCH_REQ(7) 80 #define KVM_REQ_STEAL_UPDATE KVM_ARCH_REQ(8) 81 #define KVM_REQ_NMI KVM_ARCH_REQ(9) 82 #define KVM_REQ_PMU KVM_ARCH_REQ(10) 83 #define KVM_REQ_PMI KVM_ARCH_REQ(11) 84 #define KVM_REQ_SMI KVM_ARCH_REQ(12) 85 #define KVM_REQ_MASTERCLOCK_UPDATE KVM_ARCH_REQ(13) 86 #define KVM_REQ_MCLOCK_INPROGRESS \ 87 KVM_ARCH_REQ_FLAGS(14, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 88 #define KVM_REQ_SCAN_IOAPIC \ 89 KVM_ARCH_REQ_FLAGS(15, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 90 #define KVM_REQ_GLOBAL_CLOCK_UPDATE KVM_ARCH_REQ(16) 91 #define KVM_REQ_APIC_PAGE_RELOAD \ 92 KVM_ARCH_REQ_FLAGS(17, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 93 #define KVM_REQ_HV_CRASH KVM_ARCH_REQ(18) 94 #define KVM_REQ_IOAPIC_EOI_EXIT KVM_ARCH_REQ(19) 95 #define KVM_REQ_HV_RESET KVM_ARCH_REQ(20) 96 #define KVM_REQ_HV_EXIT KVM_ARCH_REQ(21) 97 #define KVM_REQ_HV_STIMER KVM_ARCH_REQ(22) 98 #define KVM_REQ_LOAD_EOI_EXITMAP KVM_ARCH_REQ(23) 99 #define KVM_REQ_GET_NESTED_STATE_PAGES KVM_ARCH_REQ(24) 100 #define KVM_REQ_APICV_UPDATE \ 101 KVM_ARCH_REQ_FLAGS(25, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 102 #define KVM_REQ_TLB_FLUSH_CURRENT KVM_ARCH_REQ(26) 103 #define KVM_REQ_TLB_FLUSH_GUEST \ 104 KVM_ARCH_REQ_FLAGS(27, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 105 #define KVM_REQ_APF_READY KVM_ARCH_REQ(28) 106 #define KVM_REQ_MSR_FILTER_CHANGED KVM_ARCH_REQ(29) 107 #define KVM_REQ_UPDATE_CPU_DIRTY_LOGGING \ 108 KVM_ARCH_REQ_FLAGS(30, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 109 #define KVM_REQ_MMU_FREE_OBSOLETE_ROOTS \ 110 KVM_ARCH_REQ_FLAGS(31, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 111 112 #define CR0_RESERVED_BITS \ 113 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ 114 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ 115 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) 116 117 #define CR4_RESERVED_BITS \ 118 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ 119 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ 120 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ 121 | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ 122 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \ 123 | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP)) 124 125 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) 126 127 128 129 #define INVALID_PAGE (~(hpa_t)0) 130 #define VALID_PAGE(x) ((x) != INVALID_PAGE) 131 132 #define INVALID_GPA (~(gpa_t)0) 133 134 /* KVM Hugepage definitions for x86 */ 135 #define KVM_MAX_HUGEPAGE_LEVEL PG_LEVEL_1G 136 #define KVM_NR_PAGE_SIZES (KVM_MAX_HUGEPAGE_LEVEL - PG_LEVEL_4K + 1) 137 #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9) 138 #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x)) 139 #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x)) 140 #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1)) 141 #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE) 142 143 #define KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO 50 144 #define KVM_MIN_ALLOC_MMU_PAGES 64UL 145 #define KVM_MMU_HASH_SHIFT 12 146 #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) 147 #define KVM_MIN_FREE_MMU_PAGES 5 148 #define KVM_REFILL_PAGES 25 149 #define KVM_MAX_CPUID_ENTRIES 256 150 #define KVM_NR_FIXED_MTRR_REGION 88 151 #define KVM_NR_VAR_MTRR 8 152 153 #define ASYNC_PF_PER_VCPU 64 154 155 enum kvm_reg { 156 VCPU_REGS_RAX = __VCPU_REGS_RAX, 157 VCPU_REGS_RCX = __VCPU_REGS_RCX, 158 VCPU_REGS_RDX = __VCPU_REGS_RDX, 159 VCPU_REGS_RBX = __VCPU_REGS_RBX, 160 VCPU_REGS_RSP = __VCPU_REGS_RSP, 161 VCPU_REGS_RBP = __VCPU_REGS_RBP, 162 VCPU_REGS_RSI = __VCPU_REGS_RSI, 163 VCPU_REGS_RDI = __VCPU_REGS_RDI, 164 #ifdef CONFIG_X86_64 165 VCPU_REGS_R8 = __VCPU_REGS_R8, 166 VCPU_REGS_R9 = __VCPU_REGS_R9, 167 VCPU_REGS_R10 = __VCPU_REGS_R10, 168 VCPU_REGS_R11 = __VCPU_REGS_R11, 169 VCPU_REGS_R12 = __VCPU_REGS_R12, 170 VCPU_REGS_R13 = __VCPU_REGS_R13, 171 VCPU_REGS_R14 = __VCPU_REGS_R14, 172 VCPU_REGS_R15 = __VCPU_REGS_R15, 173 #endif 174 VCPU_REGS_RIP, 175 NR_VCPU_REGS, 176 177 VCPU_EXREG_PDPTR = NR_VCPU_REGS, 178 VCPU_EXREG_CR0, 179 VCPU_EXREG_CR3, 180 VCPU_EXREG_CR4, 181 VCPU_EXREG_RFLAGS, 182 VCPU_EXREG_SEGMENTS, 183 VCPU_EXREG_EXIT_INFO_1, 184 VCPU_EXREG_EXIT_INFO_2, 185 }; 186 187 enum { 188 VCPU_SREG_ES, 189 VCPU_SREG_CS, 190 VCPU_SREG_SS, 191 VCPU_SREG_DS, 192 VCPU_SREG_FS, 193 VCPU_SREG_GS, 194 VCPU_SREG_TR, 195 VCPU_SREG_LDTR, 196 }; 197 198 enum exit_fastpath_completion { 199 EXIT_FASTPATH_NONE, 200 EXIT_FASTPATH_REENTER_GUEST, 201 EXIT_FASTPATH_EXIT_HANDLED, 202 }; 203 typedef enum exit_fastpath_completion fastpath_t; 204 205 struct x86_emulate_ctxt; 206 struct x86_exception; 207 enum x86_intercept; 208 enum x86_intercept_stage; 209 210 #define KVM_NR_DB_REGS 4 211 212 #define DR6_BUS_LOCK (1 << 11) 213 #define DR6_BD (1 << 13) 214 #define DR6_BS (1 << 14) 215 #define DR6_BT (1 << 15) 216 #define DR6_RTM (1 << 16) 217 /* 218 * DR6_ACTIVE_LOW combines fixed-1 and active-low bits. 219 * We can regard all the bits in DR6_FIXED_1 as active_low bits; 220 * they will never be 0 for now, but when they are defined 221 * in the future it will require no code change. 222 * 223 * DR6_ACTIVE_LOW is also used as the init/reset value for DR6. 224 */ 225 #define DR6_ACTIVE_LOW 0xffff0ff0 226 #define DR6_VOLATILE 0x0001e80f 227 #define DR6_FIXED_1 (DR6_ACTIVE_LOW & ~DR6_VOLATILE) 228 229 #define DR7_BP_EN_MASK 0x000000ff 230 #define DR7_GE (1 << 9) 231 #define DR7_GD (1 << 13) 232 #define DR7_FIXED_1 0x00000400 233 #define DR7_VOLATILE 0xffff2bff 234 235 #define KVM_GUESTDBG_VALID_MASK \ 236 (KVM_GUESTDBG_ENABLE | \ 237 KVM_GUESTDBG_SINGLESTEP | \ 238 KVM_GUESTDBG_USE_HW_BP | \ 239 KVM_GUESTDBG_USE_SW_BP | \ 240 KVM_GUESTDBG_INJECT_BP | \ 241 KVM_GUESTDBG_INJECT_DB | \ 242 KVM_GUESTDBG_BLOCKIRQ) 243 244 245 #define PFERR_PRESENT_BIT 0 246 #define PFERR_WRITE_BIT 1 247 #define PFERR_USER_BIT 2 248 #define PFERR_RSVD_BIT 3 249 #define PFERR_FETCH_BIT 4 250 #define PFERR_PK_BIT 5 251 #define PFERR_SGX_BIT 15 252 #define PFERR_GUEST_FINAL_BIT 32 253 #define PFERR_GUEST_PAGE_BIT 33 254 #define PFERR_IMPLICIT_ACCESS_BIT 48 255 256 #define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT) 257 #define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT) 258 #define PFERR_USER_MASK (1U << PFERR_USER_BIT) 259 #define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT) 260 #define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT) 261 #define PFERR_PK_MASK (1U << PFERR_PK_BIT) 262 #define PFERR_SGX_MASK (1U << PFERR_SGX_BIT) 263 #define PFERR_GUEST_FINAL_MASK (1ULL << PFERR_GUEST_FINAL_BIT) 264 #define PFERR_GUEST_PAGE_MASK (1ULL << PFERR_GUEST_PAGE_BIT) 265 #define PFERR_IMPLICIT_ACCESS (1ULL << PFERR_IMPLICIT_ACCESS_BIT) 266 267 #define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \ 268 PFERR_WRITE_MASK | \ 269 PFERR_PRESENT_MASK) 270 271 /* apic attention bits */ 272 #define KVM_APIC_CHECK_VAPIC 0 273 /* 274 * The following bit is set with PV-EOI, unset on EOI. 275 * We detect PV-EOI changes by guest by comparing 276 * this bit with PV-EOI in guest memory. 277 * See the implementation in apic_update_pv_eoi. 278 */ 279 #define KVM_APIC_PV_EOI_PENDING 1 280 281 struct kvm_kernel_irq_routing_entry; 282 283 /* 284 * kvm_mmu_page_role tracks the properties of a shadow page (where shadow page 285 * also includes TDP pages) to determine whether or not a page can be used in 286 * the given MMU context. This is a subset of the overall kvm_cpu_role to 287 * minimize the size of kvm_memory_slot.arch.gfn_track, i.e. allows allocating 288 * 2 bytes per gfn instead of 4 bytes per gfn. 289 * 290 * Upper-level shadow pages having gptes are tracked for write-protection via 291 * gfn_track. As above, gfn_track is a 16 bit counter, so KVM must not create 292 * more than 2^16-1 upper-level shadow pages at a single gfn, otherwise 293 * gfn_track will overflow and explosions will ensure. 294 * 295 * A unique shadow page (SP) for a gfn is created if and only if an existing SP 296 * cannot be reused. The ability to reuse a SP is tracked by its role, which 297 * incorporates various mode bits and properties of the SP. Roughly speaking, 298 * the number of unique SPs that can theoretically be created is 2^n, where n 299 * is the number of bits that are used to compute the role. 300 * 301 * But, even though there are 19 bits in the mask below, not all combinations 302 * of modes and flags are possible: 303 * 304 * - invalid shadow pages are not accounted, so the bits are effectively 18 305 * 306 * - quadrant will only be used if has_4_byte_gpte=1 (non-PAE paging); 307 * execonly and ad_disabled are only used for nested EPT which has 308 * has_4_byte_gpte=0. Therefore, 2 bits are always unused. 309 * 310 * - the 4 bits of level are effectively limited to the values 2/3/4/5, 311 * as 4k SPs are not tracked (allowed to go unsync). In addition non-PAE 312 * paging has exactly one upper level, making level completely redundant 313 * when has_4_byte_gpte=1. 314 * 315 * - on top of this, smep_andnot_wp and smap_andnot_wp are only set if 316 * cr0_wp=0, therefore these three bits only give rise to 5 possibilities. 317 * 318 * Therefore, the maximum number of possible upper-level shadow pages for a 319 * single gfn is a bit less than 2^13. 320 */ 321 union kvm_mmu_page_role { 322 u32 word; 323 struct { 324 unsigned level:4; 325 unsigned has_4_byte_gpte:1; 326 unsigned quadrant:2; 327 unsigned direct:1; 328 unsigned access:3; 329 unsigned invalid:1; 330 unsigned efer_nx:1; 331 unsigned cr0_wp:1; 332 unsigned smep_andnot_wp:1; 333 unsigned smap_andnot_wp:1; 334 unsigned ad_disabled:1; 335 unsigned guest_mode:1; 336 unsigned passthrough:1; 337 unsigned :5; 338 339 /* 340 * This is left at the top of the word so that 341 * kvm_memslots_for_spte_role can extract it with a 342 * simple shift. While there is room, give it a whole 343 * byte so it is also faster to load it from memory. 344 */ 345 unsigned smm:8; 346 }; 347 }; 348 349 /* 350 * kvm_mmu_extended_role complements kvm_mmu_page_role, tracking properties 351 * relevant to the current MMU configuration. When loading CR0, CR4, or EFER, 352 * including on nested transitions, if nothing in the full role changes then 353 * MMU re-configuration can be skipped. @valid bit is set on first usage so we 354 * don't treat all-zero structure as valid data. 355 * 356 * The properties that are tracked in the extended role but not the page role 357 * are for things that either (a) do not affect the validity of the shadow page 358 * or (b) are indirectly reflected in the shadow page's role. For example, 359 * CR4.PKE only affects permission checks for software walks of the guest page 360 * tables (because KVM doesn't support Protection Keys with shadow paging), and 361 * CR0.PG, CR4.PAE, and CR4.PSE are indirectly reflected in role.level. 362 * 363 * Note, SMEP and SMAP are not redundant with sm*p_andnot_wp in the page role. 364 * If CR0.WP=1, KVM can reuse shadow pages for the guest regardless of SMEP and 365 * SMAP, but the MMU's permission checks for software walks need to be SMEP and 366 * SMAP aware regardless of CR0.WP. 367 */ 368 union kvm_mmu_extended_role { 369 u32 word; 370 struct { 371 unsigned int valid:1; 372 unsigned int execonly:1; 373 unsigned int cr4_pse:1; 374 unsigned int cr4_pke:1; 375 unsigned int cr4_smap:1; 376 unsigned int cr4_smep:1; 377 unsigned int cr4_la57:1; 378 unsigned int efer_lma:1; 379 }; 380 }; 381 382 union kvm_cpu_role { 383 u64 as_u64; 384 struct { 385 union kvm_mmu_page_role base; 386 union kvm_mmu_extended_role ext; 387 }; 388 }; 389 390 struct kvm_rmap_head { 391 unsigned long val; 392 }; 393 394 struct kvm_pio_request { 395 unsigned long linear_rip; 396 unsigned long count; 397 int in; 398 int port; 399 int size; 400 }; 401 402 #define PT64_ROOT_MAX_LEVEL 5 403 404 struct rsvd_bits_validate { 405 u64 rsvd_bits_mask[2][PT64_ROOT_MAX_LEVEL]; 406 u64 bad_mt_xwr; 407 }; 408 409 struct kvm_mmu_root_info { 410 gpa_t pgd; 411 hpa_t hpa; 412 }; 413 414 #define KVM_MMU_ROOT_INFO_INVALID \ 415 ((struct kvm_mmu_root_info) { .pgd = INVALID_PAGE, .hpa = INVALID_PAGE }) 416 417 #define KVM_MMU_NUM_PREV_ROOTS 3 418 419 #define KVM_HAVE_MMU_RWLOCK 420 421 struct kvm_mmu_page; 422 struct kvm_page_fault; 423 424 /* 425 * x86 supports 4 paging modes (5-level 64-bit, 4-level 64-bit, 3-level 32-bit, 426 * and 2-level 32-bit). The kvm_mmu structure abstracts the details of the 427 * current mmu mode. 428 */ 429 struct kvm_mmu { 430 unsigned long (*get_guest_pgd)(struct kvm_vcpu *vcpu); 431 u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index); 432 int (*page_fault)(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault); 433 void (*inject_page_fault)(struct kvm_vcpu *vcpu, 434 struct x86_exception *fault); 435 gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 436 gpa_t gva_or_gpa, u64 access, 437 struct x86_exception *exception); 438 int (*sync_page)(struct kvm_vcpu *vcpu, 439 struct kvm_mmu_page *sp); 440 void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa); 441 struct kvm_mmu_root_info root; 442 union kvm_cpu_role cpu_role; 443 union kvm_mmu_page_role root_role; 444 445 /* 446 * The pkru_mask indicates if protection key checks are needed. It 447 * consists of 16 domains indexed by page fault error code bits [4:1], 448 * with PFEC.RSVD replaced by ACC_USER_MASK from the page tables. 449 * Each domain has 2 bits which are ANDed with AD and WD from PKRU. 450 */ 451 u32 pkru_mask; 452 453 struct kvm_mmu_root_info prev_roots[KVM_MMU_NUM_PREV_ROOTS]; 454 455 /* 456 * Bitmap; bit set = permission fault 457 * Byte index: page fault error code [4:1] 458 * Bit index: pte permissions in ACC_* format 459 */ 460 u8 permissions[16]; 461 462 u64 *pae_root; 463 u64 *pml4_root; 464 u64 *pml5_root; 465 466 /* 467 * check zero bits on shadow page table entries, these 468 * bits include not only hardware reserved bits but also 469 * the bits spte never used. 470 */ 471 struct rsvd_bits_validate shadow_zero_check; 472 473 struct rsvd_bits_validate guest_rsvd_check; 474 475 u64 pdptrs[4]; /* pae */ 476 }; 477 478 struct kvm_tlb_range { 479 u64 start_gfn; 480 u64 pages; 481 }; 482 483 enum pmc_type { 484 KVM_PMC_GP = 0, 485 KVM_PMC_FIXED, 486 }; 487 488 struct kvm_pmc { 489 enum pmc_type type; 490 u8 idx; 491 u64 counter; 492 u64 eventsel; 493 struct perf_event *perf_event; 494 struct kvm_vcpu *vcpu; 495 /* 496 * eventsel value for general purpose counters, 497 * ctrl value for fixed counters. 498 */ 499 u64 current_config; 500 bool is_paused; 501 bool intr; 502 }; 503 504 /* More counters may conflict with other existing Architectural MSRs */ 505 #define KVM_INTEL_PMC_MAX_GENERIC 8 506 #define MSR_ARCH_PERFMON_PERFCTR_MAX (MSR_ARCH_PERFMON_PERFCTR0 + KVM_INTEL_PMC_MAX_GENERIC - 1) 507 #define MSR_ARCH_PERFMON_EVENTSEL_MAX (MSR_ARCH_PERFMON_EVENTSEL0 + KVM_INTEL_PMC_MAX_GENERIC - 1) 508 #define KVM_PMC_MAX_FIXED 3 509 #define KVM_AMD_PMC_MAX_GENERIC 6 510 struct kvm_pmu { 511 unsigned nr_arch_gp_counters; 512 unsigned nr_arch_fixed_counters; 513 unsigned available_event_types; 514 u64 fixed_ctr_ctrl; 515 u64 fixed_ctr_ctrl_mask; 516 u64 global_ctrl; 517 u64 global_status; 518 u64 counter_bitmask[2]; 519 u64 global_ctrl_mask; 520 u64 global_ovf_ctrl_mask; 521 u64 reserved_bits; 522 u64 raw_event_mask; 523 u8 version; 524 struct kvm_pmc gp_counters[KVM_INTEL_PMC_MAX_GENERIC]; 525 struct kvm_pmc fixed_counters[KVM_PMC_MAX_FIXED]; 526 struct irq_work irq_work; 527 DECLARE_BITMAP(reprogram_pmi, X86_PMC_IDX_MAX); 528 DECLARE_BITMAP(all_valid_pmc_idx, X86_PMC_IDX_MAX); 529 DECLARE_BITMAP(pmc_in_use, X86_PMC_IDX_MAX); 530 531 u64 ds_area; 532 u64 pebs_enable; 533 u64 pebs_enable_mask; 534 u64 pebs_data_cfg; 535 u64 pebs_data_cfg_mask; 536 537 /* 538 * If a guest counter is cross-mapped to host counter with different 539 * index, its PEBS capability will be temporarily disabled. 540 * 541 * The user should make sure that this mask is updated 542 * after disabling interrupts and before perf_guest_get_msrs(); 543 */ 544 u64 host_cross_mapped_mask; 545 546 /* 547 * The gate to release perf_events not marked in 548 * pmc_in_use only once in a vcpu time slice. 549 */ 550 bool need_cleanup; 551 552 /* 553 * The total number of programmed perf_events and it helps to avoid 554 * redundant check before cleanup if guest don't use vPMU at all. 555 */ 556 u8 event_count; 557 }; 558 559 struct kvm_pmu_ops; 560 561 enum { 562 KVM_DEBUGREG_BP_ENABLED = 1, 563 KVM_DEBUGREG_WONT_EXIT = 2, 564 }; 565 566 struct kvm_mtrr_range { 567 u64 base; 568 u64 mask; 569 struct list_head node; 570 }; 571 572 struct kvm_mtrr { 573 struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR]; 574 mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION]; 575 u64 deftype; 576 577 struct list_head head; 578 }; 579 580 /* Hyper-V SynIC timer */ 581 struct kvm_vcpu_hv_stimer { 582 struct hrtimer timer; 583 int index; 584 union hv_stimer_config config; 585 u64 count; 586 u64 exp_time; 587 struct hv_message msg; 588 bool msg_pending; 589 }; 590 591 /* Hyper-V synthetic interrupt controller (SynIC)*/ 592 struct kvm_vcpu_hv_synic { 593 u64 version; 594 u64 control; 595 u64 msg_page; 596 u64 evt_page; 597 atomic64_t sint[HV_SYNIC_SINT_COUNT]; 598 atomic_t sint_to_gsi[HV_SYNIC_SINT_COUNT]; 599 DECLARE_BITMAP(auto_eoi_bitmap, 256); 600 DECLARE_BITMAP(vec_bitmap, 256); 601 bool active; 602 bool dont_zero_synic_pages; 603 }; 604 605 /* Hyper-V per vcpu emulation context */ 606 struct kvm_vcpu_hv { 607 struct kvm_vcpu *vcpu; 608 u32 vp_index; 609 u64 hv_vapic; 610 s64 runtime_offset; 611 struct kvm_vcpu_hv_synic synic; 612 struct kvm_hyperv_exit exit; 613 struct kvm_vcpu_hv_stimer stimer[HV_SYNIC_STIMER_COUNT]; 614 DECLARE_BITMAP(stimer_pending_bitmap, HV_SYNIC_STIMER_COUNT); 615 bool enforce_cpuid; 616 struct { 617 u32 features_eax; /* HYPERV_CPUID_FEATURES.EAX */ 618 u32 features_ebx; /* HYPERV_CPUID_FEATURES.EBX */ 619 u32 features_edx; /* HYPERV_CPUID_FEATURES.EDX */ 620 u32 enlightenments_eax; /* HYPERV_CPUID_ENLIGHTMENT_INFO.EAX */ 621 u32 enlightenments_ebx; /* HYPERV_CPUID_ENLIGHTMENT_INFO.EBX */ 622 u32 syndbg_cap_eax; /* HYPERV_CPUID_SYNDBG_PLATFORM_CAPABILITIES.EAX */ 623 u32 nested_eax; /* HYPERV_CPUID_NESTED_FEATURES.EAX */ 624 u32 nested_ebx; /* HYPERV_CPUID_NESTED_FEATURES.EBX */ 625 } cpuid_cache; 626 }; 627 628 /* Xen HVM per vcpu emulation context */ 629 struct kvm_vcpu_xen { 630 u64 hypercall_rip; 631 u32 current_runstate; 632 u8 upcall_vector; 633 struct gfn_to_pfn_cache vcpu_info_cache; 634 struct gfn_to_pfn_cache vcpu_time_info_cache; 635 struct gfn_to_pfn_cache runstate_cache; 636 u64 last_steal; 637 u64 runstate_entry_time; 638 u64 runstate_times[4]; 639 unsigned long evtchn_pending_sel; 640 u32 vcpu_id; /* The Xen / ACPI vCPU ID */ 641 u32 timer_virq; 642 u64 timer_expires; /* In guest epoch */ 643 atomic_t timer_pending; 644 struct hrtimer timer; 645 int poll_evtchn; 646 struct timer_list poll_timer; 647 }; 648 649 struct kvm_queued_exception { 650 bool pending; 651 bool injected; 652 bool has_error_code; 653 u8 vector; 654 u32 error_code; 655 unsigned long payload; 656 bool has_payload; 657 }; 658 659 struct kvm_vcpu_arch { 660 /* 661 * rip and regs accesses must go through 662 * kvm_{register,rip}_{read,write} functions. 663 */ 664 unsigned long regs[NR_VCPU_REGS]; 665 u32 regs_avail; 666 u32 regs_dirty; 667 668 unsigned long cr0; 669 unsigned long cr0_guest_owned_bits; 670 unsigned long cr2; 671 unsigned long cr3; 672 unsigned long cr4; 673 unsigned long cr4_guest_owned_bits; 674 unsigned long cr4_guest_rsvd_bits; 675 unsigned long cr8; 676 u32 host_pkru; 677 u32 pkru; 678 u32 hflags; 679 u64 efer; 680 u64 apic_base; 681 struct kvm_lapic *apic; /* kernel irqchip context */ 682 bool load_eoi_exitmap_pending; 683 DECLARE_BITMAP(ioapic_handled_vectors, 256); 684 unsigned long apic_attention; 685 int32_t apic_arb_prio; 686 int mp_state; 687 u64 ia32_misc_enable_msr; 688 u64 smbase; 689 u64 smi_count; 690 bool at_instruction_boundary; 691 bool tpr_access_reporting; 692 bool xsaves_enabled; 693 bool xfd_no_write_intercept; 694 u64 ia32_xss; 695 u64 microcode_version; 696 u64 arch_capabilities; 697 u64 perf_capabilities; 698 699 /* 700 * Paging state of the vcpu 701 * 702 * If the vcpu runs in guest mode with two level paging this still saves 703 * the paging mode of the l1 guest. This context is always used to 704 * handle faults. 705 */ 706 struct kvm_mmu *mmu; 707 708 /* Non-nested MMU for L1 */ 709 struct kvm_mmu root_mmu; 710 711 /* L1 MMU when running nested */ 712 struct kvm_mmu guest_mmu; 713 714 /* 715 * Paging state of an L2 guest (used for nested npt) 716 * 717 * This context will save all necessary information to walk page tables 718 * of an L2 guest. This context is only initialized for page table 719 * walking and not for faulting since we never handle l2 page faults on 720 * the host. 721 */ 722 struct kvm_mmu nested_mmu; 723 724 /* 725 * Pointer to the mmu context currently used for 726 * gva_to_gpa translations. 727 */ 728 struct kvm_mmu *walk_mmu; 729 730 struct kvm_mmu_memory_cache mmu_pte_list_desc_cache; 731 struct kvm_mmu_memory_cache mmu_shadow_page_cache; 732 struct kvm_mmu_memory_cache mmu_shadowed_info_cache; 733 struct kvm_mmu_memory_cache mmu_page_header_cache; 734 735 /* 736 * QEMU userspace and the guest each have their own FPU state. 737 * In vcpu_run, we switch between the user and guest FPU contexts. 738 * While running a VCPU, the VCPU thread will have the guest FPU 739 * context. 740 * 741 * Note that while the PKRU state lives inside the fpu registers, 742 * it is switched out separately at VMENTER and VMEXIT time. The 743 * "guest_fpstate" state here contains the guest FPU context, with the 744 * host PRKU bits. 745 */ 746 struct fpu_guest guest_fpu; 747 748 u64 xcr0; 749 u64 guest_supported_xcr0; 750 751 struct kvm_pio_request pio; 752 void *pio_data; 753 void *sev_pio_data; 754 unsigned sev_pio_count; 755 756 u8 event_exit_inst_len; 757 758 bool exception_from_userspace; 759 760 /* Exceptions to be injected to the guest. */ 761 struct kvm_queued_exception exception; 762 /* Exception VM-Exits to be synthesized to L1. */ 763 struct kvm_queued_exception exception_vmexit; 764 765 struct kvm_queued_interrupt { 766 bool injected; 767 bool soft; 768 u8 nr; 769 } interrupt; 770 771 int halt_request; /* real mode on Intel only */ 772 773 int cpuid_nent; 774 struct kvm_cpuid_entry2 *cpuid_entries; 775 u32 kvm_cpuid_base; 776 777 u64 reserved_gpa_bits; 778 int maxphyaddr; 779 780 /* emulate context */ 781 782 struct x86_emulate_ctxt *emulate_ctxt; 783 bool emulate_regs_need_sync_to_vcpu; 784 bool emulate_regs_need_sync_from_vcpu; 785 int (*complete_userspace_io)(struct kvm_vcpu *vcpu); 786 787 gpa_t time; 788 struct pvclock_vcpu_time_info hv_clock; 789 unsigned int hw_tsc_khz; 790 struct gfn_to_pfn_cache pv_time; 791 /* set guest stopped flag in pvclock flags field */ 792 bool pvclock_set_guest_stopped_request; 793 794 struct { 795 u8 preempted; 796 u64 msr_val; 797 u64 last_steal; 798 struct gfn_to_hva_cache cache; 799 } st; 800 801 u64 l1_tsc_offset; 802 u64 tsc_offset; /* current tsc offset */ 803 u64 last_guest_tsc; 804 u64 last_host_tsc; 805 u64 tsc_offset_adjustment; 806 u64 this_tsc_nsec; 807 u64 this_tsc_write; 808 u64 this_tsc_generation; 809 bool tsc_catchup; 810 bool tsc_always_catchup; 811 s8 virtual_tsc_shift; 812 u32 virtual_tsc_mult; 813 u32 virtual_tsc_khz; 814 s64 ia32_tsc_adjust_msr; 815 u64 msr_ia32_power_ctl; 816 u64 l1_tsc_scaling_ratio; 817 u64 tsc_scaling_ratio; /* current scaling ratio */ 818 819 atomic_t nmi_queued; /* unprocessed asynchronous NMIs */ 820 unsigned nmi_pending; /* NMI queued after currently running handler */ 821 bool nmi_injected; /* Trying to inject an NMI this entry */ 822 bool smi_pending; /* SMI queued after currently running handler */ 823 u8 handling_intr_from_guest; 824 825 struct kvm_mtrr mtrr_state; 826 u64 pat; 827 828 unsigned switch_db_regs; 829 unsigned long db[KVM_NR_DB_REGS]; 830 unsigned long dr6; 831 unsigned long dr7; 832 unsigned long eff_db[KVM_NR_DB_REGS]; 833 unsigned long guest_debug_dr7; 834 u64 msr_platform_info; 835 u64 msr_misc_features_enables; 836 837 u64 mcg_cap; 838 u64 mcg_status; 839 u64 mcg_ctl; 840 u64 mcg_ext_ctl; 841 u64 *mce_banks; 842 u64 *mci_ctl2_banks; 843 844 /* Cache MMIO info */ 845 u64 mmio_gva; 846 unsigned mmio_access; 847 gfn_t mmio_gfn; 848 u64 mmio_gen; 849 850 struct kvm_pmu pmu; 851 852 /* used for guest single stepping over the given code position */ 853 unsigned long singlestep_rip; 854 855 bool hyperv_enabled; 856 struct kvm_vcpu_hv *hyperv; 857 struct kvm_vcpu_xen xen; 858 859 cpumask_var_t wbinvd_dirty_mask; 860 861 unsigned long last_retry_eip; 862 unsigned long last_retry_addr; 863 864 struct { 865 bool halted; 866 gfn_t gfns[ASYNC_PF_PER_VCPU]; 867 struct gfn_to_hva_cache data; 868 u64 msr_en_val; /* MSR_KVM_ASYNC_PF_EN */ 869 u64 msr_int_val; /* MSR_KVM_ASYNC_PF_INT */ 870 u16 vec; 871 u32 id; 872 bool send_user_only; 873 u32 host_apf_flags; 874 bool delivery_as_pf_vmexit; 875 bool pageready_pending; 876 } apf; 877 878 /* OSVW MSRs (AMD only) */ 879 struct { 880 u64 length; 881 u64 status; 882 } osvw; 883 884 struct { 885 u64 msr_val; 886 struct gfn_to_hva_cache data; 887 } pv_eoi; 888 889 u64 msr_kvm_poll_control; 890 891 /* 892 * Indicates the guest is trying to write a gfn that contains one or 893 * more of the PTEs used to translate the write itself, i.e. the access 894 * is changing its own translation in the guest page tables. KVM exits 895 * to userspace if emulation of the faulting instruction fails and this 896 * flag is set, as KVM cannot make forward progress. 897 * 898 * If emulation fails for a write to guest page tables, KVM unprotects 899 * (zaps) the shadow page for the target gfn and resumes the guest to 900 * retry the non-emulatable instruction (on hardware). Unprotecting the 901 * gfn doesn't allow forward progress for a self-changing access because 902 * doing so also zaps the translation for the gfn, i.e. retrying the 903 * instruction will hit a !PRESENT fault, which results in a new shadow 904 * page and sends KVM back to square one. 905 */ 906 bool write_fault_to_shadow_pgtable; 907 908 /* set at EPT violation at this point */ 909 unsigned long exit_qualification; 910 911 /* pv related host specific info */ 912 struct { 913 bool pv_unhalted; 914 } pv; 915 916 int pending_ioapic_eoi; 917 int pending_external_vector; 918 919 /* be preempted when it's in kernel-mode(cpl=0) */ 920 bool preempted_in_kernel; 921 922 /* Flush the L1 Data cache for L1TF mitigation on VMENTER */ 923 bool l1tf_flush_l1d; 924 925 /* Host CPU on which VM-entry was most recently attempted */ 926 int last_vmentry_cpu; 927 928 /* AMD MSRC001_0015 Hardware Configuration */ 929 u64 msr_hwcr; 930 931 /* pv related cpuid info */ 932 struct { 933 /* 934 * value of the eax register in the KVM_CPUID_FEATURES CPUID 935 * leaf. 936 */ 937 u32 features; 938 939 /* 940 * indicates whether pv emulation should be disabled if features 941 * are not present in the guest's cpuid 942 */ 943 bool enforce; 944 } pv_cpuid; 945 946 /* Protected Guests */ 947 bool guest_state_protected; 948 949 /* 950 * Set when PDPTS were loaded directly by the userspace without 951 * reading the guest memory 952 */ 953 bool pdptrs_from_userspace; 954 955 #if IS_ENABLED(CONFIG_HYPERV) 956 hpa_t hv_root_tdp; 957 #endif 958 }; 959 960 struct kvm_lpage_info { 961 int disallow_lpage; 962 }; 963 964 struct kvm_arch_memory_slot { 965 struct kvm_rmap_head *rmap[KVM_NR_PAGE_SIZES]; 966 struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1]; 967 unsigned short *gfn_track[KVM_PAGE_TRACK_MAX]; 968 }; 969 970 /* 971 * We use as the mode the number of bits allocated in the LDR for the 972 * logical processor ID. It happens that these are all powers of two. 973 * This makes it is very easy to detect cases where the APICs are 974 * configured for multiple modes; in that case, we cannot use the map and 975 * hence cannot use kvm_irq_delivery_to_apic_fast either. 976 */ 977 #define KVM_APIC_MODE_XAPIC_CLUSTER 4 978 #define KVM_APIC_MODE_XAPIC_FLAT 8 979 #define KVM_APIC_MODE_X2APIC 16 980 981 struct kvm_apic_map { 982 struct rcu_head rcu; 983 u8 mode; 984 u32 max_apic_id; 985 union { 986 struct kvm_lapic *xapic_flat_map[8]; 987 struct kvm_lapic *xapic_cluster_map[16][4]; 988 }; 989 struct kvm_lapic *phys_map[]; 990 }; 991 992 /* Hyper-V synthetic debugger (SynDbg)*/ 993 struct kvm_hv_syndbg { 994 struct { 995 u64 control; 996 u64 status; 997 u64 send_page; 998 u64 recv_page; 999 u64 pending_page; 1000 } control; 1001 u64 options; 1002 }; 1003 1004 /* Current state of Hyper-V TSC page clocksource */ 1005 enum hv_tsc_page_status { 1006 /* TSC page was not set up or disabled */ 1007 HV_TSC_PAGE_UNSET = 0, 1008 /* TSC page MSR was written by the guest, update pending */ 1009 HV_TSC_PAGE_GUEST_CHANGED, 1010 /* TSC page update was triggered from the host side */ 1011 HV_TSC_PAGE_HOST_CHANGED, 1012 /* TSC page was properly set up and is currently active */ 1013 HV_TSC_PAGE_SET, 1014 /* TSC page was set up with an inaccessible GPA */ 1015 HV_TSC_PAGE_BROKEN, 1016 }; 1017 1018 /* Hyper-V emulation context */ 1019 struct kvm_hv { 1020 struct mutex hv_lock; 1021 u64 hv_guest_os_id; 1022 u64 hv_hypercall; 1023 u64 hv_tsc_page; 1024 enum hv_tsc_page_status hv_tsc_page_status; 1025 1026 /* Hyper-v based guest crash (NT kernel bugcheck) parameters */ 1027 u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS]; 1028 u64 hv_crash_ctl; 1029 1030 struct ms_hyperv_tsc_page tsc_ref; 1031 1032 struct idr conn_to_evt; 1033 1034 u64 hv_reenlightenment_control; 1035 u64 hv_tsc_emulation_control; 1036 u64 hv_tsc_emulation_status; 1037 1038 /* How many vCPUs have VP index != vCPU index */ 1039 atomic_t num_mismatched_vp_indexes; 1040 1041 /* 1042 * How many SynICs use 'AutoEOI' feature 1043 * (protected by arch.apicv_update_lock) 1044 */ 1045 unsigned int synic_auto_eoi_used; 1046 1047 struct hv_partition_assist_pg *hv_pa_pg; 1048 struct kvm_hv_syndbg hv_syndbg; 1049 }; 1050 1051 struct msr_bitmap_range { 1052 u32 flags; 1053 u32 nmsrs; 1054 u32 base; 1055 unsigned long *bitmap; 1056 }; 1057 1058 /* Xen emulation context */ 1059 struct kvm_xen { 1060 u32 xen_version; 1061 bool long_mode; 1062 u8 upcall_vector; 1063 struct gfn_to_pfn_cache shinfo_cache; 1064 struct idr evtchn_ports; 1065 unsigned long poll_mask[BITS_TO_LONGS(KVM_MAX_VCPUS)]; 1066 }; 1067 1068 enum kvm_irqchip_mode { 1069 KVM_IRQCHIP_NONE, 1070 KVM_IRQCHIP_KERNEL, /* created with KVM_CREATE_IRQCHIP */ 1071 KVM_IRQCHIP_SPLIT, /* created with KVM_CAP_SPLIT_IRQCHIP */ 1072 }; 1073 1074 struct kvm_x86_msr_filter { 1075 u8 count; 1076 bool default_allow:1; 1077 struct msr_bitmap_range ranges[16]; 1078 }; 1079 1080 enum kvm_apicv_inhibit { 1081 1082 /********************************************************************/ 1083 /* INHIBITs that are relevant to both Intel's APICv and AMD's AVIC. */ 1084 /********************************************************************/ 1085 1086 /* 1087 * APIC acceleration is disabled by a module parameter 1088 * and/or not supported in hardware. 1089 */ 1090 APICV_INHIBIT_REASON_DISABLE, 1091 1092 /* 1093 * APIC acceleration is inhibited because AutoEOI feature is 1094 * being used by a HyperV guest. 1095 */ 1096 APICV_INHIBIT_REASON_HYPERV, 1097 1098 /* 1099 * APIC acceleration is inhibited because the userspace didn't yet 1100 * enable the kernel/split irqchip. 1101 */ 1102 APICV_INHIBIT_REASON_ABSENT, 1103 1104 /* APIC acceleration is inhibited because KVM_GUESTDBG_BLOCKIRQ 1105 * (out of band, debug measure of blocking all interrupts on this vCPU) 1106 * was enabled, to avoid AVIC/APICv bypassing it. 1107 */ 1108 APICV_INHIBIT_REASON_BLOCKIRQ, 1109 1110 /* 1111 * For simplicity, the APIC acceleration is inhibited 1112 * first time either APIC ID or APIC base are changed by the guest 1113 * from their reset values. 1114 */ 1115 APICV_INHIBIT_REASON_APIC_ID_MODIFIED, 1116 APICV_INHIBIT_REASON_APIC_BASE_MODIFIED, 1117 1118 /******************************************************/ 1119 /* INHIBITs that are relevant only to the AMD's AVIC. */ 1120 /******************************************************/ 1121 1122 /* 1123 * AVIC is inhibited on a vCPU because it runs a nested guest. 1124 * 1125 * This is needed because unlike APICv, the peers of this vCPU 1126 * cannot use the doorbell mechanism to signal interrupts via AVIC when 1127 * a vCPU runs nested. 1128 */ 1129 APICV_INHIBIT_REASON_NESTED, 1130 1131 /* 1132 * On SVM, the wait for the IRQ window is implemented with pending vIRQ, 1133 * which cannot be injected when the AVIC is enabled, thus AVIC 1134 * is inhibited while KVM waits for IRQ window. 1135 */ 1136 APICV_INHIBIT_REASON_IRQWIN, 1137 1138 /* 1139 * PIT (i8254) 're-inject' mode, relies on EOI intercept, 1140 * which AVIC doesn't support for edge triggered interrupts. 1141 */ 1142 APICV_INHIBIT_REASON_PIT_REINJ, 1143 1144 /* 1145 * AVIC is disabled because SEV doesn't support it. 1146 */ 1147 APICV_INHIBIT_REASON_SEV, 1148 }; 1149 1150 struct kvm_arch { 1151 unsigned long n_used_mmu_pages; 1152 unsigned long n_requested_mmu_pages; 1153 unsigned long n_max_mmu_pages; 1154 unsigned int indirect_shadow_pages; 1155 u8 mmu_valid_gen; 1156 struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; 1157 struct list_head active_mmu_pages; 1158 struct list_head zapped_obsolete_pages; 1159 struct list_head lpage_disallowed_mmu_pages; 1160 struct kvm_page_track_notifier_node mmu_sp_tracker; 1161 struct kvm_page_track_notifier_head track_notifier_head; 1162 /* 1163 * Protects marking pages unsync during page faults, as TDP MMU page 1164 * faults only take mmu_lock for read. For simplicity, the unsync 1165 * pages lock is always taken when marking pages unsync regardless of 1166 * whether mmu_lock is held for read or write. 1167 */ 1168 spinlock_t mmu_unsync_pages_lock; 1169 1170 struct list_head assigned_dev_head; 1171 struct iommu_domain *iommu_domain; 1172 bool iommu_noncoherent; 1173 #define __KVM_HAVE_ARCH_NONCOHERENT_DMA 1174 atomic_t noncoherent_dma_count; 1175 #define __KVM_HAVE_ARCH_ASSIGNED_DEVICE 1176 atomic_t assigned_device_count; 1177 struct kvm_pic *vpic; 1178 struct kvm_ioapic *vioapic; 1179 struct kvm_pit *vpit; 1180 atomic_t vapics_in_nmi_mode; 1181 struct mutex apic_map_lock; 1182 struct kvm_apic_map __rcu *apic_map; 1183 atomic_t apic_map_dirty; 1184 1185 /* Protects apic_access_memslot_enabled and apicv_inhibit_reasons */ 1186 struct rw_semaphore apicv_update_lock; 1187 1188 bool apic_access_memslot_enabled; 1189 unsigned long apicv_inhibit_reasons; 1190 1191 gpa_t wall_clock; 1192 1193 bool mwait_in_guest; 1194 bool hlt_in_guest; 1195 bool pause_in_guest; 1196 bool cstate_in_guest; 1197 1198 unsigned long irq_sources_bitmap; 1199 s64 kvmclock_offset; 1200 1201 /* 1202 * This also protects nr_vcpus_matched_tsc which is read from a 1203 * preemption-disabled region, so it must be a raw spinlock. 1204 */ 1205 raw_spinlock_t tsc_write_lock; 1206 u64 last_tsc_nsec; 1207 u64 last_tsc_write; 1208 u32 last_tsc_khz; 1209 u64 last_tsc_offset; 1210 u64 cur_tsc_nsec; 1211 u64 cur_tsc_write; 1212 u64 cur_tsc_offset; 1213 u64 cur_tsc_generation; 1214 int nr_vcpus_matched_tsc; 1215 1216 u32 default_tsc_khz; 1217 1218 seqcount_raw_spinlock_t pvclock_sc; 1219 bool use_master_clock; 1220 u64 master_kernel_ns; 1221 u64 master_cycle_now; 1222 struct delayed_work kvmclock_update_work; 1223 struct delayed_work kvmclock_sync_work; 1224 1225 struct kvm_xen_hvm_config xen_hvm_config; 1226 1227 /* reads protected by irq_srcu, writes by irq_lock */ 1228 struct hlist_head mask_notifier_list; 1229 1230 struct kvm_hv hyperv; 1231 struct kvm_xen xen; 1232 1233 bool backwards_tsc_observed; 1234 bool boot_vcpu_runs_old_kvmclock; 1235 u32 bsp_vcpu_id; 1236 1237 u64 disabled_quirks; 1238 int cpu_dirty_logging_count; 1239 1240 enum kvm_irqchip_mode irqchip_mode; 1241 u8 nr_reserved_ioapic_pins; 1242 1243 bool disabled_lapic_found; 1244 1245 bool x2apic_format; 1246 bool x2apic_broadcast_quirk_disabled; 1247 1248 bool guest_can_read_msr_platform_info; 1249 bool exception_payload_enabled; 1250 1251 bool triple_fault_event; 1252 1253 bool bus_lock_detection_enabled; 1254 bool enable_pmu; 1255 1256 u32 notify_window; 1257 u32 notify_vmexit_flags; 1258 /* 1259 * If exit_on_emulation_error is set, and the in-kernel instruction 1260 * emulator fails to emulate an instruction, allow userspace 1261 * the opportunity to look at it. 1262 */ 1263 bool exit_on_emulation_error; 1264 1265 /* Deflect RDMSR and WRMSR to user space when they trigger a #GP */ 1266 u32 user_space_msr_mask; 1267 struct kvm_x86_msr_filter __rcu *msr_filter; 1268 1269 u32 hypercall_exit_enabled; 1270 1271 /* Guest can access the SGX PROVISIONKEY. */ 1272 bool sgx_provisioning_allowed; 1273 1274 struct kvm_pmu_event_filter __rcu *pmu_event_filter; 1275 struct task_struct *nx_lpage_recovery_thread; 1276 1277 #ifdef CONFIG_X86_64 1278 /* 1279 * Whether the TDP MMU is enabled for this VM. This contains a 1280 * snapshot of the TDP MMU module parameter from when the VM was 1281 * created and remains unchanged for the life of the VM. If this is 1282 * true, TDP MMU handler functions will run for various MMU 1283 * operations. 1284 */ 1285 bool tdp_mmu_enabled; 1286 1287 /* 1288 * List of kvm_mmu_page structs being used as roots. 1289 * All kvm_mmu_page structs in the list should have 1290 * tdp_mmu_page set. 1291 * 1292 * For reads, this list is protected by: 1293 * the MMU lock in read mode + RCU or 1294 * the MMU lock in write mode 1295 * 1296 * For writes, this list is protected by: 1297 * the MMU lock in read mode + the tdp_mmu_pages_lock or 1298 * the MMU lock in write mode 1299 * 1300 * Roots will remain in the list until their tdp_mmu_root_count 1301 * drops to zero, at which point the thread that decremented the 1302 * count to zero should removed the root from the list and clean 1303 * it up, freeing the root after an RCU grace period. 1304 */ 1305 struct list_head tdp_mmu_roots; 1306 1307 /* 1308 * List of kvm_mmu_page structs not being used as roots. 1309 * All kvm_mmu_page structs in the list should have 1310 * tdp_mmu_page set and a tdp_mmu_root_count of 0. 1311 */ 1312 struct list_head tdp_mmu_pages; 1313 1314 /* 1315 * Protects accesses to the following fields when the MMU lock 1316 * is held in read mode: 1317 * - tdp_mmu_roots (above) 1318 * - tdp_mmu_pages (above) 1319 * - the link field of kvm_mmu_page structs used by the TDP MMU 1320 * - lpage_disallowed_mmu_pages 1321 * - the lpage_disallowed_link field of kvm_mmu_page structs used 1322 * by the TDP MMU 1323 * It is acceptable, but not necessary, to acquire this lock when 1324 * the thread holds the MMU lock in write mode. 1325 */ 1326 spinlock_t tdp_mmu_pages_lock; 1327 struct workqueue_struct *tdp_mmu_zap_wq; 1328 #endif /* CONFIG_X86_64 */ 1329 1330 /* 1331 * If set, at least one shadow root has been allocated. This flag 1332 * is used as one input when determining whether certain memslot 1333 * related allocations are necessary. 1334 */ 1335 bool shadow_root_allocated; 1336 1337 #if IS_ENABLED(CONFIG_HYPERV) 1338 hpa_t hv_root_tdp; 1339 spinlock_t hv_root_tdp_lock; 1340 #endif 1341 /* 1342 * VM-scope maximum vCPU ID. Used to determine the size of structures 1343 * that increase along with the maximum vCPU ID, in which case, using 1344 * the global KVM_MAX_VCPU_IDS may lead to significant memory waste. 1345 */ 1346 u32 max_vcpu_ids; 1347 1348 bool disable_nx_huge_pages; 1349 1350 /* 1351 * Memory caches used to allocate shadow pages when performing eager 1352 * page splitting. No need for a shadowed_info_cache since eager page 1353 * splitting only allocates direct shadow pages. 1354 * 1355 * Protected by kvm->slots_lock. 1356 */ 1357 struct kvm_mmu_memory_cache split_shadow_page_cache; 1358 struct kvm_mmu_memory_cache split_page_header_cache; 1359 1360 /* 1361 * Memory cache used to allocate pte_list_desc structs while splitting 1362 * huge pages. In the worst case, to split one huge page, 512 1363 * pte_list_desc structs are needed to add each lower level leaf sptep 1364 * to the rmap plus 1 to extend the parent_ptes rmap of the lower level 1365 * page table. 1366 * 1367 * Protected by kvm->slots_lock. 1368 */ 1369 #define SPLIT_DESC_CACHE_MIN_NR_OBJECTS (SPTE_ENT_PER_PAGE + 1) 1370 struct kvm_mmu_memory_cache split_desc_cache; 1371 }; 1372 1373 struct kvm_vm_stat { 1374 struct kvm_vm_stat_generic generic; 1375 u64 mmu_shadow_zapped; 1376 u64 mmu_pte_write; 1377 u64 mmu_pde_zapped; 1378 u64 mmu_flooded; 1379 u64 mmu_recycled; 1380 u64 mmu_cache_miss; 1381 u64 mmu_unsync; 1382 union { 1383 struct { 1384 atomic64_t pages_4k; 1385 atomic64_t pages_2m; 1386 atomic64_t pages_1g; 1387 }; 1388 atomic64_t pages[KVM_NR_PAGE_SIZES]; 1389 }; 1390 u64 nx_lpage_splits; 1391 u64 max_mmu_page_hash_collisions; 1392 u64 max_mmu_rmap_size; 1393 }; 1394 1395 struct kvm_vcpu_stat { 1396 struct kvm_vcpu_stat_generic generic; 1397 u64 pf_taken; 1398 u64 pf_fixed; 1399 u64 pf_emulate; 1400 u64 pf_spurious; 1401 u64 pf_fast; 1402 u64 pf_mmio_spte_created; 1403 u64 pf_guest; 1404 u64 tlb_flush; 1405 u64 invlpg; 1406 1407 u64 exits; 1408 u64 io_exits; 1409 u64 mmio_exits; 1410 u64 signal_exits; 1411 u64 irq_window_exits; 1412 u64 nmi_window_exits; 1413 u64 l1d_flush; 1414 u64 halt_exits; 1415 u64 request_irq_exits; 1416 u64 irq_exits; 1417 u64 host_state_reload; 1418 u64 fpu_reload; 1419 u64 insn_emulation; 1420 u64 insn_emulation_fail; 1421 u64 hypercalls; 1422 u64 irq_injections; 1423 u64 nmi_injections; 1424 u64 req_event; 1425 u64 nested_run; 1426 u64 directed_yield_attempted; 1427 u64 directed_yield_successful; 1428 u64 preemption_reported; 1429 u64 preemption_other; 1430 u64 guest_mode; 1431 u64 notify_window_exits; 1432 }; 1433 1434 struct x86_instruction_info; 1435 1436 struct msr_data { 1437 bool host_initiated; 1438 u32 index; 1439 u64 data; 1440 }; 1441 1442 struct kvm_lapic_irq { 1443 u32 vector; 1444 u16 delivery_mode; 1445 u16 dest_mode; 1446 bool level; 1447 u16 trig_mode; 1448 u32 shorthand; 1449 u32 dest_id; 1450 bool msi_redir_hint; 1451 }; 1452 1453 static inline u16 kvm_lapic_irq_dest_mode(bool dest_mode_logical) 1454 { 1455 return dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL; 1456 } 1457 1458 struct kvm_x86_ops { 1459 const char *name; 1460 1461 int (*hardware_enable)(void); 1462 void (*hardware_disable)(void); 1463 void (*hardware_unsetup)(void); 1464 bool (*has_emulated_msr)(struct kvm *kvm, u32 index); 1465 void (*vcpu_after_set_cpuid)(struct kvm_vcpu *vcpu); 1466 1467 unsigned int vm_size; 1468 int (*vm_init)(struct kvm *kvm); 1469 void (*vm_destroy)(struct kvm *kvm); 1470 1471 /* Create, but do not attach this VCPU */ 1472 int (*vcpu_precreate)(struct kvm *kvm); 1473 int (*vcpu_create)(struct kvm_vcpu *vcpu); 1474 void (*vcpu_free)(struct kvm_vcpu *vcpu); 1475 void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event); 1476 1477 void (*prepare_switch_to_guest)(struct kvm_vcpu *vcpu); 1478 void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); 1479 void (*vcpu_put)(struct kvm_vcpu *vcpu); 1480 1481 void (*update_exception_bitmap)(struct kvm_vcpu *vcpu); 1482 int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); 1483 int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); 1484 u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg); 1485 void (*get_segment)(struct kvm_vcpu *vcpu, 1486 struct kvm_segment *var, int seg); 1487 int (*get_cpl)(struct kvm_vcpu *vcpu); 1488 void (*set_segment)(struct kvm_vcpu *vcpu, 1489 struct kvm_segment *var, int seg); 1490 void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); 1491 void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); 1492 void (*post_set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); 1493 bool (*is_valid_cr4)(struct kvm_vcpu *vcpu, unsigned long cr0); 1494 void (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); 1495 int (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); 1496 void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1497 void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1498 void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1499 void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 1500 void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu); 1501 void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value); 1502 void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); 1503 unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); 1504 void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); 1505 bool (*get_if_flag)(struct kvm_vcpu *vcpu); 1506 1507 void (*flush_tlb_all)(struct kvm_vcpu *vcpu); 1508 void (*flush_tlb_current)(struct kvm_vcpu *vcpu); 1509 int (*tlb_remote_flush)(struct kvm *kvm); 1510 int (*tlb_remote_flush_with_range)(struct kvm *kvm, 1511 struct kvm_tlb_range *range); 1512 1513 /* 1514 * Flush any TLB entries associated with the given GVA. 1515 * Does not need to flush GPA->HPA mappings. 1516 * Can potentially get non-canonical addresses through INVLPGs, which 1517 * the implementation may choose to ignore if appropriate. 1518 */ 1519 void (*flush_tlb_gva)(struct kvm_vcpu *vcpu, gva_t addr); 1520 1521 /* 1522 * Flush any TLB entries created by the guest. Like tlb_flush_gva(), 1523 * does not need to flush GPA->HPA mappings. 1524 */ 1525 void (*flush_tlb_guest)(struct kvm_vcpu *vcpu); 1526 1527 int (*vcpu_pre_run)(struct kvm_vcpu *vcpu); 1528 enum exit_fastpath_completion (*vcpu_run)(struct kvm_vcpu *vcpu); 1529 int (*handle_exit)(struct kvm_vcpu *vcpu, 1530 enum exit_fastpath_completion exit_fastpath); 1531 int (*skip_emulated_instruction)(struct kvm_vcpu *vcpu); 1532 void (*update_emulated_instruction)(struct kvm_vcpu *vcpu); 1533 void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); 1534 u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu); 1535 void (*patch_hypercall)(struct kvm_vcpu *vcpu, 1536 unsigned char *hypercall_addr); 1537 void (*inject_irq)(struct kvm_vcpu *vcpu, bool reinjected); 1538 void (*inject_nmi)(struct kvm_vcpu *vcpu); 1539 void (*inject_exception)(struct kvm_vcpu *vcpu); 1540 void (*cancel_injection)(struct kvm_vcpu *vcpu); 1541 int (*interrupt_allowed)(struct kvm_vcpu *vcpu, bool for_injection); 1542 int (*nmi_allowed)(struct kvm_vcpu *vcpu, bool for_injection); 1543 bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); 1544 void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked); 1545 void (*enable_nmi_window)(struct kvm_vcpu *vcpu); 1546 void (*enable_irq_window)(struct kvm_vcpu *vcpu); 1547 void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr); 1548 bool (*check_apicv_inhibit_reasons)(enum kvm_apicv_inhibit reason); 1549 void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu); 1550 void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr); 1551 void (*hwapic_isr_update)(int isr); 1552 bool (*guest_apic_has_interrupt)(struct kvm_vcpu *vcpu); 1553 void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); 1554 void (*set_virtual_apic_mode)(struct kvm_vcpu *vcpu); 1555 void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu); 1556 void (*deliver_interrupt)(struct kvm_lapic *apic, int delivery_mode, 1557 int trig_mode, int vector); 1558 int (*sync_pir_to_irr)(struct kvm_vcpu *vcpu); 1559 int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); 1560 int (*set_identity_map_addr)(struct kvm *kvm, u64 ident_addr); 1561 u8 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio); 1562 1563 void (*load_mmu_pgd)(struct kvm_vcpu *vcpu, hpa_t root_hpa, 1564 int root_level); 1565 1566 bool (*has_wbinvd_exit)(void); 1567 1568 u64 (*get_l2_tsc_offset)(struct kvm_vcpu *vcpu); 1569 u64 (*get_l2_tsc_multiplier)(struct kvm_vcpu *vcpu); 1570 void (*write_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset); 1571 void (*write_tsc_multiplier)(struct kvm_vcpu *vcpu, u64 multiplier); 1572 1573 /* 1574 * Retrieve somewhat arbitrary exit information. Intended to 1575 * be used only from within tracepoints or error paths. 1576 */ 1577 void (*get_exit_info)(struct kvm_vcpu *vcpu, u32 *reason, 1578 u64 *info1, u64 *info2, 1579 u32 *exit_int_info, u32 *exit_int_info_err_code); 1580 1581 int (*check_intercept)(struct kvm_vcpu *vcpu, 1582 struct x86_instruction_info *info, 1583 enum x86_intercept_stage stage, 1584 struct x86_exception *exception); 1585 void (*handle_exit_irqoff)(struct kvm_vcpu *vcpu); 1586 1587 void (*request_immediate_exit)(struct kvm_vcpu *vcpu); 1588 1589 void (*sched_in)(struct kvm_vcpu *kvm, int cpu); 1590 1591 /* 1592 * Size of the CPU's dirty log buffer, i.e. VMX's PML buffer. A zero 1593 * value indicates CPU dirty logging is unsupported or disabled. 1594 */ 1595 int cpu_dirty_log_size; 1596 void (*update_cpu_dirty_logging)(struct kvm_vcpu *vcpu); 1597 1598 const struct kvm_x86_nested_ops *nested_ops; 1599 1600 void (*vcpu_blocking)(struct kvm_vcpu *vcpu); 1601 void (*vcpu_unblocking)(struct kvm_vcpu *vcpu); 1602 1603 int (*pi_update_irte)(struct kvm *kvm, unsigned int host_irq, 1604 uint32_t guest_irq, bool set); 1605 void (*pi_start_assignment)(struct kvm *kvm); 1606 void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu); 1607 bool (*dy_apicv_has_pending_interrupt)(struct kvm_vcpu *vcpu); 1608 1609 int (*set_hv_timer)(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, 1610 bool *expired); 1611 void (*cancel_hv_timer)(struct kvm_vcpu *vcpu); 1612 1613 void (*setup_mce)(struct kvm_vcpu *vcpu); 1614 1615 int (*smi_allowed)(struct kvm_vcpu *vcpu, bool for_injection); 1616 int (*enter_smm)(struct kvm_vcpu *vcpu, char *smstate); 1617 int (*leave_smm)(struct kvm_vcpu *vcpu, const char *smstate); 1618 void (*enable_smi_window)(struct kvm_vcpu *vcpu); 1619 1620 int (*mem_enc_ioctl)(struct kvm *kvm, void __user *argp); 1621 int (*mem_enc_register_region)(struct kvm *kvm, struct kvm_enc_region *argp); 1622 int (*mem_enc_unregister_region)(struct kvm *kvm, struct kvm_enc_region *argp); 1623 int (*vm_copy_enc_context_from)(struct kvm *kvm, unsigned int source_fd); 1624 int (*vm_move_enc_context_from)(struct kvm *kvm, unsigned int source_fd); 1625 void (*guest_memory_reclaimed)(struct kvm *kvm); 1626 1627 int (*get_msr_feature)(struct kvm_msr_entry *entry); 1628 1629 bool (*can_emulate_instruction)(struct kvm_vcpu *vcpu, int emul_type, 1630 void *insn, int insn_len); 1631 1632 bool (*apic_init_signal_blocked)(struct kvm_vcpu *vcpu); 1633 int (*enable_direct_tlbflush)(struct kvm_vcpu *vcpu); 1634 1635 void (*migrate_timers)(struct kvm_vcpu *vcpu); 1636 void (*msr_filter_changed)(struct kvm_vcpu *vcpu); 1637 int (*complete_emulated_msr)(struct kvm_vcpu *vcpu, int err); 1638 1639 void (*vcpu_deliver_sipi_vector)(struct kvm_vcpu *vcpu, u8 vector); 1640 1641 /* 1642 * Returns vCPU specific APICv inhibit reasons 1643 */ 1644 unsigned long (*vcpu_get_apicv_inhibit_reasons)(struct kvm_vcpu *vcpu); 1645 }; 1646 1647 struct kvm_x86_nested_ops { 1648 void (*leave_nested)(struct kvm_vcpu *vcpu); 1649 bool (*is_exception_vmexit)(struct kvm_vcpu *vcpu, u8 vector, 1650 u32 error_code); 1651 int (*check_events)(struct kvm_vcpu *vcpu); 1652 bool (*has_events)(struct kvm_vcpu *vcpu); 1653 void (*triple_fault)(struct kvm_vcpu *vcpu); 1654 int (*get_state)(struct kvm_vcpu *vcpu, 1655 struct kvm_nested_state __user *user_kvm_nested_state, 1656 unsigned user_data_size); 1657 int (*set_state)(struct kvm_vcpu *vcpu, 1658 struct kvm_nested_state __user *user_kvm_nested_state, 1659 struct kvm_nested_state *kvm_state); 1660 bool (*get_nested_state_pages)(struct kvm_vcpu *vcpu); 1661 int (*write_log_dirty)(struct kvm_vcpu *vcpu, gpa_t l2_gpa); 1662 1663 int (*enable_evmcs)(struct kvm_vcpu *vcpu, 1664 uint16_t *vmcs_version); 1665 uint16_t (*get_evmcs_version)(struct kvm_vcpu *vcpu); 1666 }; 1667 1668 struct kvm_x86_init_ops { 1669 int (*cpu_has_kvm_support)(void); 1670 int (*disabled_by_bios)(void); 1671 int (*check_processor_compatibility)(void); 1672 int (*hardware_setup)(void); 1673 unsigned int (*handle_intel_pt_intr)(void); 1674 1675 struct kvm_x86_ops *runtime_ops; 1676 struct kvm_pmu_ops *pmu_ops; 1677 }; 1678 1679 struct kvm_arch_async_pf { 1680 u32 token; 1681 gfn_t gfn; 1682 unsigned long cr3; 1683 bool direct_map; 1684 }; 1685 1686 extern u32 __read_mostly kvm_nr_uret_msrs; 1687 extern u64 __read_mostly host_efer; 1688 extern bool __read_mostly allow_smaller_maxphyaddr; 1689 extern bool __read_mostly enable_apicv; 1690 extern struct kvm_x86_ops kvm_x86_ops; 1691 1692 #define KVM_X86_OP(func) \ 1693 DECLARE_STATIC_CALL(kvm_x86_##func, *(((struct kvm_x86_ops *)0)->func)); 1694 #define KVM_X86_OP_OPTIONAL KVM_X86_OP 1695 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP 1696 #include <asm/kvm-x86-ops.h> 1697 1698 #define __KVM_HAVE_ARCH_VM_ALLOC 1699 static inline struct kvm *kvm_arch_alloc_vm(void) 1700 { 1701 return __vmalloc(kvm_x86_ops.vm_size, GFP_KERNEL_ACCOUNT | __GFP_ZERO); 1702 } 1703 1704 #define __KVM_HAVE_ARCH_VM_FREE 1705 void kvm_arch_free_vm(struct kvm *kvm); 1706 1707 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLB 1708 static inline int kvm_arch_flush_remote_tlb(struct kvm *kvm) 1709 { 1710 if (kvm_x86_ops.tlb_remote_flush && 1711 !static_call(kvm_x86_tlb_remote_flush)(kvm)) 1712 return 0; 1713 else 1714 return -ENOTSUPP; 1715 } 1716 1717 #define kvm_arch_pmi_in_guest(vcpu) \ 1718 ((vcpu) && (vcpu)->arch.handling_intr_from_guest) 1719 1720 void __init kvm_mmu_x86_module_init(void); 1721 int kvm_mmu_vendor_module_init(void); 1722 void kvm_mmu_vendor_module_exit(void); 1723 1724 void kvm_mmu_destroy(struct kvm_vcpu *vcpu); 1725 int kvm_mmu_create(struct kvm_vcpu *vcpu); 1726 int kvm_mmu_init_vm(struct kvm *kvm); 1727 void kvm_mmu_uninit_vm(struct kvm *kvm); 1728 1729 void kvm_mmu_after_set_cpuid(struct kvm_vcpu *vcpu); 1730 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu); 1731 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, 1732 const struct kvm_memory_slot *memslot, 1733 int start_level); 1734 void kvm_mmu_slot_try_split_huge_pages(struct kvm *kvm, 1735 const struct kvm_memory_slot *memslot, 1736 int target_level); 1737 void kvm_mmu_try_split_huge_pages(struct kvm *kvm, 1738 const struct kvm_memory_slot *memslot, 1739 u64 start, u64 end, 1740 int target_level); 1741 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, 1742 const struct kvm_memory_slot *memslot); 1743 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, 1744 const struct kvm_memory_slot *memslot); 1745 void kvm_mmu_zap_all(struct kvm *kvm); 1746 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen); 1747 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long kvm_nr_mmu_pages); 1748 1749 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3); 1750 1751 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 1752 const void *val, int bytes); 1753 1754 struct kvm_irq_mask_notifier { 1755 void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked); 1756 int irq; 1757 struct hlist_node link; 1758 }; 1759 1760 void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq, 1761 struct kvm_irq_mask_notifier *kimn); 1762 void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq, 1763 struct kvm_irq_mask_notifier *kimn); 1764 void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin, 1765 bool mask); 1766 1767 extern bool tdp_enabled; 1768 1769 u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu); 1770 1771 /* 1772 * EMULTYPE_NO_DECODE - Set when re-emulating an instruction (after completing 1773 * userspace I/O) to indicate that the emulation context 1774 * should be reused as is, i.e. skip initialization of 1775 * emulation context, instruction fetch and decode. 1776 * 1777 * EMULTYPE_TRAP_UD - Set when emulating an intercepted #UD from hardware. 1778 * Indicates that only select instructions (tagged with 1779 * EmulateOnUD) should be emulated (to minimize the emulator 1780 * attack surface). See also EMULTYPE_TRAP_UD_FORCED. 1781 * 1782 * EMULTYPE_SKIP - Set when emulating solely to skip an instruction, i.e. to 1783 * decode the instruction length. For use *only* by 1784 * kvm_x86_ops.skip_emulated_instruction() implementations if 1785 * EMULTYPE_COMPLETE_USER_EXIT is not set. 1786 * 1787 * EMULTYPE_ALLOW_RETRY_PF - Set when the emulator should resume the guest to 1788 * retry native execution under certain conditions, 1789 * Can only be set in conjunction with EMULTYPE_PF. 1790 * 1791 * EMULTYPE_TRAP_UD_FORCED - Set when emulating an intercepted #UD that was 1792 * triggered by KVM's magic "force emulation" prefix, 1793 * which is opt in via module param (off by default). 1794 * Bypasses EmulateOnUD restriction despite emulating 1795 * due to an intercepted #UD (see EMULTYPE_TRAP_UD). 1796 * Used to test the full emulator from userspace. 1797 * 1798 * EMULTYPE_VMWARE_GP - Set when emulating an intercepted #GP for VMware 1799 * backdoor emulation, which is opt in via module param. 1800 * VMware backdoor emulation handles select instructions 1801 * and reinjects the #GP for all other cases. 1802 * 1803 * EMULTYPE_PF - Set when emulating MMIO by way of an intercepted #PF, in which 1804 * case the CR2/GPA value pass on the stack is valid. 1805 * 1806 * EMULTYPE_COMPLETE_USER_EXIT - Set when the emulator should update interruptibility 1807 * state and inject single-step #DBs after skipping 1808 * an instruction (after completing userspace I/O). 1809 */ 1810 #define EMULTYPE_NO_DECODE (1 << 0) 1811 #define EMULTYPE_TRAP_UD (1 << 1) 1812 #define EMULTYPE_SKIP (1 << 2) 1813 #define EMULTYPE_ALLOW_RETRY_PF (1 << 3) 1814 #define EMULTYPE_TRAP_UD_FORCED (1 << 4) 1815 #define EMULTYPE_VMWARE_GP (1 << 5) 1816 #define EMULTYPE_PF (1 << 6) 1817 #define EMULTYPE_COMPLETE_USER_EXIT (1 << 7) 1818 1819 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type); 1820 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 1821 void *insn, int insn_len); 1822 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, 1823 u64 *data, u8 ndata); 1824 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu); 1825 1826 void kvm_enable_efer_bits(u64); 1827 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer); 1828 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, bool host_initiated); 1829 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data); 1830 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data); 1831 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu); 1832 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu); 1833 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu); 1834 int kvm_emulate_invd(struct kvm_vcpu *vcpu); 1835 int kvm_emulate_mwait(struct kvm_vcpu *vcpu); 1836 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu); 1837 int kvm_emulate_monitor(struct kvm_vcpu *vcpu); 1838 1839 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in); 1840 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu); 1841 int kvm_emulate_halt(struct kvm_vcpu *vcpu); 1842 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu); 1843 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu); 1844 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu); 1845 1846 void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 1847 int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg); 1848 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); 1849 1850 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 1851 int reason, bool has_error_code, u32 error_code); 1852 1853 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0); 1854 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4); 1855 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 1856 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); 1857 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 1858 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); 1859 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); 1860 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); 1861 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); 1862 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); 1863 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu); 1864 1865 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); 1866 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); 1867 1868 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu); 1869 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 1870 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu); 1871 1872 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); 1873 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); 1874 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, unsigned long payload); 1875 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr); 1876 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); 1877 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); 1878 void kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, 1879 struct x86_exception *fault); 1880 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); 1881 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr); 1882 1883 static inline int __kvm_irq_line_state(unsigned long *irq_state, 1884 int irq_source_id, int level) 1885 { 1886 /* Logical OR for level trig interrupt */ 1887 if (level) 1888 __set_bit(irq_source_id, irq_state); 1889 else 1890 __clear_bit(irq_source_id, irq_state); 1891 1892 return !!(*irq_state); 1893 } 1894 1895 #define KVM_MMU_ROOT_CURRENT BIT(0) 1896 #define KVM_MMU_ROOT_PREVIOUS(i) BIT(1+i) 1897 #define KVM_MMU_ROOTS_ALL (~0UL) 1898 1899 int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level); 1900 void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id); 1901 1902 void kvm_inject_nmi(struct kvm_vcpu *vcpu); 1903 1904 void kvm_update_dr7(struct kvm_vcpu *vcpu); 1905 1906 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn); 1907 void kvm_mmu_free_roots(struct kvm *kvm, struct kvm_mmu *mmu, 1908 ulong roots_to_free); 1909 void kvm_mmu_free_guest_mode_roots(struct kvm *kvm, struct kvm_mmu *mmu); 1910 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 1911 struct x86_exception *exception); 1912 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 1913 struct x86_exception *exception); 1914 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 1915 struct x86_exception *exception); 1916 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 1917 struct x86_exception *exception); 1918 1919 bool kvm_apicv_activated(struct kvm *kvm); 1920 bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu); 1921 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu); 1922 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm, 1923 enum kvm_apicv_inhibit reason, bool set); 1924 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm, 1925 enum kvm_apicv_inhibit reason, bool set); 1926 1927 static inline void kvm_set_apicv_inhibit(struct kvm *kvm, 1928 enum kvm_apicv_inhibit reason) 1929 { 1930 kvm_set_or_clear_apicv_inhibit(kvm, reason, true); 1931 } 1932 1933 static inline void kvm_clear_apicv_inhibit(struct kvm *kvm, 1934 enum kvm_apicv_inhibit reason) 1935 { 1936 kvm_set_or_clear_apicv_inhibit(kvm, reason, false); 1937 } 1938 1939 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); 1940 1941 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code, 1942 void *insn, int insn_len); 1943 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva); 1944 void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 1945 gva_t gva, hpa_t root_hpa); 1946 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid); 1947 void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd); 1948 1949 void kvm_configure_mmu(bool enable_tdp, int tdp_forced_root_level, 1950 int tdp_max_root_level, int tdp_huge_page_level); 1951 1952 static inline u16 kvm_read_ldt(void) 1953 { 1954 u16 ldt; 1955 asm("sldt %0" : "=g"(ldt)); 1956 return ldt; 1957 } 1958 1959 static inline void kvm_load_ldt(u16 sel) 1960 { 1961 asm("lldt %0" : : "rm"(sel)); 1962 } 1963 1964 #ifdef CONFIG_X86_64 1965 static inline unsigned long read_msr(unsigned long msr) 1966 { 1967 u64 value; 1968 1969 rdmsrl(msr, value); 1970 return value; 1971 } 1972 #endif 1973 1974 static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) 1975 { 1976 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); 1977 } 1978 1979 #define TSS_IOPB_BASE_OFFSET 0x66 1980 #define TSS_BASE_SIZE 0x68 1981 #define TSS_IOPB_SIZE (65536 / 8) 1982 #define TSS_REDIRECTION_SIZE (256 / 8) 1983 #define RMODE_TSS_SIZE \ 1984 (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1) 1985 1986 enum { 1987 TASK_SWITCH_CALL = 0, 1988 TASK_SWITCH_IRET = 1, 1989 TASK_SWITCH_JMP = 2, 1990 TASK_SWITCH_GATE = 3, 1991 }; 1992 1993 #define HF_GIF_MASK (1 << 0) 1994 #define HF_NMI_MASK (1 << 3) 1995 #define HF_IRET_MASK (1 << 4) 1996 #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */ 1997 #define HF_SMM_MASK (1 << 6) 1998 #define HF_SMM_INSIDE_NMI_MASK (1 << 7) 1999 2000 #define __KVM_VCPU_MULTIPLE_ADDRESS_SPACE 2001 #define KVM_ADDRESS_SPACE_NUM 2 2002 2003 #define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0) 2004 #define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm) 2005 2006 #define KVM_ARCH_WANT_MMU_NOTIFIER 2007 2008 int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v); 2009 int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); 2010 int kvm_cpu_has_extint(struct kvm_vcpu *v); 2011 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu); 2012 int kvm_cpu_get_interrupt(struct kvm_vcpu *v); 2013 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event); 2014 2015 int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low, 2016 unsigned long ipi_bitmap_high, u32 min, 2017 unsigned long icr, int op_64_bit); 2018 2019 int kvm_add_user_return_msr(u32 msr); 2020 int kvm_find_user_return_msr(u32 msr); 2021 int kvm_set_user_return_msr(unsigned index, u64 val, u64 mask); 2022 2023 static inline bool kvm_is_supported_user_return_msr(u32 msr) 2024 { 2025 return kvm_find_user_return_msr(msr) >= 0; 2026 } 2027 2028 u64 kvm_scale_tsc(u64 tsc, u64 ratio); 2029 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc); 2030 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier); 2031 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier); 2032 2033 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu); 2034 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); 2035 2036 void kvm_make_scan_ioapic_request(struct kvm *kvm); 2037 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, 2038 unsigned long *vcpu_bitmap); 2039 2040 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 2041 struct kvm_async_pf *work); 2042 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 2043 struct kvm_async_pf *work); 2044 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, 2045 struct kvm_async_pf *work); 2046 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu); 2047 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu); 2048 extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn); 2049 2050 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu); 2051 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err); 2052 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu); 2053 2054 void __user *__x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, 2055 u32 size); 2056 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu); 2057 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu); 2058 2059 bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq, 2060 struct kvm_vcpu **dest_vcpu); 2061 2062 void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, 2063 struct kvm_lapic_irq *irq); 2064 2065 static inline bool kvm_irq_is_postable(struct kvm_lapic_irq *irq) 2066 { 2067 /* We can only post Fixed and LowPrio IRQs */ 2068 return (irq->delivery_mode == APIC_DM_FIXED || 2069 irq->delivery_mode == APIC_DM_LOWEST); 2070 } 2071 2072 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) 2073 { 2074 static_call_cond(kvm_x86_vcpu_blocking)(vcpu); 2075 } 2076 2077 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) 2078 { 2079 static_call_cond(kvm_x86_vcpu_unblocking)(vcpu); 2080 } 2081 2082 static inline int kvm_cpu_get_apicid(int mps_cpu) 2083 { 2084 #ifdef CONFIG_X86_LOCAL_APIC 2085 return default_cpu_present_to_apicid(mps_cpu); 2086 #else 2087 WARN_ON_ONCE(1); 2088 return BAD_APICID; 2089 #endif 2090 } 2091 2092 #define put_smstate(type, buf, offset, val) \ 2093 *(type *)((buf) + (offset) - 0x7e00) = val 2094 2095 #define GET_SMSTATE(type, buf, offset) \ 2096 (*(type *)((buf) + (offset) - 0x7e00)) 2097 2098 int kvm_cpu_dirty_log_size(void); 2099 2100 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages); 2101 2102 #define KVM_CLOCK_VALID_FLAGS \ 2103 (KVM_CLOCK_TSC_STABLE | KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC) 2104 2105 #define KVM_X86_VALID_QUIRKS \ 2106 (KVM_X86_QUIRK_LINT0_REENABLED | \ 2107 KVM_X86_QUIRK_CD_NW_CLEARED | \ 2108 KVM_X86_QUIRK_LAPIC_MMIO_HOLE | \ 2109 KVM_X86_QUIRK_OUT_7E_INC_RIP | \ 2110 KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT | \ 2111 KVM_X86_QUIRK_FIX_HYPERCALL_INSN | \ 2112 KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS) 2113 2114 #endif /* _ASM_X86_KVM_HOST_H */ 2115